15 	intel_de_rmw(dev_priv, SOUTH_CHICKEN2, 0, FDI_MPHY_IOSFSB_RESET_CTL);  in lpt_fdi_reset_mphy()
21 	intel_de_rmw(dev_priv, SOUTH_CHICKEN2, FDI_MPHY_IOSFSB_RESET_CTL, 0);  in lpt_fdi_reset_mphy()
24 			 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))  in lpt_fdi_reset_mphy()
35 	tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);  in lpt_fdi_program_mphy()
36 	tmp &= ~(0xFF << 24);  in lpt_fdi_program_mphy()
37 	tmp |= (0x12 << 24);  in lpt_fdi_program_mphy()
38 	intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);  in lpt_fdi_program_mphy()
40 	tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);  in lpt_fdi_program_mphy()
42 	intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);  in lpt_fdi_program_mphy()
44 	tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);  in lpt_fdi_program_mphy()
46 	intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);  in lpt_fdi_program_mphy()
48 	tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);  in lpt_fdi_program_mphy()
50 	intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);  in lpt_fdi_program_mphy()
52 	tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);  in lpt_fdi_program_mphy()
54 	intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);  in lpt_fdi_program_mphy()
56 	tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);  in lpt_fdi_program_mphy()
59 	intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);  in lpt_fdi_program_mphy()
61 	tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);  in lpt_fdi_program_mphy()
64 	intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);  in lpt_fdi_program_mphy()
66 	tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);  in lpt_fdi_program_mphy()
67 	tmp &= ~0xFF;  in lpt_fdi_program_mphy()
68 	tmp |= 0x1C;  in lpt_fdi_program_mphy()
69 	intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);  in lpt_fdi_program_mphy()
71 	tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);  in lpt_fdi_program_mphy()
72 	tmp &= ~0xFF;  in lpt_fdi_program_mphy()
73 	tmp |= 0x1C;  in lpt_fdi_program_mphy()
74 	intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);  in lpt_fdi_program_mphy()
76 	tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);  in lpt_fdi_program_mphy()
77 	tmp &= ~(0xFF << 16);  in lpt_fdi_program_mphy()
78 	tmp |= (0x1C << 16);  in lpt_fdi_program_mphy()
79 	intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);  in lpt_fdi_program_mphy()
81 	tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);  in lpt_fdi_program_mphy()
82 	tmp &= ~(0xFF << 16);  in lpt_fdi_program_mphy()
83 	tmp |= (0x1C << 16);  in lpt_fdi_program_mphy()
84 	intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);  in lpt_fdi_program_mphy()
86 	tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);  in lpt_fdi_program_mphy()
88 	intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);  in lpt_fdi_program_mphy()
90 	tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);  in lpt_fdi_program_mphy()
92 	intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);  in lpt_fdi_program_mphy()
94 	tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);  in lpt_fdi_program_mphy()
95 	tmp &= ~(0xF << 28);  in lpt_fdi_program_mphy()
97 	intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);  in lpt_fdi_program_mphy()
99 	tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);  in lpt_fdi_program_mphy()
100 	tmp &= ~(0xF << 28);  in lpt_fdi_program_mphy()
102 	intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);  in lpt_fdi_program_mphy()
128 	memset(p, 0, sizeof(*p));  in iclkip_params_init()
150 	for (p->auxdiv = 0; p->auxdiv < 2; p->auxdiv++) {  in lpt_compute_iclkip()
160 		if (p->divsel <= 0x7f)  in lpt_compute_iclkip()
234 	if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)  in lpt_get_iclkip()
235 		return 0;  in lpt_get_iclkip()
244 		return 0;  in lpt_get_iclkip()
337 	[BEND_IDX( 50)] = 0x3B23,
338 	[BEND_IDX( 45)] = 0x3B23,
339 	[BEND_IDX( 40)] = 0x3C23,
340 	[BEND_IDX( 35)] = 0x3C23,
341 	[BEND_IDX( 30)] = 0x3D23,
342 	[BEND_IDX( 25)] = 0x3D23,
343 	[BEND_IDX( 20)] = 0x3E23,
344 	[BEND_IDX( 15)] = 0x3E23,
345 	[BEND_IDX( 10)] = 0x3F23,
346 	[BEND_IDX(  5)] = 0x3F23,
347 	[BEND_IDX(  0)] = 0x0025,
348 	[BEND_IDX( -5)] = 0x0025,
349 	[BEND_IDX(-10)] = 0x0125,
350 	[BEND_IDX(-15)] = 0x0125,
351 	[BEND_IDX(-20)] = 0x0225,
352 	[BEND_IDX(-25)] = 0x0225,
353 	[BEND_IDX(-30)] = 0x0325,
354 	[BEND_IDX(-35)] = 0x0325,
355 	[BEND_IDX(-40)] = 0x0425,
356 	[BEND_IDX(-45)] = 0x0425,
357 	[BEND_IDX(-50)] = 0x0525,
363  * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
371 	if (drm_WARN_ON(&dev_priv->drm, steps % 5 != 0))  in lpt_bend_clkout_dp()
379 	if (steps % 10 != 0)  in lpt_bend_clkout_dp()
380 		tmp = 0xAAAAAAAB;  in lpt_bend_clkout_dp()
382 		tmp = 0x00000000;  in lpt_bend_clkout_dp()
386 	tmp &= 0xffff0000;  in lpt_bend_clkout_dp()
400 	if ((ctl & SPLL_PLL_ENABLE) == 0)  in spll_uses_pch_ssc()
404 	    (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)  in spll_uses_pch_ssc()
420 	if ((ctl & WRPLL_PLL_ENABLE) == 0)  in wrpll_uses_pch_ssc()
428 	    (fuse_strap & HSW_CPU_SSC_ENABLE) == 0)  in wrpll_uses_pch_ssc()
464 	dev_priv->display.dpll.pch_ssc_use = 0;  in lpt_init_pch_refclk()
485 		lpt_bend_clkout_dp(dev_priv, 0);  in lpt_init_pch_refclk()