Lines Matching +full:mac +full:- +full:divider
2 * Copyright © 2006-2007 Intel Corporation
65 int divider; member
108 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_lvds_get_hw_state()
113 wakeref = intel_display_power_get_if_enabled(i915, encoder->power_domain); in intel_lvds_get_hw_state()
117 ret = intel_lvds_port_enabled(i915, lvds_encoder->reg, pipe); in intel_lvds_get_hw_state()
119 intel_display_power_put(i915, encoder->power_domain, wakeref); in intel_lvds_get_hw_state()
127 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_lvds_get_config()
131 crtc_state->output_types |= BIT(INTEL_OUTPUT_LVDS); in intel_lvds_get_config()
133 tmp = intel_de_read(dev_priv, lvds_encoder->reg); in intel_lvds_get_config()
143 crtc_state->hw.adjusted_mode.flags |= flags; in intel_lvds_get_config()
146 crtc_state->gmch_pfit.lvds_border_bits = in intel_lvds_get_config()
153 crtc_state->gmch_pfit.control |= tmp & PFIT_PANEL_8TO6_DITHER_ENABLE; in intel_lvds_get_config()
156 crtc_state->hw.adjusted_mode.crtc_clock = crtc_state->port_clock; in intel_lvds_get_config()
164 pps->powerdown_on_reset = intel_de_read(dev_priv, in intel_lvds_pps_get_hw_state()
168 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); in intel_lvds_pps_get_hw_state()
169 pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
170 pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
173 pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
174 pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
177 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); in intel_lvds_pps_get_hw_state()
181 * too short power-cycle delay due to the asynchronous programming of in intel_lvds_pps_get_hw_state()
185 val--; in intel_lvds_pps_get_hw_state()
187 pps->t4 = val * 1000; in intel_lvds_pps_get_hw_state()
190 pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) { in intel_lvds_pps_get_hw_state()
191 drm_dbg_kms(&dev_priv->drm, in intel_lvds_pps_get_hw_state()
195 pps->t1_t2 = 40 * 10; in intel_lvds_pps_get_hw_state()
196 pps->t5 = 200 * 10; in intel_lvds_pps_get_hw_state()
198 pps->t3 = 35 * 10; in intel_lvds_pps_get_hw_state()
199 pps->tx = 200 * 10; in intel_lvds_pps_get_hw_state()
202 drm_dbg(&dev_priv->drm, "LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d " in intel_lvds_pps_get_hw_state()
203 "divider %d port %d powerdown_on_reset %d\n", in intel_lvds_pps_get_hw_state()
204 pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx, in intel_lvds_pps_get_hw_state()
205 pps->divider, pps->port, pps->powerdown_on_reset); in intel_lvds_pps_get_hw_state()
214 drm_WARN_ON(&dev_priv->drm, in intel_lvds_pps_init_hw()
216 if (pps->powerdown_on_reset) in intel_lvds_pps_init_hw()
221 REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | in intel_lvds_pps_init_hw()
222 REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) | in intel_lvds_pps_init_hw()
223 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5)); in intel_lvds_pps_init_hw()
226 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | in intel_lvds_pps_init_hw()
227 REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx)); in intel_lvds_pps_init_hw()
230 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | in intel_lvds_pps_init_hw()
231 REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(pps->t4, 1000) + 1)); in intel_lvds_pps_init_hw()
240 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_pre_enable_lvds()
241 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_pre_enable_lvds()
242 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_pre_enable_lvds()
243 enum pipe pipe = crtc->pipe; in intel_pre_enable_lvds()
248 assert_shared_dpll_disabled(i915, crtc_state->shared_dpll); in intel_pre_enable_lvds()
253 intel_lvds_pps_init_hw(i915, &lvds_encoder->init_pps); in intel_pre_enable_lvds()
255 temp = lvds_encoder->init_lvds_val; in intel_pre_enable_lvds()
268 temp |= crtc_state->gmch_pfit.lvds_border_bits; in intel_pre_enable_lvds()
271 * Set the B0-B3 data pairs corresponding to whether we're going to in intel_pre_enable_lvds()
272 * set the DPLLs for dual-channel mode or not. in intel_pre_enable_lvds()
274 if (lvds_encoder->is_dual_link) in intel_pre_enable_lvds()
280 * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) in intel_pre_enable_lvds()
286 temp |= lvds_encoder->a3_power; in intel_pre_enable_lvds()
290 * special lvds dither control bit on pch-split platforms, dithering is in intel_pre_enable_lvds()
298 if (crtc_state->dither && crtc_state->pipe_bpp == 18) in intel_pre_enable_lvds()
304 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) in intel_pre_enable_lvds()
306 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) in intel_pre_enable_lvds()
309 intel_de_write(i915, lvds_encoder->reg, temp); in intel_pre_enable_lvds()
321 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_enable_lvds()
323 intel_de_rmw(dev_priv, lvds_encoder->reg, 0, LVDS_PORT_EN); in intel_enable_lvds()
326 intel_de_posting_read(dev_priv, lvds_encoder->reg); in intel_enable_lvds()
329 drm_err(&dev_priv->drm, in intel_enable_lvds()
341 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_disable_lvds()
345 drm_err(&dev_priv->drm, in intel_disable_lvds()
348 intel_de_rmw(dev_priv, lvds_encoder->reg, LVDS_PORT_EN, 0); in intel_disable_lvds()
349 intel_de_posting_read(dev_priv, lvds_encoder->reg); in intel_disable_lvds()
381 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_lvds_shutdown()
384 drm_err(&dev_priv->drm, in intel_lvds_shutdown()
393 struct drm_i915_private *i915 = to_i915(connector->base.dev); in intel_lvds_mode_valid()
396 int max_pixclk = to_i915(connector->base.dev)->display.cdclk.max_dotclk_freq; in intel_lvds_mode_valid()
407 if (fixed_mode->clock > max_pixclk) in intel_lvds_mode_valid()
417 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_lvds_compute_config()
419 struct intel_connector *connector = lvds_encoder->attached_connector; in intel_lvds_compute_config()
420 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_lvds_compute_config()
421 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_lvds_compute_config()
426 if (DISPLAY_VER(i915) < 4 && crtc->pipe == 0) { in intel_lvds_compute_config()
427 drm_err(&i915->drm, "Can't support LVDS on pipe A\n"); in intel_lvds_compute_config()
428 return -EINVAL; in intel_lvds_compute_config()
432 crtc_state->has_pch_encoder = true; in intel_lvds_compute_config()
434 return -EINVAL; in intel_lvds_compute_config()
437 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) in intel_lvds_compute_config()
442 /* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */ in intel_lvds_compute_config()
443 if (lvds_bpp != crtc_state->pipe_bpp && !crtc_state->bw_constrained) { in intel_lvds_compute_config()
444 drm_dbg_kms(&i915->drm, in intel_lvds_compute_config()
446 crtc_state->pipe_bpp, lvds_bpp); in intel_lvds_compute_config()
447 crtc_state->pipe_bpp = lvds_bpp; in intel_lvds_compute_config()
450 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; in intel_lvds_compute_config()
451 crtc_state->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_lvds_compute_config()
463 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) in intel_lvds_compute_config()
464 return -EINVAL; in intel_lvds_compute_config()
485 const struct drm_edid *fixed_edid = connector->panel.fixed_edid; in intel_lvds_get_modes()
489 drm_edid_connector_update(&connector->base, fixed_edid); in intel_lvds_get_modes()
491 return drm_edid_connector_add_modes(&connector->base); in intel_lvds_get_modes()
521 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); in intel_no_lvds_dmi_callback()
529 .ident = "Apple Mac Mini (Core series)",
537 .ident = "Apple Mac Mini (Core 2 series)",
545 .ident = "MSI IM-945GSE-A",
572 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
580 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
585 .ident = "AOpen i915GMm-HFS",
588 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
593 .ident = "AOpen i45GMx-I",
596 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
601 .ident = "Aopen i945GTt-VFA",
632 .ident = "Asus AT5NM10T-I",
635 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
640 .ident = "Hewlett-Packard HP t5740",
642 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
648 .ident = "Hewlett-Packard t5745",
650 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
656 .ident = "Hewlett-Packard st5747",
658 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
666 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
667 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
672 .ident = "Gigabyte GA-D525TUD",
680 .ident = "Supermicro X7SPA-H",
683 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
740 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); in intel_dual_link_lvds_callback()
776 for_each_intel_encoder(&i915->drm, encoder) { in intel_get_lvds_encoder()
777 if (encoder->type == INTEL_OUTPUT_LVDS) in intel_get_lvds_encoder()
788 return encoder && to_lvds_encoder(encoder)->is_dual_link; in intel_is_dual_link_lvds()
793 struct drm_i915_private *i915 = to_i915(lvds_encoder->base.base.dev); in compute_is_dual_link_lvds()
794 struct intel_connector *connector = lvds_encoder->attached_connector; in compute_is_dual_link_lvds()
800 if (i915->display.params.lvds_channel_mode > 0) in compute_is_dual_link_lvds()
801 return i915->display.params.lvds_channel_mode == 2; in compute_is_dual_link_lvds()
804 if (fixed_mode->clock > 112999) in compute_is_dual_link_lvds()
816 val = intel_de_read(i915, lvds_encoder->reg); in compute_is_dual_link_lvds()
822 val = connector->panel.vbt.bios_lvds_val; in compute_is_dual_link_lvds()
833 * intel_lvds_init - setup LVDS connectors on this device
841 struct intel_display *display = &i915->display; in intel_lvds_init()
852 drm_WARN(&i915->drm, !i915->display.vbt.int_lvds_support, in intel_lvds_init()
857 if (!i915->display.vbt.int_lvds_support) { in intel_lvds_init()
858 drm_dbg_kms(&i915->drm, in intel_lvds_init()
878 drm_dbg_kms(&i915->drm, in intel_lvds_init()
882 drm_dbg_kms(&i915->drm, in intel_lvds_init()
896 lvds_encoder->attached_connector = connector; in intel_lvds_init()
897 encoder = &lvds_encoder->base; in intel_lvds_init()
899 drm_connector_init_with_ddc(&i915->drm, &connector->base, in intel_lvds_init()
904 drm_encoder_init(&i915->drm, &encoder->base, &intel_lvds_enc_funcs, in intel_lvds_init()
907 encoder->enable = intel_enable_lvds; in intel_lvds_init()
908 encoder->pre_enable = intel_pre_enable_lvds; in intel_lvds_init()
909 encoder->compute_config = intel_lvds_compute_config; in intel_lvds_init()
911 encoder->disable = pch_disable_lvds; in intel_lvds_init()
912 encoder->post_disable = pch_post_disable_lvds; in intel_lvds_init()
914 encoder->disable = gmch_disable_lvds; in intel_lvds_init()
916 encoder->get_hw_state = intel_lvds_get_hw_state; in intel_lvds_init()
917 encoder->get_config = intel_lvds_get_config; in intel_lvds_init()
918 encoder->update_pipe = intel_backlight_update; in intel_lvds_init()
919 encoder->shutdown = intel_lvds_shutdown; in intel_lvds_init()
920 connector->get_hw_state = intel_connector_get_hw_state; in intel_lvds_init()
924 encoder->type = INTEL_OUTPUT_LVDS; in intel_lvds_init()
925 encoder->power_domain = POWER_DOMAIN_PORT_OTHER; in intel_lvds_init()
926 encoder->port = PORT_NONE; in intel_lvds_init()
927 encoder->cloneable = 0; in intel_lvds_init()
929 encoder->pipe_mask = BIT(PIPE_B); in intel_lvds_init()
931 encoder->pipe_mask = ~0; in intel_lvds_init()
933 drm_connector_helper_add(&connector->base, &intel_lvds_connector_helper_funcs); in intel_lvds_init()
934 connector->base.display_info.subpixel_order = SubPixelHorizontalRGB; in intel_lvds_init()
936 lvds_encoder->reg = lvds_reg; in intel_lvds_init()
938 intel_lvds_add_properties(&connector->base); in intel_lvds_init()
940 intel_lvds_pps_get_hw_state(i915, &lvds_encoder->init_pps); in intel_lvds_init()
941 lvds_encoder->init_lvds_val = lvds; in intel_lvds_init()
955 mutex_lock(&i915->drm.mode_config.mutex); in intel_lvds_init()
957 drm_edid = drm_edid_read_switcheroo(&connector->base, connector->base.ddc); in intel_lvds_init()
959 drm_edid = drm_edid_read_ddc(&connector->base, connector->base.ddc); in intel_lvds_init()
961 if (drm_edid_connector_update(&connector->base, drm_edid) || in intel_lvds_init()
962 !drm_edid_connector_add_modes(&connector->base)) { in intel_lvds_init()
963 drm_edid_connector_update(&connector->base, NULL); in intel_lvds_init()
965 drm_edid = ERR_PTR(-EINVAL); in intel_lvds_init()
968 drm_edid = ERR_PTR(-ENOENT); in intel_lvds_init()
970 intel_bios_init_panel_late(display, &connector->panel, NULL, in intel_lvds_init()
988 mutex_unlock(&i915->drm.mode_config.mutex); in intel_lvds_init()
998 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); in intel_lvds_init()
999 drm_dbg_kms(&i915->drm, "detected %s-link lvds configuration\n", in intel_lvds_init()
1000 lvds_encoder->is_dual_link ? "dual" : "single"); in intel_lvds_init()
1002 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; in intel_lvds_init()
1007 drm_dbg_kms(&i915->drm, "No LVDS modes found, disabling.\n"); in intel_lvds_init()
1008 drm_connector_cleanup(&connector->base); in intel_lvds_init()
1009 drm_encoder_cleanup(&encoder->base); in intel_lvds_init()