Lines Matching +full:hdmi +full:- +full:connector
3 * Copyright © 2006-2009 Intel Corporation
30 #include <linux/hdmi.h>
71 drm_WARN(display->drm, in assert_hdmi_port_disabled()
72 intel_de_read(display, intel_hdmi->hdmi_reg) & enabled_bits, in assert_hdmi_port_disabled()
73 "HDMI port enabled, expecting disabled\n"); in assert_hdmi_port_disabled()
80 drm_WARN(display->drm, in assert_hdmi_transcoder_func_disabled()
83 "HDMI transcoder function enabled, expecting disabled\n"); in assert_hdmi_transcoder_func_disabled()
214 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), in g4x_write_infoframe()
265 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) in g4x_infoframes_enabled()
279 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ibx_write_infoframe()
280 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); in ibx_write_infoframe()
284 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), in ibx_write_infoframe()
295 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), in ibx_write_infoframe()
301 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0); in ibx_write_infoframe()
317 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ibx_read_infoframe()
321 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe), in ibx_read_infoframe()
325 *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe)); in ibx_read_infoframe()
332 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; in ibx_infoframes_enabled()
339 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) in ibx_infoframes_enabled()
354 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in cpt_write_infoframe()
355 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); in cpt_write_infoframe()
359 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), in cpt_write_infoframe()
373 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), in cpt_write_infoframe()
379 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0); in cpt_write_infoframe()
395 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in cpt_read_infoframe()
399 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe), in cpt_read_infoframe()
403 *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe)); in cpt_read_infoframe()
410 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; in cpt_infoframes_enabled()
428 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_write_infoframe()
429 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); in vlv_write_infoframe()
433 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), in vlv_write_infoframe()
445 VLV_TVIDEO_DIP_DATA(crtc->pipe), *data); in vlv_write_infoframe()
451 VLV_TVIDEO_DIP_DATA(crtc->pipe), 0); in vlv_write_infoframe()
467 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_read_infoframe()
471 intel_de_rmw(display, VLV_TVIDEO_DIP_CTL(crtc->pipe), in vlv_read_infoframe()
476 VLV_TVIDEO_DIP_DATA(crtc->pipe)); in vlv_read_infoframe()
483 enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe; in vlv_infoframes_enabled()
489 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port)) in vlv_infoframes_enabled()
504 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in hsw_write_infoframe()
512 drm_WARN_ON(display->drm, len > data_size); in hsw_write_infoframe()
530 if (!(IS_DISPLAY_VER(display, 13, 14) && crtc_state->has_psr && in hsw_write_infoframe()
531 !crtc_state->has_panel_replay && type == DP_SDP_VSC)) in hsw_write_infoframe()
546 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in hsw_read_infoframe()
560 HSW_TVIDEO_DIP_CTL(display, pipe_config->cpu_transcoder)); in hsw_infoframes_enabled()
607 val = dig_port->infoframes_enabled(encoder, crtc_state); in intel_hdmi_infoframes_enabled()
627 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
638 * The hdmi pack() functions don't know about that hardware specific hole so we
651 if ((crtc_state->infoframes.enable & in intel_write_infoframe()
655 if (drm_WARN_ON(encoder->base.dev, frame->any.type != type)) in intel_write_infoframe()
659 len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1); in intel_write_infoframe()
660 if (drm_WARN_ON(encoder->base.dev, len < 0)) in intel_write_infoframe()
668 dig_port->write_infoframe(encoder, crtc_state, type, buffer, len); in intel_write_infoframe()
680 if ((crtc_state->infoframes.enable & in intel_read_infoframe()
684 dig_port->read_infoframe(encoder, crtc_state, in intel_read_infoframe()
691 ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1); in intel_read_infoframe()
693 drm_dbg_kms(encoder->base.dev, in intel_read_infoframe()
698 if (frame->any.type != type) in intel_read_infoframe()
699 drm_dbg_kms(encoder->base.dev, in intel_read_infoframe()
701 frame->any.type, type); in intel_read_infoframe()
709 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi; in intel_hdmi_compute_avi_infoframe()
711 &crtc_state->hw.adjusted_mode; in intel_hdmi_compute_avi_infoframe()
712 struct drm_connector *connector = conn_state->connector; in intel_hdmi_compute_avi_infoframe() local
715 if (!crtc_state->has_infoframe) in intel_hdmi_compute_avi_infoframe()
718 crtc_state->infoframes.enable |= in intel_hdmi_compute_avi_infoframe()
721 ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector, in intel_hdmi_compute_avi_infoframe()
726 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) in intel_hdmi_compute_avi_infoframe()
727 frame->colorspace = HDMI_COLORSPACE_YUV420; in intel_hdmi_compute_avi_infoframe()
728 else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) in intel_hdmi_compute_avi_infoframe()
729 frame->colorspace = HDMI_COLORSPACE_YUV444; in intel_hdmi_compute_avi_infoframe()
731 frame->colorspace = HDMI_COLORSPACE_RGB; in intel_hdmi_compute_avi_infoframe()
736 drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range && in intel_hdmi_compute_avi_infoframe()
737 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); in intel_hdmi_compute_avi_infoframe()
739 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) { in intel_hdmi_compute_avi_infoframe()
740 drm_hdmi_avi_infoframe_quant_range(frame, connector, in intel_hdmi_compute_avi_infoframe()
742 crtc_state->limited_color_range ? in intel_hdmi_compute_avi_infoframe()
746 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; in intel_hdmi_compute_avi_infoframe()
747 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED; in intel_hdmi_compute_avi_infoframe()
755 if (drm_WARN_ON(encoder->base.dev, ret)) in intel_hdmi_compute_avi_infoframe()
766 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_hdmi_compute_spd_infoframe()
767 struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd; in intel_hdmi_compute_spd_infoframe()
770 if (!crtc_state->has_infoframe) in intel_hdmi_compute_spd_infoframe()
773 crtc_state->infoframes.enable |= in intel_hdmi_compute_spd_infoframe()
781 if (drm_WARN_ON(encoder->base.dev, ret)) in intel_hdmi_compute_spd_infoframe()
784 frame->sdi = HDMI_SPD_SDI_PC; in intel_hdmi_compute_spd_infoframe()
787 if (drm_WARN_ON(encoder->base.dev, ret)) in intel_hdmi_compute_spd_infoframe()
799 &crtc_state->infoframes.hdmi.vendor.hdmi; in intel_hdmi_compute_hdmi_infoframe()
801 &conn_state->connector->display_info; in intel_hdmi_compute_hdmi_infoframe()
804 if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe) in intel_hdmi_compute_hdmi_infoframe()
807 crtc_state->infoframes.enable |= in intel_hdmi_compute_hdmi_infoframe()
811 conn_state->connector, in intel_hdmi_compute_hdmi_infoframe()
812 &crtc_state->hw.adjusted_mode); in intel_hdmi_compute_hdmi_infoframe()
813 if (drm_WARN_ON(encoder->base.dev, ret)) in intel_hdmi_compute_hdmi_infoframe()
817 if (drm_WARN_ON(encoder->base.dev, ret)) in intel_hdmi_compute_hdmi_infoframe()
829 struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm; in intel_hdmi_compute_drm_infoframe()
835 if (!crtc_state->has_infoframe) in intel_hdmi_compute_drm_infoframe()
838 if (!conn_state->hdr_output_metadata) in intel_hdmi_compute_drm_infoframe()
841 crtc_state->infoframes.enable |= in intel_hdmi_compute_drm_infoframe()
846 drm_dbg_kms(display->drm, in intel_hdmi_compute_drm_infoframe()
852 if (drm_WARN_ON(display->drm, ret)) in intel_hdmi_compute_drm_infoframe()
865 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; in g4x_set_infoframes()
868 u32 port = VIDEO_DIP_PORT(encoder->port); in g4x_set_infoframes()
887 drm_dbg_kms(display->drm, in g4x_set_infoframes()
901 drm_dbg_kms(display->drm, in g4x_set_infoframes()
919 &crtc_state->infoframes.avi); in g4x_set_infoframes()
922 &crtc_state->infoframes.spd); in g4x_set_infoframes()
925 &crtc_state->infoframes.hdmi); in g4x_set_infoframes()
931 * From HDMI specification 1.4a:
932 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
933 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
934 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
935 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
961 return mode->crtc_hdisplay % pixels_per_group == 0 && in gcp_default_phase_possible()
962 mode->crtc_htotal % pixels_per_group == 0 && in gcp_default_phase_possible()
963 mode->crtc_hblank_start % pixels_per_group == 0 && in gcp_default_phase_possible()
964 mode->crtc_hblank_end % pixels_per_group == 0 && in gcp_default_phase_possible()
965 mode->crtc_hsync_start % pixels_per_group == 0 && in gcp_default_phase_possible()
966 mode->crtc_hsync_end % pixels_per_group == 0 && in gcp_default_phase_possible()
967 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 || in gcp_default_phase_possible()
968 mode->crtc_htotal/2 % pixels_per_group == 0); in gcp_default_phase_possible()
976 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_set_gcp_infoframe()
977 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_hdmi_set_gcp_infoframe()
980 if ((crtc_state->infoframes.enable & in intel_hdmi_set_gcp_infoframe()
985 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder); in intel_hdmi_set_gcp_infoframe()
987 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); in intel_hdmi_set_gcp_infoframe()
989 reg = TVIDEO_DIP_GCP(crtc->pipe); in intel_hdmi_set_gcp_infoframe()
993 intel_de_write(display, reg, crtc_state->infoframes.gcp); in intel_hdmi_set_gcp_infoframe()
1002 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_read_gcp_infoframe()
1003 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_hdmi_read_gcp_infoframe()
1006 if ((crtc_state->infoframes.enable & in intel_hdmi_read_gcp_infoframe()
1011 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder); in intel_hdmi_read_gcp_infoframe()
1013 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); in intel_hdmi_read_gcp_infoframe()
1015 reg = TVIDEO_DIP_GCP(crtc->pipe); in intel_hdmi_read_gcp_infoframe()
1019 crtc_state->infoframes.gcp = intel_de_read(display, reg); in intel_hdmi_read_gcp_infoframe()
1026 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_compute_gcp_infoframe()
1028 if (IS_G4X(dev_priv) || !crtc_state->has_infoframe) in intel_hdmi_compute_gcp_infoframe()
1031 crtc_state->infoframes.enable |= in intel_hdmi_compute_gcp_infoframe()
1035 if (crtc_state->pipe_bpp > 24) in intel_hdmi_compute_gcp_infoframe()
1036 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION; in intel_hdmi_compute_gcp_infoframe()
1039 if (gcp_default_phase_possible(crtc_state->pipe_bpp, in intel_hdmi_compute_gcp_infoframe()
1040 &crtc_state->hw.adjusted_mode)) in intel_hdmi_compute_gcp_infoframe()
1041 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE; in intel_hdmi_compute_gcp_infoframe()
1050 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in ibx_set_infoframes()
1052 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; in ibx_set_infoframes()
1053 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); in ibx_set_infoframes()
1055 u32 port = VIDEO_DIP_PORT(encoder->port); in ibx_set_infoframes()
1074 drm_WARN(display->drm, val & VIDEO_DIP_ENABLE, in ibx_set_infoframes()
1094 &crtc_state->infoframes.avi); in ibx_set_infoframes()
1097 &crtc_state->infoframes.spd); in ibx_set_infoframes()
1100 &crtc_state->infoframes.hdmi); in ibx_set_infoframes()
1109 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in cpt_set_infoframes()
1111 i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe); in cpt_set_infoframes()
1143 &crtc_state->infoframes.avi); in cpt_set_infoframes()
1146 &crtc_state->infoframes.spd); in cpt_set_infoframes()
1149 &crtc_state->infoframes.hdmi); in cpt_set_infoframes()
1158 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_set_infoframes()
1160 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe); in vlv_set_infoframes()
1162 u32 port = VIDEO_DIP_PORT(encoder->port); in vlv_set_infoframes()
1181 drm_WARN(display->drm, val & VIDEO_DIP_ENABLE, in vlv_set_infoframes()
1201 &crtc_state->infoframes.avi); in vlv_set_infoframes()
1204 &crtc_state->infoframes.spd); in vlv_set_infoframes()
1207 &crtc_state->infoframes.hdmi); in vlv_set_infoframes()
1217 crtc_state->cpu_transcoder); in hsw_set_infoframes()
1221 crtc_state->cpu_transcoder); in hsw_set_infoframes()
1242 &crtc_state->infoframes.avi); in hsw_set_infoframes()
1245 &crtc_state->infoframes.spd); in hsw_set_infoframes()
1248 &crtc_state->infoframes.hdmi); in hsw_set_infoframes()
1251 &crtc_state->infoframes.drm); in hsw_set_infoframes()
1254 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable) in intel_dp_dual_mode_set_tmds_output() argument
1256 struct intel_display *display = to_intel_display(hdmi); in intel_dp_dual_mode_set_tmds_output()
1257 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; in intel_dp_dual_mode_set_tmds_output()
1259 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI) in intel_dp_dual_mode_set_tmds_output()
1262 drm_dbg_kms(display->drm, "%s DP dual mode adaptor TMDS output\n", in intel_dp_dual_mode_set_tmds_output()
1265 drm_dp_dual_mode_set_tmds_output(display->drm, in intel_dp_dual_mode_set_tmds_output()
1266 hdmi->dp_dual_mode.type, ddc, enable); in intel_dp_dual_mode_set_tmds_output()
1272 struct intel_hdmi *hdmi = &dig_port->hdmi; in intel_hdmi_hdcp_read() local
1273 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; in intel_hdmi_hdcp_read()
1293 return ret >= 0 ? -EIO : ret; in intel_hdmi_hdcp_read()
1299 struct intel_hdmi *hdmi = &dig_port->hdmi; in intel_hdmi_hdcp_write() local
1300 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; in intel_hdmi_hdcp_write()
1307 return -ENOMEM; in intel_hdmi_hdcp_write()
1321 ret = -EIO; in intel_hdmi_hdcp_write()
1332 struct intel_hdmi *hdmi = &dig_port->hdmi; in intel_hdmi_hdcp_write_an_aksv() local
1333 struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc; in intel_hdmi_hdcp_write_an_aksv()
1339 drm_dbg_kms(display->drm, "Write An over DDC failed (%d)\n", in intel_hdmi_hdcp_write_an_aksv()
1346 drm_dbg_kms(display->drm, "Failed to output aksv (%d)\n", ret); in intel_hdmi_hdcp_write_an_aksv()
1361 drm_dbg_kms(display->drm, "Read Bksv over DDC failed (%d)\n", in intel_hdmi_hdcp_read_bksv()
1376 drm_dbg_kms(display->drm, in intel_hdmi_hdcp_read_bstatus()
1392 drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n", in intel_hdmi_hdcp_repeater_present()
1410 drm_dbg_kms(display->drm, "Read Ri' over DDC failed (%d)\n", in intel_hdmi_hdcp_read_ri_prime()
1425 drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n", in intel_hdmi_hdcp_read_ksv_ready()
1442 drm_dbg_kms(display->drm, in intel_hdmi_hdcp_read_ksv_fifo()
1457 return -EINVAL; in intel_hdmi_hdcp_read_v_prime_part()
1462 drm_dbg_kms(display->drm, in intel_hdmi_hdcp_read_v_prime_part()
1468 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector, in kbl_repositioning_enc_en_signal() argument
1471 struct intel_display *display = to_intel_display(connector); in kbl_repositioning_enc_en_signal()
1472 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); in kbl_repositioning_enc_en_signal()
1473 struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc); in kbl_repositioning_enc_en_signal()
1479 PIPEDSL(display, crtc->pipe)); in kbl_repositioning_enc_en_signal()
1485 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, in kbl_repositioning_enc_en_signal()
1488 drm_err(display->drm, in kbl_repositioning_enc_en_signal()
1493 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder, in kbl_repositioning_enc_en_signal()
1496 drm_err(display->drm, in kbl_repositioning_enc_en_signal()
1510 struct intel_hdmi *hdmi = &dig_port->hdmi; in intel_hdmi_hdcp_toggle_signalling() local
1511 struct intel_connector *connector = hdmi->attached_connector; in intel_hdmi_hdcp_toggle_signalling() local
1512 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); in intel_hdmi_hdcp_toggle_signalling()
1518 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, in intel_hdmi_hdcp_toggle_signalling()
1522 drm_err(display->drm, "%s HDCP signalling failed (%d)\n", in intel_hdmi_hdcp_toggle_signalling()
1532 return kbl_repositioning_enc_en_signal(connector, in intel_hdmi_hdcp_toggle_signalling()
1540 struct intel_connector *connector) in intel_hdmi_hdcp_check_link_once() argument
1543 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_hdmi_hdcp_check_link_once()
1544 enum port port = dig_port->base.port; in intel_hdmi_hdcp_check_link_once()
1545 enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder; in intel_hdmi_hdcp_check_link_once()
1562 drm_dbg_kms(display->drm, "Ri' mismatch detected (%x)\n", in intel_hdmi_hdcp_check_link_once()
1572 struct intel_connector *connector) in intel_hdmi_hdcp_check_link() argument
1578 if (intel_hdmi_hdcp_check_link_once(dig_port, connector)) in intel_hdmi_hdcp_check_link()
1581 drm_err(display->drm, "Link check failed\n"); in intel_hdmi_hdcp_check_link()
1624 return -EINVAL; in get_hdcp2_msg_timeout()
1638 drm_dbg_kms(display->drm, "rx_status read failed. Err %d\n", in hdcp2_detect_msg_availability()
1674 drm_dbg_kms(display->drm, in intel_hdmi_hdcp2_wait_for_msg()
1682 int intel_hdmi_hdcp2_write_msg(struct intel_connector *connector, in intel_hdmi_hdcp2_write_msg() argument
1685 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); in intel_hdmi_hdcp2_write_msg()
1693 int intel_hdmi_hdcp2_read_msg(struct intel_connector *connector, in intel_hdmi_hdcp2_read_msg() argument
1696 struct intel_display *display = to_intel_display(connector); in intel_hdmi_hdcp2_read_msg()
1697 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); in intel_hdmi_hdcp2_read_msg()
1698 struct intel_hdmi *hdmi = &dig_port->hdmi; in intel_hdmi_hdcp2_read_msg() local
1699 struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp; in intel_hdmi_hdcp2_read_msg()
1704 hdcp->is_paired); in intel_hdmi_hdcp2_read_msg()
1713 drm_dbg_kms(display->drm, in intel_hdmi_hdcp2_read_msg()
1716 return -EINVAL; in intel_hdmi_hdcp2_read_msg()
1722 drm_dbg_kms(display->drm, "Failed to read msg_id: %d(%zd)\n", in intel_hdmi_hdcp2_read_msg()
1730 struct intel_connector *connector) in intel_hdmi_hdcp2_check_link() argument
1740 * Re-auth request and Link Integrity Failures are represented by in intel_hdmi_hdcp2_check_link()
1752 int intel_hdmi_hdcp2_get_capability(struct intel_connector *connector, in intel_hdmi_hdcp2_get_capability() argument
1755 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); in intel_hdmi_hdcp2_get_capability()
1789 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_source_max_tmds_clock()
1803 vbt_max_tmds_clock = intel_bios_hdmi_max_tmds_clock(encoder->devdata); in intel_hdmi_source_max_tmds_clock()
1810 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi, in intel_has_hdmi_sink() argument
1813 struct intel_connector *connector = hdmi->attached_connector; in intel_has_hdmi_sink() local
1815 return connector->base.display_info.is_hdmi && in intel_has_hdmi_sink()
1816 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI; in intel_has_hdmi_sink()
1821 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420; in intel_hdmi_is_ycbcr420()
1824 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, in hdmi_port_clock_limit() argument
1828 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; in hdmi_port_clock_limit()
1832 struct intel_connector *connector = hdmi->attached_connector; in hdmi_port_clock_limit() local
1833 const struct drm_display_info *info = &connector->base.display_info; in hdmi_port_clock_limit()
1835 if (hdmi->dp_dual_mode.max_tmds_clock) in hdmi_port_clock_limit()
1837 hdmi->dp_dual_mode.max_tmds_clock); in hdmi_port_clock_limit()
1839 if (info->max_tmds_clock) in hdmi_port_clock_limit()
1841 info->max_tmds_clock); in hdmi_port_clock_limit()
1850 hdmi_port_clock_valid(struct intel_hdmi *hdmi, in hdmi_port_clock_valid() argument
1854 struct intel_display *display = to_intel_display(hdmi); in hdmi_port_clock_valid()
1855 struct drm_i915_private *dev_priv = to_i915(display->drm); in hdmi_port_clock_valid()
1856 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; in hdmi_port_clock_valid()
1860 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, in hdmi_port_clock_valid()
1864 /* GLK DPLL can't generate 446-480 MHz */ in hdmi_port_clock_valid()
1868 /* BXT/GLK DPLL can't generate 223-240 MHz */ in hdmi_port_clock_valid()
1873 /* CHV DPLL can't generate 216-240 MHz */ in hdmi_port_clock_valid()
1877 /* ICL+ combo PHY PLL can't generate 500-533.2 MHz */ in hdmi_port_clock_valid()
1881 /* ICL+ TC PHY PLL can't generate 500-532.8 MHz */ in hdmi_port_clock_valid()
1886 * SNPS PHYs' MPLLB table-based programming can only handle a fixed in hdmi_port_clock_valid()
1890 * the MPLLB for HDMI in the future. in hdmi_port_clock_valid()
1893 return intel_cx0_phy_check_hdmi_link_rate(hdmi, clock); in hdmi_port_clock_valid()
1930 static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector, in intel_hdmi_sink_bpc_possible() argument
1934 const struct drm_display_info *info = &connector->display_info; in intel_hdmi_sink_bpc_possible()
1935 const struct drm_hdmi_info *hdmi = &info->hdmi; in intel_hdmi_sink_bpc_possible() local
1943 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36; in intel_hdmi_sink_bpc_possible()
1945 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36; in intel_hdmi_sink_bpc_possible()
1951 return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30; in intel_hdmi_sink_bpc_possible()
1953 return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30; in intel_hdmi_sink_bpc_possible()
1963 intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock, in intel_hdmi_mode_clock_valid() argument
1967 struct intel_display *display = to_intel_display(connector->dev); in intel_hdmi_mode_clock_valid()
1968 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); in intel_hdmi_mode_clock_valid() local
1977 for (bpc = 12; bpc >= 8; bpc -= 2) { in intel_hdmi_mode_clock_valid()
1983 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, sink_format)) in intel_hdmi_mode_clock_valid()
1986 status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink); in intel_hdmi_mode_clock_valid()
1992 drm_WARN_ON(display->drm, status == MODE_OK); in intel_hdmi_mode_clock_valid()
1998 intel_hdmi_mode_valid(struct drm_connector *connector, in intel_hdmi_mode_valid() argument
2001 struct intel_display *display = to_intel_display(connector->dev); in intel_hdmi_mode_valid()
2002 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); in intel_hdmi_mode_valid() local
2003 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_hdmi_mode_valid()
2005 int clock = mode->clock; in intel_hdmi_mode_valid()
2006 int max_dotclk = to_i915(connector->dev)->display.cdclk.max_dotclk_freq; in intel_hdmi_mode_valid()
2007 bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state); in intel_hdmi_mode_valid()
2015 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING) in intel_hdmi_mode_valid()
2021 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { in intel_hdmi_mode_valid()
2036 ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode); in intel_hdmi_mode_valid()
2043 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format); in intel_hdmi_mode_valid()
2046 !connector->ycbcr_420_allowed || in intel_hdmi_mode_valid()
2047 !drm_mode_is_420_also(&connector->display_info, mode)) in intel_hdmi_mode_valid()
2051 status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format); in intel_hdmi_mode_valid()
2062 struct drm_atomic_state *state = crtc_state->uapi.state; in intel_hdmi_bpc_possible()
2064 struct drm_connector *connector; in intel_hdmi_bpc_possible() local
2067 for_each_new_connector_in_state(state, connector, connector_state, i) { in intel_hdmi_bpc_possible()
2068 if (connector_state->crtc != crtc_state->uapi.crtc) in intel_hdmi_bpc_possible()
2071 if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, in intel_hdmi_bpc_possible()
2072 crtc_state->sink_format)) in intel_hdmi_bpc_possible()
2083 &crtc_state->hw.adjusted_mode; in hdmi_bpc_possible()
2091 (adjusted_mode->crtc_hblank_end - in hdmi_bpc_possible()
2092 adjusted_mode->crtc_hblank_start) % 8 == 2) in hdmi_bpc_possible()
2095 return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink); in hdmi_bpc_possible()
2107 * bandwidth constraints. HDMI minimum is 8bpc however. in intel_hdmi_compute_bpc()
2109 bpc = max(crtc_state->pipe_bpp / 3, 8); in intel_hdmi_compute_bpc()
2119 for (; bpc >= 8; bpc -= 2) { in intel_hdmi_compute_bpc()
2121 crtc_state->sink_format); in intel_hdmi_compute_bpc()
2126 crtc_state->has_hdmi_sink) == MODE_OK) in intel_hdmi_compute_bpc()
2130 return -EINVAL; in intel_hdmi_compute_bpc()
2139 &crtc_state->hw.adjusted_mode; in intel_hdmi_compute_clock()
2140 int bpc, clock = adjusted_mode->crtc_clock; in intel_hdmi_compute_clock()
2142 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) in intel_hdmi_compute_clock()
2150 crtc_state->port_clock = in intel_hdmi_compute_clock()
2151 intel_hdmi_tmds_clock(clock, bpc, crtc_state->sink_format); in intel_hdmi_compute_clock()
2156 * back up to the HDMI minimum 8bpc in that case. in intel_hdmi_compute_clock()
2158 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3); in intel_hdmi_compute_clock()
2160 drm_dbg_kms(display->drm, in intel_hdmi_compute_clock()
2161 "picking %d bpc for HDMI output (pipe bpp: %d)\n", in intel_hdmi_compute_clock()
2162 bpc, crtc_state->pipe_bpp); in intel_hdmi_compute_clock()
2173 &crtc_state->hw.adjusted_mode; in intel_hdmi_limited_color_range()
2177 * crtc_state->limited_color_range only applies to RGB, in intel_hdmi_limited_color_range()
2182 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) in intel_hdmi_limited_color_range()
2185 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { in intel_hdmi_limited_color_range()
2186 /* See CEA-861-E - 5.1 Default Encoding Parameters */ in intel_hdmi_limited_color_range()
2187 return crtc_state->has_hdmi_sink && in intel_hdmi_limited_color_range()
2191 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED; in intel_hdmi_limited_color_range()
2199 struct drm_connector *connector = conn_state->connector; in intel_hdmi_has_audio() local
2203 if (!crtc_state->has_hdmi_sink) in intel_hdmi_has_audio()
2206 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) in intel_hdmi_has_audio()
2207 return connector->display_info.has_audio; in intel_hdmi_has_audio()
2209 return intel_conn_state->force_audio == HDMI_AUDIO_ON; in intel_hdmi_has_audio()
2214 struct intel_connector *connector, in intel_hdmi_sink_format() argument
2217 if (!crtc_state->has_hdmi_sink) in intel_hdmi_sink_format()
2220 if (connector->base.ycbcr_420_allowed && ycbcr_420_output) in intel_hdmi_sink_format()
2229 return crtc_state->sink_format; in intel_hdmi_output_format()
2238 struct intel_connector *connector = to_intel_connector(conn_state->connector); in intel_hdmi_compute_output_format() local
2239 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_hdmi_compute_output_format()
2240 const struct drm_display_info *info = &connector->base.display_info; in intel_hdmi_compute_output_format()
2244 crtc_state->sink_format = in intel_hdmi_compute_output_format()
2245 intel_hdmi_sink_format(crtc_state, connector, ycbcr_420_only); in intel_hdmi_compute_output_format()
2247 if (ycbcr_420_only && crtc_state->sink_format != INTEL_OUTPUT_FORMAT_YCBCR420) { in intel_hdmi_compute_output_format()
2248 drm_dbg_kms(display->drm, in intel_hdmi_compute_output_format()
2250 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB; in intel_hdmi_compute_output_format()
2253 crtc_state->output_format = intel_hdmi_output_format(crtc_state); in intel_hdmi_compute_output_format()
2256 if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || in intel_hdmi_compute_output_format()
2257 !crtc_state->has_hdmi_sink || in intel_hdmi_compute_output_format()
2258 !connector->base.ycbcr_420_allowed || in intel_hdmi_compute_output_format()
2262 crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; in intel_hdmi_compute_output_format()
2263 crtc_state->output_format = intel_hdmi_output_format(crtc_state); in intel_hdmi_compute_output_format()
2272 return crtc_state->uapi.encoder_mask && in intel_hdmi_is_cloned()
2273 !is_power_of_2(crtc_state->uapi.encoder_mask); in intel_hdmi_is_cloned()
2279 * Gen 10+ support HDMI 2.0 : the max tmds clock is 594MHz, and in source_supports_scrambling()
2282 * HDMI 2.0, have an HDMI1.4 retimer chip, and the max tmds clock is in source_supports_scrambling()
2287 * HDMI 1.4 retimer chip doesn't. in source_supports_scrambling()
2299 struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder); in intel_hdmi_compute_has_hdmi_sink() local
2301 return intel_has_hdmi_sink(hdmi, conn_state) && in intel_hdmi_compute_has_hdmi_sink()
2310 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_hdmi_compute_config()
2311 struct drm_connector *connector = conn_state->connector; in intel_hdmi_compute_config() local
2312 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc; in intel_hdmi_compute_config()
2315 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) in intel_hdmi_compute_config()
2316 return -EINVAL; in intel_hdmi_compute_config()
2318 if (!connector->interlace_allowed && in intel_hdmi_compute_config()
2319 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) in intel_hdmi_compute_config()
2320 return -EINVAL; in intel_hdmi_compute_config()
2322 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_hdmi_compute_config()
2324 if (pipe_config->has_hdmi_sink) in intel_hdmi_compute_config()
2325 pipe_config->has_infoframe = true; in intel_hdmi_compute_config()
2327 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) in intel_hdmi_compute_config()
2328 pipe_config->pixel_multiplier = 2; in intel_hdmi_compute_config()
2330 pipe_config->has_audio = in intel_hdmi_compute_config()
2342 drm_dbg_kms(display->drm, in intel_hdmi_compute_config()
2343 "unsupported HDMI clock (%d kHz), rejecting mode\n", in intel_hdmi_compute_config()
2344 pipe_config->hw.adjusted_mode.crtc_clock); in intel_hdmi_compute_config()
2354 pipe_config->limited_color_range = in intel_hdmi_compute_config()
2357 if (conn_state->picture_aspect_ratio) in intel_hdmi_compute_config()
2358 adjusted_mode->picture_aspect_ratio = in intel_hdmi_compute_config()
2359 conn_state->picture_aspect_ratio; in intel_hdmi_compute_config()
2361 pipe_config->lane_count = 4; in intel_hdmi_compute_config()
2363 if (scdc->scrambling.supported && source_supports_scrambling(encoder)) { in intel_hdmi_compute_config()
2364 if (scdc->scrambling.low_rates) in intel_hdmi_compute_config()
2365 pipe_config->hdmi_scrambling = true; in intel_hdmi_compute_config()
2367 if (pipe_config->port_clock > 340000) { in intel_hdmi_compute_config()
2368 pipe_config->hdmi_scrambling = true; in intel_hdmi_compute_config()
2369 pipe_config->hdmi_high_tmds_clock_ratio = true; in intel_hdmi_compute_config()
2377 drm_dbg_kms(display->drm, "bad AVI infoframe\n"); in intel_hdmi_compute_config()
2378 return -EINVAL; in intel_hdmi_compute_config()
2382 drm_dbg_kms(display->drm, "bad SPD infoframe\n"); in intel_hdmi_compute_config()
2383 return -EINVAL; in intel_hdmi_compute_config()
2387 drm_dbg_kms(display->drm, "bad HDMI infoframe\n"); in intel_hdmi_compute_config()
2388 return -EINVAL; in intel_hdmi_compute_config()
2392 drm_dbg_kms(display->drm, "bad DRM infoframe\n"); in intel_hdmi_compute_config()
2393 return -EINVAL; in intel_hdmi_compute_config()
2411 intel_hdmi_unset_edid(struct drm_connector *connector) in intel_hdmi_unset_edid() argument
2413 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); in intel_hdmi_unset_edid()
2415 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE; in intel_hdmi_unset_edid()
2416 intel_hdmi->dp_dual_mode.max_tmds_clock = 0; in intel_hdmi_unset_edid()
2418 drm_edid_free(to_intel_connector(connector)->detect_edid); in intel_hdmi_unset_edid()
2419 to_intel_connector(connector)->detect_edid = NULL; in intel_hdmi_unset_edid()
2423 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector) in intel_hdmi_dp_dual_mode_detect() argument
2425 struct intel_display *display = to_intel_display(connector->dev); in intel_hdmi_dp_dual_mode_detect()
2426 struct drm_i915_private *dev_priv = to_i915(connector->dev); in intel_hdmi_dp_dual_mode_detect()
2427 struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector)); in intel_hdmi_dp_dual_mode_detect() local
2428 struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; in intel_hdmi_dp_dual_mode_detect()
2429 struct i2c_adapter *ddc = connector->ddc; in intel_hdmi_dp_dual_mode_detect()
2432 type = drm_dp_dual_mode_detect(display->drm, ddc); in intel_hdmi_dp_dual_mode_detect()
2444 if (!connector->force && in intel_hdmi_dp_dual_mode_detect()
2445 intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) { in intel_hdmi_dp_dual_mode_detect()
2446 drm_dbg_kms(display->drm, in intel_hdmi_dp_dual_mode_detect()
2457 hdmi->dp_dual_mode.type = type; in intel_hdmi_dp_dual_mode_detect()
2458 hdmi->dp_dual_mode.max_tmds_clock = in intel_hdmi_dp_dual_mode_detect()
2459 drm_dp_dual_mode_max_tmds_clock(display->drm, type, ddc); in intel_hdmi_dp_dual_mode_detect()
2461 drm_dbg_kms(display->drm, in intel_hdmi_dp_dual_mode_detect()
2464 hdmi->dp_dual_mode.max_tmds_clock); in intel_hdmi_dp_dual_mode_detect()
2468 !intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) { in intel_hdmi_dp_dual_mode_detect()
2469 drm_dbg_kms(display->drm, in intel_hdmi_dp_dual_mode_detect()
2470 "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n"); in intel_hdmi_dp_dual_mode_detect()
2471 hdmi->dp_dual_mode.max_tmds_clock = 0; in intel_hdmi_dp_dual_mode_detect()
2476 intel_hdmi_set_edid(struct drm_connector *connector) in intel_hdmi_set_edid() argument
2478 struct intel_display *display = to_intel_display(connector->dev); in intel_hdmi_set_edid()
2479 struct drm_i915_private *dev_priv = to_i915(connector->dev); in intel_hdmi_set_edid()
2480 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); in intel_hdmi_set_edid()
2481 struct i2c_adapter *ddc = connector->ddc; in intel_hdmi_set_edid()
2488 drm_edid = drm_edid_read_ddc(connector, ddc); in intel_hdmi_set_edid()
2491 drm_dbg_kms(display->drm, in intel_hdmi_set_edid()
2492 "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n"); in intel_hdmi_set_edid()
2494 drm_edid = drm_edid_read_ddc(connector, ddc); in intel_hdmi_set_edid()
2499 drm_edid_connector_update(connector, drm_edid); in intel_hdmi_set_edid()
2501 to_intel_connector(connector)->detect_edid = drm_edid; in intel_hdmi_set_edid()
2504 intel_hdmi_dp_dual_mode_detect(connector); in intel_hdmi_set_edid()
2511 cec_notifier_set_phys_addr(intel_hdmi->cec_notifier, in intel_hdmi_set_edid()
2512 connector->display_info.source_physical_address); in intel_hdmi_set_edid()
2518 intel_hdmi_detect(struct drm_connector *connector, bool force) in intel_hdmi_detect() argument
2520 struct intel_display *display = to_intel_display(connector->dev); in intel_hdmi_detect()
2522 struct drm_i915_private *dev_priv = to_i915(connector->dev); in intel_hdmi_detect()
2523 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector)); in intel_hdmi_detect()
2524 struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base; in intel_hdmi_detect()
2527 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", in intel_hdmi_detect()
2528 connector->base.id, connector->name); in intel_hdmi_detect()
2534 return connector->status; in intel_hdmi_detect()
2542 intel_hdmi_unset_edid(connector); in intel_hdmi_detect()
2544 if (intel_hdmi_set_edid(connector)) in intel_hdmi_detect()
2551 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier); in intel_hdmi_detect()
2557 intel_hdmi_force(struct drm_connector *connector) in intel_hdmi_force() argument
2559 struct intel_display *display = to_intel_display(connector->dev); in intel_hdmi_force()
2560 struct drm_i915_private *i915 = to_i915(connector->dev); in intel_hdmi_force()
2562 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", in intel_hdmi_force()
2563 connector->base.id, connector->name); in intel_hdmi_force()
2568 intel_hdmi_unset_edid(connector); in intel_hdmi_force()
2570 if (connector->status != connector_status_connected) in intel_hdmi_force()
2573 intel_hdmi_set_edid(connector); in intel_hdmi_force()
2576 static int intel_hdmi_get_modes(struct drm_connector *connector) in intel_hdmi_get_modes() argument
2578 /* drm_edid_connector_update() done in ->detect() or ->force() */ in intel_hdmi_get_modes()
2579 return drm_edid_connector_add_modes(connector); in intel_hdmi_get_modes()
2583 intel_hdmi_connector_register(struct drm_connector *connector) in intel_hdmi_connector_register() argument
2587 ret = intel_connector_register(connector); in intel_hdmi_connector_register()
2594 static void intel_hdmi_connector_unregister(struct drm_connector *connector) in intel_hdmi_connector_unregister() argument
2596 struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier; in intel_hdmi_connector_unregister()
2600 intel_connector_unregister(connector); in intel_hdmi_connector_unregister()
2616 static int intel_hdmi_connector_atomic_check(struct drm_connector *connector, in intel_hdmi_connector_atomic_check() argument
2619 struct intel_display *display = to_intel_display(connector->dev); in intel_hdmi_connector_atomic_check()
2622 return intel_digital_connector_atomic_check(connector, state); in intel_hdmi_connector_atomic_check()
2624 return g4x_hdmi_connector_atomic_check(connector, state); in intel_hdmi_connector_atomic_check()
2634 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector) in intel_hdmi_add_properties() argument
2638 intel_attach_force_audio_property(connector); in intel_hdmi_add_properties()
2639 intel_attach_broadcast_rgb_property(connector); in intel_hdmi_add_properties()
2640 intel_attach_aspect_ratio_property(connector); in intel_hdmi_add_properties()
2642 intel_attach_hdmi_colorspace_property(connector); in intel_hdmi_add_properties()
2643 drm_connector_attach_content_type_property(connector); in intel_hdmi_add_properties()
2646 drm_connector_attach_hdr_output_metadata_property(connector); in intel_hdmi_add_properties()
2649 drm_connector_attach_max_bpc_property(connector, 8, 12); in intel_hdmi_add_properties()
2655 * @connector: drm_connector
2661 * This function handles scrambling on HDMI 2.0 capable sinks.
2663 * it enables scrambling. This should be called before enabling the HDMI
2671 struct drm_connector *connector, in intel_hdmi_handle_sink_scrambling() argument
2677 &connector->display_info.hdmi.scdc.scrambling; in intel_hdmi_handle_sink_scrambling()
2679 if (!sink_scrambling->supported) in intel_hdmi_handle_sink_scrambling()
2682 drm_dbg_kms(display->drm, in intel_hdmi_handle_sink_scrambling()
2683 "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n", in intel_hdmi_handle_sink_scrambling()
2684 connector->base.id, connector->name, in intel_hdmi_handle_sink_scrambling()
2688 return drm_scdc_set_high_tmds_clock_ratio(connector, high_tmds_clock_ratio) && in intel_hdmi_handle_sink_scrambling()
2689 drm_scdc_set_scrambling(connector, scrambling); in intel_hdmi_handle_sink_scrambling()
2694 enum port port = encoder->port; in chv_encoder_to_ddc_pin()
2717 enum port port = encoder->port; in bxt_encoder_to_ddc_pin()
2737 enum port port = encoder->port; in cnp_encoder_to_ddc_pin()
2764 enum port port = encoder->port; in icl_encoder_to_ddc_pin()
2771 drm_WARN(display->drm, 1, "Unknown port:%c\n", port_name(port)); in icl_encoder_to_ddc_pin()
2800 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in rkl_encoder_to_ddc_pin()
2803 WARN_ON(encoder->port == PORT_C); in rkl_encoder_to_ddc_pin()
2807 * final two outputs use type-c pins, even though they're actually in rkl_encoder_to_ddc_pin()
2808 * combo outputs. With CMP, the traditional DDI A-D pins are used for in rkl_encoder_to_ddc_pin()
2812 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; in rkl_encoder_to_ddc_pin()
2820 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in gen9bc_tgp_encoder_to_ddc_pin()
2823 drm_WARN_ON(display->drm, encoder->port == PORT_A); in gen9bc_tgp_encoder_to_ddc_pin()
2827 * final two outputs use type-c pins, even though they're actually in gen9bc_tgp_encoder_to_ddc_pin()
2828 * combo outputs. With CMP, the traditional DDI A-D pins are used for in gen9bc_tgp_encoder_to_ddc_pin()
2832 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C; in gen9bc_tgp_encoder_to_ddc_pin()
2846 WARN_ON(encoder->port == PORT_B || encoder->port == PORT_C); in adls_encoder_to_ddc_pin()
2849 * Pin mapping for ADL-S requires TC pins for all combo phy outputs in adls_encoder_to_ddc_pin()
2855 return GMBUS_PIN_9_TC1_ICP + phy - PHY_B; in adls_encoder_to_ddc_pin()
2860 enum port port = encoder->port; in g4x_encoder_to_ddc_pin()
2884 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_default_ddc_pin()
2916 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in get_encoder_by_ddc_pin()
2919 for_each_intel_encoder(display->drm, other) { in get_encoder_by_ddc_pin()
2920 struct intel_connector *connector; in get_encoder_by_ddc_pin() local
2928 connector = enc_to_dig_port(other)->hdmi.attached_connector; in get_encoder_by_ddc_pin()
2930 if (connector && connector->base.ddc == intel_gmbus_get_adapter(i915, ddc_pin)) in get_encoder_by_ddc_pin()
2940 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_hdmi_ddc_pin()
2945 ddc_pin = intel_bios_hdmi_ddc_pin(encoder->devdata); in intel_hdmi_ddc_pin()
2954 drm_dbg_kms(display->drm, in intel_hdmi_ddc_pin()
2956 encoder->base.base.id, encoder->base.name, ddc_pin); in intel_hdmi_ddc_pin()
2962 drm_dbg_kms(display->drm, in intel_hdmi_ddc_pin()
2964 encoder->base.base.id, encoder->base.name, ddc_pin, in intel_hdmi_ddc_pin()
2965 other->base.base.id, other->base.name); in intel_hdmi_ddc_pin()
2969 drm_dbg_kms(display->drm, in intel_hdmi_ddc_pin()
2971 encoder->base.base.id, encoder->base.name, in intel_hdmi_ddc_pin()
2981 to_i915(dig_port->base.base.dev); in intel_infoframe_init()
2984 dig_port->write_infoframe = vlv_write_infoframe; in intel_infoframe_init()
2985 dig_port->read_infoframe = vlv_read_infoframe; in intel_infoframe_init()
2986 dig_port->set_infoframes = vlv_set_infoframes; in intel_infoframe_init()
2987 dig_port->infoframes_enabled = vlv_infoframes_enabled; in intel_infoframe_init()
2989 dig_port->write_infoframe = g4x_write_infoframe; in intel_infoframe_init()
2990 dig_port->read_infoframe = g4x_read_infoframe; in intel_infoframe_init()
2991 dig_port->set_infoframes = g4x_set_infoframes; in intel_infoframe_init()
2992 dig_port->infoframes_enabled = g4x_infoframes_enabled; in intel_infoframe_init()
2994 if (intel_bios_encoder_is_lspcon(dig_port->base.devdata)) { in intel_infoframe_init()
2995 dig_port->write_infoframe = lspcon_write_infoframe; in intel_infoframe_init()
2996 dig_port->read_infoframe = lspcon_read_infoframe; in intel_infoframe_init()
2997 dig_port->set_infoframes = lspcon_set_infoframes; in intel_infoframe_init()
2998 dig_port->infoframes_enabled = lspcon_infoframes_enabled; in intel_infoframe_init()
3000 dig_port->write_infoframe = hsw_write_infoframe; in intel_infoframe_init()
3001 dig_port->read_infoframe = hsw_read_infoframe; in intel_infoframe_init()
3002 dig_port->set_infoframes = hsw_set_infoframes; in intel_infoframe_init()
3003 dig_port->infoframes_enabled = hsw_infoframes_enabled; in intel_infoframe_init()
3006 dig_port->write_infoframe = ibx_write_infoframe; in intel_infoframe_init()
3007 dig_port->read_infoframe = ibx_read_infoframe; in intel_infoframe_init()
3008 dig_port->set_infoframes = ibx_set_infoframes; in intel_infoframe_init()
3009 dig_port->infoframes_enabled = ibx_infoframes_enabled; in intel_infoframe_init()
3011 dig_port->write_infoframe = cpt_write_infoframe; in intel_infoframe_init()
3012 dig_port->read_infoframe = cpt_read_infoframe; in intel_infoframe_init()
3013 dig_port->set_infoframes = cpt_set_infoframes; in intel_infoframe_init()
3014 dig_port->infoframes_enabled = cpt_infoframes_enabled; in intel_infoframe_init()
3022 struct drm_connector *connector = &intel_connector->base; in intel_hdmi_init_connector() local
3023 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; in intel_hdmi_init_connector()
3024 struct intel_encoder *intel_encoder = &dig_port->base; in intel_hdmi_init_connector()
3025 struct drm_device *dev = intel_encoder->base.dev; in intel_hdmi_init_connector()
3027 enum port port = intel_encoder->port; in intel_hdmi_init_connector()
3031 drm_dbg_kms(display->drm, in intel_hdmi_init_connector()
3032 "Adding HDMI connector on [ENCODER:%d:%s]\n", in intel_hdmi_init_connector()
3033 intel_encoder->base.base.id, intel_encoder->base.name); in intel_hdmi_init_connector()
3038 if (drm_WARN(dev, dig_port->max_lanes < 4, in intel_hdmi_init_connector()
3039 "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", in intel_hdmi_init_connector()
3040 dig_port->max_lanes, intel_encoder->base.base.id, in intel_hdmi_init_connector()
3041 intel_encoder->base.name)) in intel_hdmi_init_connector()
3048 drm_connector_init_with_ddc(dev, connector, in intel_hdmi_init_connector()
3053 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs); in intel_hdmi_init_connector()
3056 connector->interlace_allowed = true; in intel_hdmi_init_connector()
3058 connector->stereo_allowed = true; in intel_hdmi_init_connector()
3061 connector->ycbcr_420_allowed = true; in intel_hdmi_init_connector()
3063 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; in intel_hdmi_init_connector()
3064 intel_connector->base.polled = intel_connector->polled; in intel_hdmi_init_connector()
3067 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; in intel_hdmi_init_connector()
3069 intel_connector->get_hw_state = intel_connector_get_hw_state; in intel_hdmi_init_connector()
3071 intel_hdmi_add_properties(intel_hdmi, connector); in intel_hdmi_init_connector()
3074 intel_hdmi->attached_connector = intel_connector; in intel_hdmi_init_connector()
3080 drm_dbg_kms(display->drm, in intel_hdmi_init_connector()
3084 cec_fill_conn_info_from_drm(&conn_info, connector); in intel_hdmi_init_connector()
3086 intel_hdmi->cec_notifier = in intel_hdmi_init_connector()
3087 cec_notifier_conn_register(dev->dev, port_identifier(port), in intel_hdmi_init_connector()
3089 if (!intel_hdmi->cec_notifier) in intel_hdmi_init_connector()
3090 drm_dbg_kms(display->drm, "CEC notifier get failed\n"); in intel_hdmi_init_connector()
3094 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height
3118 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder
3125 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink
3153 int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock; in intel_hdmi_dsc_get_num_slices()
3164 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 || in intel_hdmi_dsc_get_num_slices()
3165 crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) in intel_hdmi_dsc_get_num_slices()
3188 * clock per slice (in MHz) as read from HF-VSDB. in intel_hdmi_dsc_get_num_slices()
3200 * of PCON encoder and HDMI decoder can support. in intel_hdmi_dsc_get_num_slices()
3220 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices); in intel_hdmi_dsc_get_num_slices()
3229 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on
3258 * for each bpp we check if no of bytes can be supported by HDMI sink in intel_hdmi_dsc_get_bpp()
3307 bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16; in intel_hdmi_dsc_get_bpp()
3318 bpp_target_x16 -= bpp_decrement_x16; in intel_hdmi_dsc_get_bpp()