Lines Matching full:display
35 #include <drm/display/drm_hdcp_helper.h>
36 #include <drm/display/drm_hdmi_helper.h>
37 #include <drm/display/drm_scdc_helper.h>
66 struct intel_display *display = to_intel_display(intel_hdmi); in assert_hdmi_port_disabled() local
69 enabled_bits = HAS_DDI(display) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; in assert_hdmi_port_disabled()
71 drm_WARN(display->drm, in assert_hdmi_port_disabled()
72 intel_de_read(display, intel_hdmi->hdmi_reg) & enabled_bits, in assert_hdmi_port_disabled()
77 assert_hdmi_transcoder_func_disabled(struct intel_display *display, in assert_hdmi_transcoder_func_disabled() argument
80 drm_WARN(display->drm, in assert_hdmi_transcoder_func_disabled()
81 intel_de_read(display, TRANS_DDI_FUNC_CTL(display, cpu_transcoder)) & in assert_hdmi_transcoder_func_disabled()
156 hsw_dip_data_reg(struct intel_display *display, in hsw_dip_data_reg() argument
163 return HSW_TVIDEO_DIP_GMP_DATA(display, cpu_transcoder, i); in hsw_dip_data_reg()
165 return HSW_TVIDEO_DIP_VSC_DATA(display, cpu_transcoder, i); in hsw_dip_data_reg()
167 return ADL_TVIDEO_DIP_AS_SDP_DATA(display, cpu_transcoder, i); in hsw_dip_data_reg()
169 return ICL_VIDEO_DIP_PPS_DATA(display, cpu_transcoder, i); in hsw_dip_data_reg()
171 return HSW_TVIDEO_DIP_AVI_DATA(display, cpu_transcoder, i); in hsw_dip_data_reg()
173 return HSW_TVIDEO_DIP_SPD_DATA(display, cpu_transcoder, i); in hsw_dip_data_reg()
175 return HSW_TVIDEO_DIP_VS_DATA(display, cpu_transcoder, i); in hsw_dip_data_reg()
177 return GLK_TVIDEO_DIP_DRM_DATA(display, cpu_transcoder, i); in hsw_dip_data_reg()
184 static int hsw_dip_data_size(struct intel_display *display, in hsw_dip_data_size() argument
195 if (DISPLAY_VER(display) >= 11) in hsw_dip_data_size()
209 struct intel_display *display = to_intel_display(encoder); in g4x_write_infoframe() local
211 u32 val = intel_de_read(display, VIDEO_DIP_CTL); in g4x_write_infoframe()
214 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), in g4x_write_infoframe()
222 intel_de_write(display, VIDEO_DIP_CTL, val); in g4x_write_infoframe()
225 intel_de_write(display, VIDEO_DIP_DATA, *data); in g4x_write_infoframe()
230 intel_de_write(display, VIDEO_DIP_DATA, 0); in g4x_write_infoframe()
236 intel_de_write(display, VIDEO_DIP_CTL, val); in g4x_write_infoframe()
237 intel_de_posting_read(display, VIDEO_DIP_CTL); in g4x_write_infoframe()
245 struct intel_display *display = to_intel_display(encoder); in g4x_read_infoframe() local
249 intel_de_rmw(display, VIDEO_DIP_CTL, in g4x_read_infoframe()
253 *data++ = intel_de_read(display, VIDEO_DIP_DATA); in g4x_read_infoframe()
259 struct intel_display *display = to_intel_display(encoder); in g4x_infoframes_enabled() local
260 u32 val = intel_de_read(display, VIDEO_DIP_CTL); in g4x_infoframes_enabled()
277 struct intel_display *display = to_intel_display(encoder); in ibx_write_infoframe() local
281 u32 val = intel_de_read(display, reg); in ibx_write_infoframe()
284 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), in ibx_write_infoframe()
292 intel_de_write(display, reg, val); in ibx_write_infoframe()
295 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), in ibx_write_infoframe()
301 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0); in ibx_write_infoframe()
307 intel_de_write(display, reg, val); in ibx_write_infoframe()
308 intel_de_posting_read(display, reg); in ibx_write_infoframe()
316 struct intel_display *display = to_intel_display(encoder); in ibx_read_infoframe() local
321 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe), in ibx_read_infoframe()
325 *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe)); in ibx_read_infoframe()
331 struct intel_display *display = to_intel_display(encoder); in ibx_infoframes_enabled() local
334 u32 val = intel_de_read(display, reg); in ibx_infoframes_enabled()
352 struct intel_display *display = to_intel_display(encoder); in cpt_write_infoframe() local
356 u32 val = intel_de_read(display, reg); in cpt_write_infoframe()
359 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), in cpt_write_infoframe()
370 intel_de_write(display, reg, val); in cpt_write_infoframe()
373 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), in cpt_write_infoframe()
379 intel_de_write(display, TVIDEO_DIP_DATA(crtc->pipe), 0); in cpt_write_infoframe()
385 intel_de_write(display, reg, val); in cpt_write_infoframe()
386 intel_de_posting_read(display, reg); in cpt_write_infoframe()
394 struct intel_display *display = to_intel_display(encoder); in cpt_read_infoframe() local
399 intel_de_rmw(display, TVIDEO_DIP_CTL(crtc->pipe), in cpt_read_infoframe()
403 *data++ = intel_de_read(display, TVIDEO_DIP_DATA(crtc->pipe)); in cpt_read_infoframe()
409 struct intel_display *display = to_intel_display(encoder); in cpt_infoframes_enabled() local
411 u32 val = intel_de_read(display, TVIDEO_DIP_CTL(pipe)); in cpt_infoframes_enabled()
426 struct intel_display *display = to_intel_display(encoder); in vlv_write_infoframe() local
430 u32 val = intel_de_read(display, reg); in vlv_write_infoframe()
433 drm_WARN(display->drm, !(val & VIDEO_DIP_ENABLE), in vlv_write_infoframe()
441 intel_de_write(display, reg, val); in vlv_write_infoframe()
444 intel_de_write(display, in vlv_write_infoframe()
450 intel_de_write(display, in vlv_write_infoframe()
457 intel_de_write(display, reg, val); in vlv_write_infoframe()
458 intel_de_posting_read(display, reg); in vlv_write_infoframe()
466 struct intel_display *display = to_intel_display(encoder); in vlv_read_infoframe() local
471 intel_de_rmw(display, VLV_TVIDEO_DIP_CTL(crtc->pipe), in vlv_read_infoframe()
475 *data++ = intel_de_read(display, in vlv_read_infoframe()
482 struct intel_display *display = to_intel_display(encoder); in vlv_infoframes_enabled() local
484 u32 val = intel_de_read(display, VLV_TVIDEO_DIP_CTL(pipe)); in vlv_infoframes_enabled()
502 struct intel_display *display = to_intel_display(encoder); in hsw_write_infoframe() local
505 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(display, cpu_transcoder); in hsw_write_infoframe()
508 u32 val = intel_de_read(display, ctl_reg); in hsw_write_infoframe()
510 data_size = hsw_dip_data_size(display, type); in hsw_write_infoframe()
512 drm_WARN_ON(display->drm, len > data_size); in hsw_write_infoframe()
515 intel_de_write(display, ctl_reg, val); in hsw_write_infoframe()
518 intel_de_write(display, in hsw_write_infoframe()
519 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2), in hsw_write_infoframe()
525 intel_de_write(display, in hsw_write_infoframe()
526 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2), in hsw_write_infoframe()
530 if (!(IS_DISPLAY_VER(display, 13, 14) && crtc_state->has_psr && in hsw_write_infoframe()
537 intel_de_write(display, ctl_reg, val); in hsw_write_infoframe()
538 intel_de_posting_read(display, ctl_reg); in hsw_write_infoframe()
545 struct intel_display *display = to_intel_display(encoder); in hsw_read_infoframe() local
551 *data++ = intel_de_read(display, in hsw_read_infoframe()
552 hsw_dip_data_reg(display, cpu_transcoder, type, i >> 2)); in hsw_read_infoframe()
558 struct intel_display *display = to_intel_display(encoder); in hsw_infoframes_enabled() local
559 u32 val = intel_de_read(display, in hsw_infoframes_enabled()
560 HSW_TVIDEO_DIP_CTL(display, pipe_config->cpu_transcoder)); in hsw_infoframes_enabled()
567 if (DISPLAY_VER(display) >= 10) in hsw_infoframes_enabled()
570 if (HAS_AS_SDP(display)) in hsw_infoframes_enabled()
602 struct intel_display *display = to_intel_display(encoder); in intel_hdmi_infoframes_enabled() local
613 if (HAS_DDI(display)) { in intel_hdmi_infoframes_enabled()
828 struct intel_display *display = to_intel_display(encoder); in intel_hdmi_compute_drm_infoframe() local
832 if (DISPLAY_VER(display) < 10) in intel_hdmi_compute_drm_infoframe()
846 drm_dbg_kms(display->drm, in intel_hdmi_compute_drm_infoframe()
852 if (drm_WARN_ON(display->drm, ret)) in intel_hdmi_compute_drm_infoframe()
863 struct intel_display *display = to_intel_display(encoder); in g4x_set_infoframes() local
867 u32 val = intel_de_read(display, reg); in g4x_set_infoframes()
887 drm_dbg_kms(display->drm, in g4x_set_infoframes()
894 intel_de_write(display, reg, val); in g4x_set_infoframes()
895 intel_de_posting_read(display, reg); in g4x_set_infoframes()
901 drm_dbg_kms(display->drm, in g4x_set_infoframes()
914 intel_de_write(display, reg, val); in g4x_set_infoframes()
915 intel_de_posting_read(display, reg); in g4x_set_infoframes()
975 struct intel_display *display = to_intel_display(encoder); in intel_hdmi_set_gcp_infoframe() local
984 if (HAS_DDI(display)) in intel_hdmi_set_gcp_infoframe()
985 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder); in intel_hdmi_set_gcp_infoframe()
993 intel_de_write(display, reg, crtc_state->infoframes.gcp); in intel_hdmi_set_gcp_infoframe()
1001 struct intel_display *display = to_intel_display(encoder); in intel_hdmi_read_gcp_infoframe() local
1010 if (HAS_DDI(display)) in intel_hdmi_read_gcp_infoframe()
1011 reg = HSW_TVIDEO_DIP_GCP(display, crtc_state->cpu_transcoder); in intel_hdmi_read_gcp_infoframe()
1019 crtc_state->infoframes.gcp = intel_de_read(display, reg); in intel_hdmi_read_gcp_infoframe()
1038 /* Enable default_phase whenever the display mode is suitably aligned */ in intel_hdmi_compute_gcp_infoframe()
1049 struct intel_display *display = to_intel_display(encoder); in ibx_set_infoframes() local
1054 u32 val = intel_de_read(display, reg); in ibx_set_infoframes()
1068 intel_de_write(display, reg, val); in ibx_set_infoframes()
1069 intel_de_posting_read(display, reg); in ibx_set_infoframes()
1074 drm_WARN(display->drm, val & VIDEO_DIP_ENABLE, in ibx_set_infoframes()
1089 intel_de_write(display, reg, val); in ibx_set_infoframes()
1090 intel_de_posting_read(display, reg); in ibx_set_infoframes()
1108 struct intel_display *display = to_intel_display(encoder); in cpt_set_infoframes() local
1112 u32 val = intel_de_read(display, reg); in cpt_set_infoframes()
1125 intel_de_write(display, reg, val); in cpt_set_infoframes()
1126 intel_de_posting_read(display, reg); in cpt_set_infoframes()
1138 intel_de_write(display, reg, val); in cpt_set_infoframes()
1139 intel_de_posting_read(display, reg); in cpt_set_infoframes()
1157 struct intel_display *display = to_intel_display(encoder); in vlv_set_infoframes() local
1161 u32 val = intel_de_read(display, reg); in vlv_set_infoframes()
1175 intel_de_write(display, reg, val); in vlv_set_infoframes()
1176 intel_de_posting_read(display, reg); in vlv_set_infoframes()
1181 drm_WARN(display->drm, val & VIDEO_DIP_ENABLE, in vlv_set_infoframes()
1196 intel_de_write(display, reg, val); in vlv_set_infoframes()
1197 intel_de_posting_read(display, reg); in vlv_set_infoframes()
1215 struct intel_display *display = to_intel_display(encoder); in hsw_set_infoframes() local
1216 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(display, in hsw_set_infoframes()
1218 u32 val = intel_de_read(display, reg); in hsw_set_infoframes()
1220 assert_hdmi_transcoder_func_disabled(display, in hsw_set_infoframes()
1229 intel_de_write(display, reg, val); in hsw_set_infoframes()
1230 intel_de_posting_read(display, reg); in hsw_set_infoframes()
1237 intel_de_write(display, reg, val); in hsw_set_infoframes()
1238 intel_de_posting_read(display, reg); in hsw_set_infoframes()
1256 struct intel_display *display = to_intel_display(hdmi); in intel_dp_dual_mode_set_tmds_output() local
1262 drm_dbg_kms(display->drm, "%s DP dual mode adaptor TMDS output\n", in intel_dp_dual_mode_set_tmds_output()
1265 drm_dp_dual_mode_set_tmds_output(display->drm, in intel_dp_dual_mode_set_tmds_output()
1331 struct intel_display *display = to_intel_display(dig_port); in intel_hdmi_hdcp_write_an_aksv() local
1339 drm_dbg_kms(display->drm, "Write An over DDC failed (%d)\n", in intel_hdmi_hdcp_write_an_aksv()
1346 drm_dbg_kms(display->drm, "Failed to output aksv (%d)\n", ret); in intel_hdmi_hdcp_write_an_aksv()
1355 struct intel_display *display = to_intel_display(dig_port); in intel_hdmi_hdcp_read_bksv() local
1361 drm_dbg_kms(display->drm, "Read Bksv over DDC failed (%d)\n", in intel_hdmi_hdcp_read_bksv()
1370 struct intel_display *display = to_intel_display(dig_port); in intel_hdmi_hdcp_read_bstatus() local
1376 drm_dbg_kms(display->drm, in intel_hdmi_hdcp_read_bstatus()
1386 struct intel_display *display = to_intel_display(dig_port); in intel_hdmi_hdcp_repeater_present() local
1392 drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n", in intel_hdmi_hdcp_repeater_present()
1404 struct intel_display *display = to_intel_display(dig_port); in intel_hdmi_hdcp_read_ri_prime() local
1410 drm_dbg_kms(display->drm, "Read Ri' over DDC failed (%d)\n", in intel_hdmi_hdcp_read_ri_prime()
1419 struct intel_display *display = to_intel_display(dig_port); in intel_hdmi_hdcp_read_ksv_ready() local
1425 drm_dbg_kms(display->drm, "Read bcaps over DDC failed (%d)\n", in intel_hdmi_hdcp_read_ksv_ready()
1437 struct intel_display *display = to_intel_display(dig_port); in intel_hdmi_hdcp_read_ksv_fifo() local
1442 drm_dbg_kms(display->drm, in intel_hdmi_hdcp_read_ksv_fifo()
1453 struct intel_display *display = to_intel_display(dig_port); in intel_hdmi_hdcp_read_v_prime_part() local
1462 drm_dbg_kms(display->drm, in intel_hdmi_hdcp_read_v_prime_part()
1471 struct intel_display *display = to_intel_display(connector); in kbl_repositioning_enc_en_signal() local
1478 scanline = intel_de_read(display, in kbl_repositioning_enc_en_signal()
1479 PIPEDSL(display, crtc->pipe)); in kbl_repositioning_enc_en_signal()
1488 drm_err(display->drm, in kbl_repositioning_enc_en_signal()
1496 drm_err(display->drm, in kbl_repositioning_enc_en_signal()
1509 struct intel_display *display = to_intel_display(dig_port); in intel_hdmi_hdcp_toggle_signalling() local
1522 drm_err(display->drm, "%s HDCP signalling failed (%d)\n", in intel_hdmi_hdcp_toggle_signalling()
1542 struct intel_display *display = to_intel_display(dig_port); in intel_hdmi_hdcp_check_link_once() local
1562 drm_dbg_kms(display->drm, "Ri' mismatch detected (%x)\n", in intel_hdmi_hdcp_check_link_once()
1574 struct intel_display *display = to_intel_display(dig_port); in intel_hdmi_hdcp_check_link() local
1581 drm_err(display->drm, "Link check failed\n"); in intel_hdmi_hdcp_check_link()
1632 struct intel_display *display = to_intel_display(dig_port); in hdcp2_detect_msg_availability() local
1638 drm_dbg_kms(display->drm, "rx_status read failed. Err %d\n", in hdcp2_detect_msg_availability()
1659 struct intel_display *display = to_intel_display(dig_port); in intel_hdmi_hdcp2_wait_for_msg() local
1674 drm_dbg_kms(display->drm, in intel_hdmi_hdcp2_wait_for_msg()
1696 struct intel_display *display = to_intel_display(connector); in intel_hdmi_hdcp2_read_msg() local
1713 drm_dbg_kms(display->drm, in intel_hdmi_hdcp2_read_msg()
1722 drm_dbg_kms(display->drm, "Failed to read msg_id: %d(%zd)\n", in intel_hdmi_hdcp2_read_msg()
1788 struct intel_display *display = to_intel_display(encoder); in intel_hdmi_source_max_tmds_clock() local
1792 if (DISPLAY_VER(display) >= 13 || IS_ALDERLAKE_S(dev_priv)) in intel_hdmi_source_max_tmds_clock()
1794 else if (DISPLAY_VER(display) >= 10) in intel_hdmi_source_max_tmds_clock()
1796 else if (DISPLAY_VER(display) >= 8 || IS_HASWELL(dev_priv)) in intel_hdmi_source_max_tmds_clock()
1798 else if (DISPLAY_VER(display) >= 5) in intel_hdmi_source_max_tmds_clock()
1854 struct intel_display *display = to_intel_display(hdmi); in hdmi_port_clock_valid() local
1855 struct drm_i915_private *dev_priv = to_i915(display->drm); in hdmi_port_clock_valid()
1892 if (DISPLAY_VER(display) >= 14) in hdmi_port_clock_valid()
1915 static bool intel_hdmi_source_bpc_possible(struct intel_display *display, int bpc) in intel_hdmi_source_bpc_possible() argument
1919 return !HAS_GMCH(display); in intel_hdmi_source_bpc_possible()
1921 return DISPLAY_VER(display) >= 11; in intel_hdmi_source_bpc_possible()
1967 struct intel_display *display = to_intel_display(connector->dev); in intel_hdmi_mode_clock_valid() local
1980 if (!intel_hdmi_source_bpc_possible(display, bpc)) in intel_hdmi_mode_clock_valid()
1992 drm_WARN_ON(display->drm, status == MODE_OK); in intel_hdmi_mode_clock_valid()
2001 struct intel_display *display = to_intel_display(connector->dev); in intel_hdmi_mode_valid() local
2003 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_hdmi_mode_valid()
2006 int max_dotclk = to_i915(connector->dev)->display.cdclk.max_dotclk_freq; in intel_hdmi_mode_valid()
2081 struct intel_display *display = to_intel_display(crtc_state); in hdmi_bpc_possible() local
2085 if (!intel_hdmi_source_bpc_possible(display, bpc)) in hdmi_bpc_possible()
2088 /* Display Wa_1405510057:icl,ehl */ in hdmi_bpc_possible()
2090 bpc == 10 && DISPLAY_VER(display) == 11 && in hdmi_bpc_possible()
2137 struct intel_display *display = to_intel_display(encoder); in intel_hdmi_compute_clock() local
2160 drm_dbg_kms(display->drm, in intel_hdmi_compute_clock()
2237 struct intel_display *display = to_intel_display(encoder); in intel_hdmi_compute_output_format() local
2248 drm_dbg_kms(display->drm, in intel_hdmi_compute_output_format()
2309 struct intel_display *display = to_intel_display(encoder); in intel_hdmi_compute_config() local
2342 drm_dbg_kms(display->drm, in intel_hdmi_compute_config()
2377 drm_dbg_kms(display->drm, "bad AVI infoframe\n"); in intel_hdmi_compute_config()
2382 drm_dbg_kms(display->drm, "bad SPD infoframe\n"); in intel_hdmi_compute_config()
2387 drm_dbg_kms(display->drm, "bad HDMI infoframe\n"); in intel_hdmi_compute_config()
2392 drm_dbg_kms(display->drm, "bad DRM infoframe\n"); in intel_hdmi_compute_config()
2425 struct intel_display *display = to_intel_display(connector->dev); in intel_hdmi_dp_dual_mode_detect() local
2432 type = drm_dp_dual_mode_detect(display->drm, ddc); in intel_hdmi_dp_dual_mode_detect()
2446 drm_dbg_kms(display->drm, in intel_hdmi_dp_dual_mode_detect()
2459 drm_dp_dual_mode_max_tmds_clock(display->drm, type, ddc); in intel_hdmi_dp_dual_mode_detect()
2461 drm_dbg_kms(display->drm, in intel_hdmi_dp_dual_mode_detect()
2467 if ((DISPLAY_VER(display) >= 8 || IS_HASWELL(dev_priv)) && in intel_hdmi_dp_dual_mode_detect()
2469 drm_dbg_kms(display->drm, in intel_hdmi_dp_dual_mode_detect()
2478 struct intel_display *display = to_intel_display(connector->dev); in intel_hdmi_set_edid() local
2491 drm_dbg_kms(display->drm, in intel_hdmi_set_edid()
2498 /* Below we depend on display info having been updated */ in intel_hdmi_set_edid()
2520 struct intel_display *display = to_intel_display(connector->dev); in intel_hdmi_detect() local
2527 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", in intel_hdmi_detect()
2538 if (DISPLAY_VER(display) >= 11 && in intel_hdmi_detect()
2559 struct intel_display *display = to_intel_display(connector->dev); in intel_hdmi_force() local
2562 drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s]\n", in intel_hdmi_force()
2619 struct intel_display *display = to_intel_display(connector->dev); in intel_hdmi_connector_atomic_check() local
2621 if (HAS_DDI(display)) in intel_hdmi_connector_atomic_check()
2636 struct intel_display *display = to_intel_display(intel_hdmi); in intel_hdmi_add_properties() local
2645 if (DISPLAY_VER(display) >= 10) in intel_hdmi_add_properties()
2648 if (!HAS_GMCH(display)) in intel_hdmi_add_properties()
2675 struct intel_display *display = to_intel_display(encoder); in intel_hdmi_handle_sink_scrambling() local
2682 drm_dbg_kms(display->drm, in intel_hdmi_handle_sink_scrambling()
2763 struct intel_display *display = to_intel_display(encoder); in icl_encoder_to_ddc_pin() local
2771 drm_WARN(display->drm, 1, "Unknown port:%c\n", port_name(port)); in icl_encoder_to_ddc_pin()
2819 struct intel_display *display = to_intel_display(encoder); in gen9bc_tgp_encoder_to_ddc_pin() local
2823 drm_WARN_ON(display->drm, encoder->port == PORT_A); in gen9bc_tgp_encoder_to_ddc_pin()
2883 struct intel_display *display = to_intel_display(encoder); in intel_hdmi_default_ddc_pin() local
2893 else if (DISPLAY_VER(display) == 9 && HAS_PCH_TGP(dev_priv)) in intel_hdmi_default_ddc_pin()
2915 struct intel_display *display = to_intel_display(encoder); in get_encoder_by_ddc_pin() local
2919 for_each_intel_encoder(display->drm, other) { in get_encoder_by_ddc_pin()
2939 struct intel_display *display = to_intel_display(encoder); in intel_hdmi_ddc_pin() local
2954 drm_dbg_kms(display->drm, in intel_hdmi_ddc_pin()
2962 drm_dbg_kms(display->drm, in intel_hdmi_ddc_pin()
2969 drm_dbg_kms(display->drm, in intel_hdmi_ddc_pin()
2979 struct intel_display *display = to_intel_display(dig_port); in intel_infoframe_init() local
2993 } else if (HAS_DDI(display)) { in intel_infoframe_init()
3021 struct intel_display *display = to_intel_display(dig_port); in intel_hdmi_init_connector() local
3031 drm_dbg_kms(display->drm, in intel_hdmi_init_connector()
3035 if (DISPLAY_VER(display) < 12 && drm_WARN_ON(dev, port == PORT_A)) in intel_hdmi_init_connector()
3055 if (DISPLAY_VER(display) < 12) in intel_hdmi_init_connector()
3060 if (DISPLAY_VER(display) >= 10) in intel_hdmi_init_connector()
3066 if (HAS_DDI(display)) in intel_hdmi_init_connector()
3080 drm_dbg_kms(display->drm, in intel_hdmi_init_connector()
3090 drm_dbg_kms(display->drm, "CEC notifier get failed\n"); in intel_hdmi_init_connector()
3095 * @vactive: Vactive of a display mode