39  * DOC: fifo underrun handling
45  * If an underrun is detected this is logged into dmesg. To avoid flooding logs
46  * and occupying the cpu underrun interrupts are disabled after the first
49  * Note that underrun detection on gmch platforms is a bit more ugly since there
51  * interrupt register). Also on some other platforms underrun interrupts are
52  * shared, which means that if we detect an underrun we need to disable underrun
55  * The code also supports underrun detection on the PCH transcoder.
110 	drm_err(&dev_priv->drm, "pipe %c underrun\n", pipe_name(crtc->pipe));  in i9xx_check_fifo_underruns()
130 			drm_err(&dev_priv->drm, "pipe %c underrun\n",  in i9xx_set_fifo_underrun_reporting()
163 	drm_err(&dev_priv->drm, "fifo underrun on pipe %c\n", pipe_name(pipe));  in ivb_check_fifo_underruns()
185 				"uncleared fifo underrun on pipe %c\n",  in ivb_set_fifo_underrun_reporting()
252 	drm_err(&dev_priv->drm, "pch fifo underrun on pch transcoder %c\n",  in cpt_check_pch_fifo_underruns()
276 				"uncleared pch fifo underrun on pch transcoder %c\n",  in cpt_set_fifo_underrun_reporting()
312  * This function sets the fifo underrun state for @pipe. It is used in the
316  * Notice that on some platforms disabling underrun reports for one pipe
320  * Returns the previous state of underrun reporting.
337  * intel_set_pch_fifo_underrun_reporting - set PCH fifo underrun reporting state
344  * underrun reporting for one transcoder may also disable all the other PCH
348  * Returns the previous state of underrun reporting.
363 	 * underrun statistics in crtc A. Since we never expose this anywhere  in intel_set_pch_fifo_underrun_reporting()
364 	 * nor use it outside of the fifo underrun code here using the "wrong"  in intel_set_pch_fifo_underrun_reporting()
387  * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt
391  * This handles a CPU fifo underrun interrupt, generating an underrun warning
392  * into dmesg if underrun reporting is enabled and then disables the underrun
412 	 * whether an underrun has happened, and on XELPD+, it will also record  in intel_cpu_fifo_underrun_irq_handler()
413 	 * whether the underrun was soft/hard and whether it was triggered by  in intel_cpu_fifo_underrun_irq_handler()
417 	 * Note that although the IIR gives us the same underrun and soft/hard  in intel_cpu_fifo_underrun_irq_handler()
419 	 * the underrun was caused by the downstream port.  in intel_cpu_fifo_underrun_irq_handler()
433 			drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun: %s%s%s%s\n",  in intel_cpu_fifo_underrun_irq_handler()
440 			drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));  in intel_cpu_fifo_underrun_irq_handler()
447  * intel_pch_fifo_underrun_irq_handler - handle PCH fifo underrun interrupt
451  * This handles a PCH fifo underrun interrupt, generating an underrun warning
452  * into dmesg if underrun reporting is enabled and then disables the underrun
461 		drm_err(&dev_priv->drm, "PCH transcoder %c FIFO underrun\n",  in intel_pch_fifo_underrun_irq_handler()
526 	 * We track the PCH trancoder underrun reporting state  in intel_init_fifo_underrun_reporting()
527 	 * within the crtc. With crtc for pipe A housing the underrun  in intel_init_fifo_underrun_reporting()
530 	 * and marking underrun reporting as disabled for the non-existing  in intel_init_fifo_underrun_reporting()