Lines Matching full:pipe

47  * occurrence until the next modeset on a given pipe.
50 * is no interrupt (despite that the signalling bit is in the PIPESTAT pipe
62 enum pipe pipe; in ivb_can_enable_err_int() local
66 for_each_pipe(dev_priv, pipe) { in ivb_can_enable_err_int()
67 crtc = intel_crtc_for_pipe(dev_priv, pipe); in ivb_can_enable_err_int()
79 enum pipe pipe; in cpt_can_enable_serr_int() local
84 for_each_pipe(dev_priv, pipe) { in cpt_can_enable_serr_int()
85 crtc = intel_crtc_for_pipe(dev_priv, pipe); in cpt_can_enable_serr_int()
97 i915_reg_t reg = PIPESTAT(dev_priv, crtc->pipe); in i9xx_check_fifo_underruns()
105 enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe); in i9xx_check_fifo_underruns()
109 trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe); in i9xx_check_fifo_underruns()
110 drm_err(&dev_priv->drm, "pipe %c underrun\n", pipe_name(crtc->pipe)); in i9xx_check_fifo_underruns()
114 enum pipe pipe, in i9xx_set_fifo_underrun_reporting() argument
118 i915_reg_t reg = PIPESTAT(dev_priv, pipe); in i9xx_set_fifo_underrun_reporting()
123 u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); in i9xx_set_fifo_underrun_reporting()
130 drm_err(&dev_priv->drm, "pipe %c underrun\n", in i9xx_set_fifo_underrun_reporting()
131 pipe_name(pipe)); in i9xx_set_fifo_underrun_reporting()
136 enum pipe pipe, bool enable) in ilk_set_fifo_underrun_reporting() argument
139 u32 bit = (pipe == PIPE_A) ? in ilk_set_fifo_underrun_reporting()
151 enum pipe pipe = crtc->pipe; in ivb_check_fifo_underruns() local
156 if ((err_int & ERR_INT_FIFO_UNDERRUN(pipe)) == 0) in ivb_check_fifo_underruns()
159 intel_de_write(dev_priv, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); in ivb_check_fifo_underruns()
162 trace_intel_cpu_fifo_underrun(dev_priv, pipe); in ivb_check_fifo_underruns()
163 drm_err(&dev_priv->drm, "fifo underrun on pipe %c\n", pipe_name(pipe)); in ivb_check_fifo_underruns()
167 enum pipe pipe, bool enable, in ivb_set_fifo_underrun_reporting() argument
173 ERR_INT_FIFO_UNDERRUN(pipe)); in ivb_set_fifo_underrun_reporting()
183 intel_de_read(dev_priv, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { in ivb_set_fifo_underrun_reporting()
185 "uncleared fifo underrun on pipe %c\n", in ivb_set_fifo_underrun_reporting()
186 pipe_name(pipe)); in ivb_set_fifo_underrun_reporting()
205 enum pipe pipe, bool enable) in bdw_set_fifo_underrun_reporting() argument
213 ICL_PIPESTATUS(dev_priv, pipe), in bdw_set_fifo_underrun_reporting()
216 bdw_enable_pipe_irq(dev_priv, pipe, mask); in bdw_set_fifo_underrun_reporting()
218 bdw_disable_pipe_irq(dev_priv, pipe, mask); in bdw_set_fifo_underrun_reporting()
223 enum pipe pch_transcoder, in ibx_set_fifo_underrun_reporting()
239 enum pipe pch_transcoder = crtc->pipe; in cpt_check_pch_fifo_underruns()
257 enum pipe pch_transcoder, in cpt_set_fifo_underrun_reporting()
283 enum pipe pipe, bool enable) in __intel_set_cpu_fifo_underrun_reporting() argument
286 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); in __intel_set_cpu_fifo_underrun_reporting()
295 i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old); in __intel_set_cpu_fifo_underrun_reporting()
297 ilk_set_fifo_underrun_reporting(dev, pipe, enable); in __intel_set_cpu_fifo_underrun_reporting()
299 ivb_set_fifo_underrun_reporting(dev, pipe, enable, old); in __intel_set_cpu_fifo_underrun_reporting()
301 bdw_set_fifo_underrun_reporting(dev, pipe, enable); in __intel_set_cpu_fifo_underrun_reporting()
309 * @pipe: (CPU) pipe to set state for
312 * This function sets the fifo underrun state for @pipe. It is used in the
314 * expected when disabling or enabling the pipe.
316 * Notice that on some platforms disabling underrun reports for one pipe
317 * disables for all due to shared interrupts. Actual reporting is still per-pipe
323 enum pipe pipe, bool enable) in intel_set_cpu_fifo_underrun_reporting() argument
329 ret = __intel_set_cpu_fifo_underrun_reporting(&dev_priv->drm, pipe, in intel_set_cpu_fifo_underrun_reporting()
339 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
351 enum pipe pch_transcoder, in intel_set_pch_fifo_underrun_reporting()
360 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT in intel_set_pch_fifo_underrun_reporting()
362 * pch transcoder -> pipe lookups from interrupt code simply store the in intel_set_pch_fifo_underrun_reporting()
389 * @pipe: (CPU) pipe to set state for
396 enum pipe pipe) in intel_cpu_fifo_underrun_irq_handler() argument
398 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); in intel_cpu_fifo_underrun_irq_handler()
423 ICL_PIPESTATUS(dev_priv, pipe)) & in intel_cpu_fifo_underrun_irq_handler()
425 intel_de_write(dev_priv, ICL_PIPESTATUS(dev_priv, pipe), in intel_cpu_fifo_underrun_irq_handler()
429 if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) { in intel_cpu_fifo_underrun_irq_handler()
430 trace_intel_cpu_fifo_underrun(dev_priv, pipe); in intel_cpu_fifo_underrun_irq_handler()
433 drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun: %s%s%s%s\n", in intel_cpu_fifo_underrun_irq_handler()
434 pipe_name(pipe), in intel_cpu_fifo_underrun_irq_handler()
440 drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe)); in intel_cpu_fifo_underrun_irq_handler()
449 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
456 enum pipe pch_transcoder) in intel_pch_fifo_underrun_irq_handler()
527 * within the crtc. With crtc for pipe A housing the underrun in intel_init_fifo_underrun_reporting()
528 * reporting state for PCH transcoder A, crtc for pipe B housing in intel_init_fifo_underrun_reporting()
534 if (intel_has_pch_trancoder(i915, crtc->pipe)) in intel_init_fifo_underrun_reporting()