Lines Matching +full:0 +full:x46000

11 #define FDI_PLL_BIOS_0  _MMIO(0x46000)
12 #define  FDI_PLL_FB_CLOCK_MASK  0xff
13 #define FDI_PLL_BIOS_1  _MMIO(0x46004)
14 #define FDI_PLL_BIOS_2  _MMIO(0x46008)
15 #define DISPLAY_PORT_PLL_BIOS_0         _MMIO(0x4600c)
16 #define DISPLAY_PORT_PLL_BIOS_1         _MMIO(0x46010)
17 #define DISPLAY_PORT_PLL_BIOS_2         _MMIO(0x46014)
19 #define FDI_PLL_FREQ_CTL        _MMIO(0x46030)
21 #define  FDI_PLL_FREQ_LOCK_LIMIT_MASK   0xfff00
22 #define  FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK  0xff
24 #define _FDI_RXA_CHICKEN        0xc200c
25 #define _FDI_RXB_CHICKEN        0xc2010
27 #define  FDI_RX_PHASE_SYNC_POINTER_EN	(1 << 0)
31 #define _FDI_TXA_CTL            0x60100
32 #define _FDI_TXB_CTL            0x61100
34 #define  FDI_TX_DISABLE         (0 << 31)
36 #define  FDI_LINK_TRAIN_PATTERN_1       (0 << 28)
40 #define  FDI_LINK_TRAIN_VOLTAGE_0_4V    (0 << 25)
44 #define  FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0 << 22)
48 /* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
51 #define  FDI_LINK_TRAIN_400MV_0DB_SNB_A		(0x38 << 22)
52 #define  FDI_LINK_TRAIN_400MV_6DB_SNB_A		(0x02 << 22)
53 #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_A	(0x01 << 22)
54 #define  FDI_LINK_TRAIN_800MV_0DB_SNB_A		(0x0 << 22)
56 #define  FDI_LINK_TRAIN_400MV_0DB_SNB_B		(0x0 << 22)
57 #define  FDI_LINK_TRAIN_400MV_6DB_SNB_B		(0x3a << 22)
58 #define  FDI_LINK_TRAIN_600MV_3_5DB_SNB_B	(0x39 << 22)
59 #define  FDI_LINK_TRAIN_800MV_0DB_SNB_B		(0x38 << 22)
60 #define  FDI_LINK_TRAIN_VOL_EMP_MASK		(0x3f << 22)
69 #define  FDI_LINK_TRAIN_PATTERN_1_IVB       (0 << 8)
77 #define  FDI_SCRAMBLING_ENABLE          (0 << 7)
81 #define _FDI_RXA_CTL             0xf000c
82 #define _FDI_RXB_CTL             0xf100c
89 #define  FDI_8BPC                       (0 << 16)
104 #define  FDI_LINK_TRAIN_PATTERN_1_CPT		(0 << 8)
110 #define _FDI_RXA_MISC			0xf0010
111 #define _FDI_RXB_MISC			0xf1010
118 #define  FDI_RX_FDI_DELAY_90		(0x90 << 0)
121 #define _FDI_RXA_TUSIZE1        0xf0030
122 #define _FDI_RXA_TUSIZE2        0xf0038
123 #define _FDI_RXB_TUSIZE1        0xf1030
124 #define _FDI_RXB_TUSIZE2        0xf1038
139 #define FDI_RX_SYMBOL_QUEUE_OVERFLOW    (1 << 0)
141 #define _FDI_RXA_IIR            0xf0014
142 #define _FDI_RXA_IMR            0xf0018
143 #define _FDI_RXB_IIR            0xf1014
144 #define _FDI_RXB_IMR            0xf1018
148 #define FDI_PLL_CTL_1           _MMIO(0xfe000)
149 #define FDI_PLL_CTL_2           _MMIO(0xfe004)