Lines Matching +full:0 +full:x3200
9 #define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */
10 #define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */
11 #define FBC_CONTROL _MMIO(0x3208)
21 #define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
23 #define FBC_COMMAND _MMIO(0x320c)
24 #define FBC_CMD_COMPRESS REG_BIT(0)
25 #define FBC_STATUS _MMIO(0x3210)
29 #define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0)
30 #define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */
33 #define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0)
38 #define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0)
40 #define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */
41 #define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */
43 #define FBC_MOD_NUM_VALID REG_BIT(0)
44 #define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */
45 #define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */
46 #define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0)
53 #define DPFC_CB_BASE _MMIO(0x3200)
54 #define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240)
55 #define DPFC_CONTROL _MMIO(0x3208)
56 #define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248)
71 #define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0)
74 #define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0)
76 #define DPFC_RECOMP_CTL _MMIO(0x320c)
77 #define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c)
80 #define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0)
81 #define DPFC_STATUS _MMIO(0x3210)
82 #define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250)
84 #define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0)
85 #define DPFC_STATUS2 _MMIO(0x3214)
86 #define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254)
87 #define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0)
88 #define DPFC_FENCE_YOFF _MMIO(0x3218)
89 #define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258)
90 #define DPFC_CHICKEN _MMIO(0x3224)
91 #define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264)
98 #define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268)
100 #define FBC_STRIDE_MASK REG_GENMASK(14, 0)
103 #define ILK_FBC_RT_BASE _MMIO(0x2128)
104 #define ILK_FBC_RT_VALID REG_BIT(0)
107 #define SNB_DPFC_CTL_SA _MMIO(0x100100)
109 #define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0)
111 #define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104)
113 #define IVB_FBC_RT_BASE _MMIO(0x7020)
114 #define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024)
116 #define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384)