26  * "The Color Control Surface (CCS) contains the compression status of
28  *  is specified by 2 bits in the CCS. Each CCS cache-line represents
30  *  cache-line-pairs. CCS is always Y tiled."
33  * each cache line in the CCS corresponds to an area of 32x16 cache
35  * us a ratio of one byte in the CCS for each 8x16 pixels in the
50  * Gen-12 compression uses 4 bits of CCS data for each cache line pair in the
51  * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
53  * 32x32 pixels, the ratio turns out to 1B in the CCS for every 2x32 pixels in
152 	} ccs;  member
178 		.ccs.packed_aux_planes = BIT(1),
179 		.ccs.planar_aux_planes = BIT(2) | BIT(3),
187 		.ccs.packed_aux_planes = BIT(1),
195 		.ccs.cc_planes = BIT(2),
196 		.ccs.packed_aux_planes = BIT(1),
208 		.ccs.cc_planes = BIT(1),
224 		.ccs.packed_aux_planes = BIT(1),
225 		.ccs.planar_aux_planes = BIT(2) | BIT(3),
233 		.ccs.packed_aux_planes = BIT(1),
241 		.ccs.cc_planes = BIT(2),
242 		.ccs.packed_aux_planes = BIT(1),
250 		.ccs.packed_aux_planes = BIT(1),
258 		.ccs.packed_aux_planes = BIT(1),
384  * intel_fb_is_ccs_modifier: Check if a modifier is a CCS modifier type
398  * intel_fb_is_rc_ccs_cc_modifier: Check if a modifier is an RC CCS CC modifier type
411  * intel_fb_is_mc_ccs_modifier: Check if a modifier is an MC CCS modifier type
472 	 * Separate AuxCCS and Flat CCS modifiers to be run only on platforms  in plane_has_modifier()
476 	    HAS_FLAT_CCS(i915) != !md->ccs.packed_aux_planes)  in plane_has_modifier()
550 	if (hweight8(md->ccs.planar_aux_planes) == 2)  in format_is_yuv_semiplanar()
574 		return md->ccs.planar_aux_planes;  in ccs_aux_plane_mask()
576 		return md->ccs.packed_aux_planes;  in ccs_aux_plane_mask()
580  * intel_fb_is_ccs_aux_plane: Check if a framebuffer color plane is a CCS AUX plane
585  * Returns %true if @fb's color plane at index @color_plane is a CCS AUX plane.
595  * intel_fb_is_gen12_ccs_aux_plane: Check if a framebuffer color plane is a GEN12 CCS AUX plane
600  * Returns %true if @fb's color plane at index @color_plane is a GEN12 CCS AUX plane.
611  * intel_fb_rc_ccs_cc_plane: Get the CCS CC color plane index for a framebuffer
622 	if (!md->ccs.cc_planes)  in intel_fb_rc_ccs_cc_plane()
625 	drm_WARN_ON_ONCE(fb->dev, hweight8(md->ccs.cc_planes) > 1);  in intel_fb_rc_ccs_cc_plane()
627 	return ilog2((int)md->ccs.cc_planes);  in intel_fb_rc_ccs_cc_plane()
675 	if (md->ccs.packed_aux_planes | md->ccs.planar_aux_planes)  in skl_main_to_aux_plane()
782  * it's a 64 byte portion of the tile on TGL+ CCS surfaces.
837 	 * TODO: Deduct the subsampling from the char block for all CCS  in intel_fb_plane_get_subsampling()
854 	 * first plane. That's incorrect for the CCS AUX plane of the first  in intel_fb_plane_get_subsampling()
1117 	 * here the main and CCS coordinates must match only within a (64 byte  in intel_fb_check_ccs_xy()
1134 	 * CCS doesn't have its own x/y offset register, so the intra CCS tile  in intel_fb_check_ccs_xy()
1135 	 * x/y offsets must match between CCS and the main surface.  in intel_fb_check_ccs_xy()
1139 			      "Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n",  in intel_fb_check_ccs_xy()
1172 	 * The new CCS hash mode isn't compatible with remapping as  in intel_plane_can_remap()
1466 			 * The hardware automagically calculates the CCS AUX surface  in calc_plane_remap_info()
1751 	 * The new CCS hash mode makes remapping impossible  in intel_fb_max_stride()
1788 		 * one 64 byte cacheline on the CCS AUX surface.  in intel_fb_stride_alignment()
2049 					    "ccs aux plane %d pitch (%d) must be %d\n",  in intel_framebuffer_init()