Lines Matching full:dpll

34 	for ((__i) = 0; (__i) < (__i915)->display.dpll.num_shared_dpll && \
35 		     ((__pll) = &(__i915)->display.dpll.shared_dplls[(__i)]) ; (__i)++)
48  * enum intel_dpll_id - possible DPLL ids
50  * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.
54 	 * @DPLL_ID_PRIVATE: non-shared dpll in use
59 	 * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB
63 	 * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB
185 	u32 dpll;  member
198 	 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
201 	 * the DPLL.
284  * struct intel_shared_dpll_state - hold the DPLL atomic state
286  * This structure holds an atomic state for the DPLL, that can represent
295 	 * @pipe_mask: mask of pipes using this DPLL, active or not
300 	 * @hw_state: hardware configuration for the DPLL stored in
311 	 * @name: DPLL name; used for logging
321 	 * @id: unique indentifier for this DPLL
326 	 * @power_domain: extra power domain required by the DPLL
333 	 * Inform the state checker that the DPLL is kept enabled even if
341 	 * Inform the state checker that the DPLL can be used as a fallback
365 	 * @active_mask: mask of active pipes (i.e. DPMS on) using this DPLL
381 	 * need to be grabbed to disable DC states while this DPLL is enabled
391 /* shared dpll functions */