i915/display/intel_dpll_mgr.h

2  * Copyright © 2012-2016 Intel Corporation
34 	for ((__i) = 0; (__i) < (__i915)->display.dpll.num_shared_dpll && \
35 		     ((__pll) = &(__i915)->display.dpll.shared_dplls[(__i)]) ; (__i)++)
48  * enum intel_dpll_id - possible DPLL ids
54 	 * @DPLL_ID_PRIVATE: non-shared dpll in use
56 	DPLL_ID_PRIVATE = -1,
113 	 * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0
117 	 * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1
121 	 * @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4
158 	 * @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0
162 	 * @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1
166 	 * @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2
170 	 * @DPLL_ID_DG1_DPLL3: DG1 combo PHY DPLL3
284  * struct intel_shared_dpll_state - hold the DPLL atomic state
307  * struct dpll_info - display PLL platform specific info
342 	 * (for TC->TBT fallback).
348  * struct intel_shared_dpll - display PLL with tracked state and users
380 	 * @wakeref: In some platforms a device-level runtime pm reference may