36 	} dot, vco, n, m, m1, m2, p, p1;  member
49 	.m2 = { .min = 6, .max = 16 },
62 	.m2 = { .min = 6, .max = 16 },
75 	.m2 = { .min = 6, .max = 16 },
88 	.m2 = { .min = 3, .max = 7 },
101 	.m2 = { .min = 3, .max = 7 },
115 	.m2 = { .min = 5, .max = 11 },
130 	.m2 = { .min = 5, .max = 11 },
143 	.m2 = { .min = 5, .max = 11 },
157 	.m2 = { .min = 5, .max = 11 },
171 	/* Pineview only has one combined m divider, which we treat as m2. */
173 	.m2 = { .min = 0, .max = 254 },
186 	.m2 = { .min = 0, .max = 254 },
195  * We calculate clock using (register_value + 2) for N/M1/M2, so here
204 	.m2 = { .min = 5, .max = 9 },
217 	.m2 = { .min = 5, .max = 9 },
230 	.m2 = { .min = 5, .max = 9 },
244 	.m2 = { .min = 5, .max = 9 },
257 	.m2 = { .min = 5, .max = 9 },
275 	.m2 = { .min = 11, .max = 156 },
291 	.m2 = { .min = 24 << 22, .max = 175 << 22 },
301 	/* FIXME: find real m2 limits */
302 	.m2 = { .min = 2 << 22, .max = 255 << 22 },
318 	clock->m = clock->m2 + 2;  in pnv_calc_dpll_params()
331 	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);  in i9xx_dpll_compute_m()
349 	clock->m = clock->m1 * clock->m2;  in vlv_calc_dpll_params()
362 	clock->m = clock->m1 * clock->m2;  in chv_calc_dpll_params()
440 		clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;  in i9xx_crtc_clock_get()
443 		clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;  in i9xx_crtc_clock_get()
533 	clock.m2 = REG_FIELD_GET(DPIO_M2_DIV_MASK, tmp);  in vlv_crtc_clock_get()
565 	clock.m2 = REG_FIELD_GET(DPIO_CHV_M2_DIV_MASK, pll_dw0) << 22;  in chv_crtc_clock_get()
567 		clock.m2 |= REG_FIELD_GET(DPIO_CHV_M2_FRAC_DIV_MASK, pll_dw2);  in chv_crtc_clock_get()
587 	if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)  in intel_pll_is_valid()
593 		if (clock->m1 <= clock->m2)  in intel_pll_is_valid()
665 		for (clock.m2 = limit->m2.min;  in i9xx_find_best_dpll()
666 		     clock.m2 <= limit->m2.max; clock.m2++) {  in i9xx_find_best_dpll()
667 			if (clock.m2 >= clock.m1)  in i9xx_find_best_dpll()
723 		for (clock.m2 = limit->m2.min;  in pnv_find_best_dpll()
724 		     clock.m2 <= limit->m2.max; clock.m2++) {  in pnv_find_best_dpll()
783 		/* based on hardware requirement, prefere larger m1,m2 */  in g4x_find_best_dpll()
786 			for (clock.m2 = limit->m2.max;  in g4x_find_best_dpll()
787 			     clock.m2 >= limit->m2.min; clock.m2--) {  in g4x_find_best_dpll()
879 				/* based on hardware requirement, prefer bigger m1,m2 values */  in vlv_find_best_dpll()
883 					clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,  in vlv_find_best_dpll()
925 	u64 m2;  in chv_find_best_dpll()  local
947 			m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22,  in chv_find_best_dpll()
950 			if (m2 > INT_MAX/clock.m1)  in chv_find_best_dpll()
953 			clock.m2 = m2;  in chv_find_best_dpll()
986 	return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;  in i9xx_dpll_compute_fp()
991 	return (1 << dpll->n) << 16 | dpll->m2;  in pnv_dpll_compute_fp()
1935 		DPIO_M2_DIV(clock->m2) |  in vlv_prepare_pll()
2042 	m2_frac = clock->m2 & 0x3fffff;  in chv_prepare_pll()
2053 	/* Feedback post-divider - m2 */  in chv_prepare_pll()
2055 		       DPIO_CHV_M2_DIV(clock->m2 >> 22));  in chv_prepare_pll()
2062 	/* M2 fraction division */  in chv_prepare_pll()
2066 	/* M2 fraction division enable */  in chv_prepare_pll()