36 	} dot, vco, n, m, m1, m2, p, p1;  member
48 	.m1 = { .min = 18, .max = 26 },
61 	.m1 = { .min = 18, .max = 26 },
74 	.m1 = { .min = 18, .max = 26 },
87 	.m1 = { .min = 8, .max = 18 },
100 	.m1 = { .min = 8, .max = 18 },
114 	.m1 = { .min = 17, .max = 23 },
129 	.m1 = { .min = 16, .max = 23 },
142 	.m1 = { .min = 17, .max = 23 },
156 	.m1 = { .min = 17, .max = 23 },
172 	.m1 = { .min = 0, .max = 0 },
185 	.m1 = { .min = 0, .max = 0 },
195  * We calculate clock using (register_value + 2) for N/M1/M2, so here
203 	.m1 = { .min = 12, .max = 22 },
216 	.m1 = { .min = 12, .max = 22 },
229 	.m1 = { .min = 12, .max = 22 },
243 	.m1 = { .min = 12, .max = 22 },
256 	.m1 = { .min = 12, .max = 22 },
274 	.m1 = { .min = 2, .max = 3 },
290 	.m1 = { .min = 2, .max = 2 },
300 	.m1 = { .min = 2, .max = 2 },
315 /* m1 is reserved as 0 in Pineview, n is a ring counter */
331 	return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);  in i9xx_dpll_compute_m()
349 	clock->m = clock->m1 * clock->m2;  in vlv_calc_dpll_params()
362 	clock->m = clock->m1 * clock->m2;  in chv_calc_dpll_params()
437 	clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;  in i9xx_crtc_clock_get()
532 	clock.m1 = REG_FIELD_GET(DPIO_M1_DIV_MASK, tmp);  in vlv_crtc_clock_get()
564 	clock.m1 = REG_FIELD_GET(DPIO_CHV_M1_DIV_MASK, pll_dw1) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;  in chv_crtc_clock_get()
589 	if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)  in intel_pll_is_valid()
593 		if (clock->m1 <= clock->m2)  in intel_pll_is_valid()
663 	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;  in i9xx_find_best_dpll()
664 	     clock.m1++) {  in i9xx_find_best_dpll()
667 			if (clock.m2 >= clock.m1)  in i9xx_find_best_dpll()
721 	for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;  in pnv_find_best_dpll()
722 	     clock.m1++) {  in pnv_find_best_dpll()
783 		/* based on hardware requirement, prefere larger m1,m2 */  in g4x_find_best_dpll()
784 		for (clock.m1 = limit->m1.max;  in g4x_find_best_dpll()
785 		     clock.m1 >= limit->m1.min; clock.m1--) {  in g4x_find_best_dpll()
879 				/* based on hardware requirement, prefer bigger m1,m2 values */  in vlv_find_best_dpll()
880 				for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {  in vlv_find_best_dpll()
884 								     refclk * clock.m1);  in vlv_find_best_dpll()
932 	 * Based on hardware doc, the n always set to 1, and m1 always  in chv_find_best_dpll()
937 	clock.m1 = 2;  in chv_find_best_dpll()
948 						   refclk * clock.m1);  in chv_find_best_dpll()
950 			if (m2 > INT_MAX/clock.m1)  in chv_find_best_dpll()
986 	return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;  in i9xx_dpll_compute_fp()
1934 	tmp = DPIO_M1_DIV(clock->m1) |  in vlv_prepare_pll()
2057 	/* Feedback refclk divider - n and m1 */  in chv_prepare_pll()