Lines Matching +full:1 +full:p1
36 } dot, vco, n, m, m1, m2, p, p1; member
51 .p1 = { .min = 2, .max = 33 },
64 .p1 = { .min = 2, .max = 33 },
77 .p1 = { .min = 1, .max = 6 },
85 .n = { .min = 1, .max = 6 },
90 .p1 = { .min = 1, .max = 8 },
98 .n = { .min = 1, .max = 6 },
103 .p1 = { .min = 1, .max = 8 },
112 .n = { .min = 1, .max = 4 },
117 .p1 = { .min = 1, .max = 3},
127 .n = { .min = 1, .max = 4 },
132 .p1 = { .min = 1, .max = 8},
140 .n = { .min = 1, .max = 3 },
145 .p1 = { .min = 2, .max = 8 },
154 .n = { .min = 1, .max = 3 },
159 .p1 = { .min = 2, .max = 6 },
175 .p1 = { .min = 1, .max = 8 },
188 .p1 = { .min = 1, .max = 8 },
201 .n = { .min = 1, .max = 5 },
206 .p1 = { .min = 1, .max = 8 },
214 .n = { .min = 1, .max = 3 },
219 .p1 = { .min = 2, .max = 8 },
227 .n = { .min = 1, .max = 3 },
232 .p1 = { .min = 2, .max = 8 },
241 .n = { .min = 1, .max = 2 },
246 .p1 = { .min = 2, .max = 8 },
254 .n = { .min = 1, .max = 3 },
259 .p1 = { .min = 2, .max = 6 },
273 .n = { .min = 1, .max = 7 },
276 .p1 = { .min = 2, .max = 3 },
289 .n = { .min = 1, .max = 1 },
292 .p1 = { .min = 2, .max = 4 },
293 .p2 = { .p2_slow = 1, .p2_fast = 14 },
299 .n = { .min = 1, .max = 1 },
303 .p1 = { .min = 2, .max = 4 },
304 .p2 = { .p2_slow = 1, .p2_fast = 20 },
319 clock->p = clock->p1 * clock->p2; in pnv_calc_dpll_params()
337 clock->p = clock->p1 * clock->p2; in i9xx_calc_dpll_params()
350 clock->p = clock->p1 * clock->p2 * 5; in vlv_calc_dpll_params()
363 clock->p = clock->p1 * clock->p2 * 5; in chv_calc_dpll_params()
439 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; in i9xx_crtc_clock_get()
448 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> in i9xx_crtc_clock_get()
451 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> in i9xx_crtc_clock_get()
482 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> in i9xx_crtc_clock_get()
491 clock.p1 = 2; in i9xx_crtc_clock_get()
493 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> in i9xx_crtc_clock_get()
535 clock.p1 = REG_FIELD_GET(DPIO_P1_DIV_MASK, tmp); in vlv_crtc_clock_get()
569 clock.p1 = REG_FIELD_GET(DPIO_CHV_P1_DIV_MASK, cmn_dw13); in chv_crtc_clock_get()
585 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) in intel_pll_is_valid()
671 for (clock.p1 = limit->p1.min; in i9xx_find_best_dpll()
672 clock.p1 <= limit->p1.max; clock.p1++) { in i9xx_find_best_dpll()
727 for (clock.p1 = limit->p1.min; in pnv_find_best_dpll()
728 clock.p1 <= limit->p1.max; clock.p1++) { in pnv_find_best_dpll()
788 for (clock.p1 = limit->p1.max; in g4x_find_best_dpll()
789 clock.p1 >= limit->p1.min; clock.p1--) { in g4x_find_best_dpll()
875 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { in vlv_find_best_dpll()
877 clock.p2 -= clock.p2 > 10 ? 2 : 1) { in vlv_find_best_dpll()
878 clock.p = clock.p1 * clock.p2 * 5; in vlv_find_best_dpll()
932 * Based on hardware doc, the n always set to 1, and m1 always in chv_find_best_dpll()
934 * revisit this because n may not 1 anymore. in chv_find_best_dpll()
936 clock.n = 1; in chv_find_best_dpll()
939 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { in chv_find_best_dpll()
942 clock.p2 -= clock.p2 > 10 ? 2 : 1) { in chv_find_best_dpll()
945 clock.p = clock.p1 * clock.p2 * 5; in chv_find_best_dpll()
991 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp()
996 return (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; in i965_dpll_md()
1016 dpll |= (crtc_state->pixel_multiplier - 1) in i9xx_dpll()
1027 /* compute bitmask from p1 value */ in i9xx_dpll()
1029 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_dpll()
1030 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in i9xx_dpll()
1032 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; in i9xx_dpll()
1033 WARN_ON(reduced_clock->p1 != clock->p1); in i9xx_dpll()
1035 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i9xx_dpll()
1036 WARN_ON(reduced_clock->p1 != clock->p1); in i9xx_dpll()
1102 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_dpll()
1104 if (clock->p1 == 2) in i8xx_dpll()
1107 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; in i8xx_dpll()
1111 WARN_ON(reduced_clock->p1 != clock->p1); in i8xx_dpll()
1119 * Enable) must be set to “1” in both the DPLL A Control Register in i8xx_dpll()
1282 dpll |= (crtc_state->pixel_multiplier - 1) in ilk_dpll()
1310 /* compute bitmask from p1 value */ in ilk_dpll()
1311 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; in ilk_dpll()
1313 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; in ilk_dpll()
1844 * the P1/P2 dividers. Otherwise the DPLL will keep using the old in i9xx_enable_pll()
1936 DPIO_P1_DIV(clock->p1) | in vlv_prepare_pll()
1939 DPIO_K_DIV(1); in vlv_prepare_pll()
2002 if (intel_de_wait_for_set(dev_priv, DPLL(dev_priv, pipe), DPLL_LOCK_VLV, 1)) in _vlv_enable_pll()
2046 /* p1 and p2 divider */ in chv_prepare_pll()
2049 DPIO_CHV_P1_DIV(clock->p1) | in chv_prepare_pll()
2051 DPIO_CHV_K_DIV(1)); in chv_prepare_pll()
2060 DPIO_CHV_N_DIV(1)); in chv_prepare_pll()
2143 udelay(1); in _chv_enable_pll()
2149 if (intel_de_wait_for_set(dev_priv, DPLL(dev_priv, pipe), DPLL_LOCK_VLV, 1)) in _chv_enable_pll()
2223 crtc_state->pixel_multiplier = 1; in vlv_force_pll_on()