Lines Matching +full:2 +full:- +full:lane
2 * Copyright © 2014-2016 Intel Corporation
45 * IOSF-SB port.
48 * houses a common lane part which contains the PLL and other common
49 * logic. CH0 common lane also contains the IOSF-SB logic for the
59 * each spline is made up of one Physical Access Coding Sub-Layer
64 * Additionally the PHY also contains an AUX lane with AUX blocks
70 * Generally on VLV/CHV the common lane corresponds to the pipe and
103 * ---------------------------------
106 * |---------------|---------------| Display PHY
108 * |-------|-------|-------|-------|
110 * ---------------------------------
112 * ---------------------------------
115 * -----------------
118 * |---------------| Display PHY
120 * |-------|-------|
122 * -----------------
124 * -----------------
128 * struct bxt_dpio_phy_info - Hold info for a broxton DDI phy
137 * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor.
163 } channel[2];
179 .rcomp_phy = -1,
201 .rcomp_phy = -1,
254 if (port == phy_info->channel[DPIO_CH0].port) { in bxt_port_to_phy_channel()
260 if (phy_info->dual_channel && in bxt_port_to_phy_channel()
261 port == phy_info->channel[DPIO_CH1].port) { in bxt_port_to_phy_channel()
268 drm_WARN(&dev_priv->drm, 1, "PHY not found for PORT %c", in bxt_port_to_phy_channel()
275 * Like intel_de_rmw() but reads from a single per-lane register and
295 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in bxt_dpio_phy_set_signal_levels()
299 int lane, n_entries; in bxt_dpio_phy_set_signal_levels() local
301 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in bxt_dpio_phy_set_signal_levels()
302 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in bxt_dpio_phy_set_signal_levels()
305 bxt_port_to_phy_channel(dev_priv, encoder->port, &phy, &ch); in bxt_dpio_phy_set_signal_levels()
309 * can read only lane registers and we pick lanes 0/1 for that. in bxt_dpio_phy_set_signal_levels()
315 for (lane = 0; lane < crtc_state->lane_count; lane++) { in bxt_dpio_phy_set_signal_levels()
316 int level = intel_ddi_level(encoder, crtc_state, lane); in bxt_dpio_phy_set_signal_levels()
318 intel_de_rmw(dev_priv, BXT_PORT_TX_DW2_LN(phy, ch, lane), in bxt_dpio_phy_set_signal_levels()
320 MARGIN_000(trans->entries[level].bxt.margin) | in bxt_dpio_phy_set_signal_levels()
321 UNIQ_TRANS_SCALE(trans->entries[level].bxt.scale)); in bxt_dpio_phy_set_signal_levels()
324 for (lane = 0; lane < crtc_state->lane_count; lane++) { in bxt_dpio_phy_set_signal_levels()
325 int level = intel_ddi_level(encoder, crtc_state, lane); in bxt_dpio_phy_set_signal_levels()
328 intel_de_rmw(dev_priv, BXT_PORT_TX_DW3_LN(phy, ch, lane), in bxt_dpio_phy_set_signal_levels()
330 trans->entries[level].bxt.enable ? in bxt_dpio_phy_set_signal_levels()
333 val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN(phy, ch, lane)); in bxt_dpio_phy_set_signal_levels()
335 drm_err(&dev_priv->drm, in bxt_dpio_phy_set_signal_levels()
339 for (lane = 0; lane < crtc_state->lane_count; lane++) { in bxt_dpio_phy_set_signal_levels()
340 int level = intel_ddi_level(encoder, crtc_state, lane); in bxt_dpio_phy_set_signal_levels()
342 intel_de_rmw(dev_priv, BXT_PORT_TX_DW4_LN(phy, ch, lane), in bxt_dpio_phy_set_signal_levels()
344 DE_EMPHASIS(trans->entries[level].bxt.deemphasis)); in bxt_dpio_phy_set_signal_levels()
359 if (!(intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask)) in bxt_dpio_phy_is_enabled()
364 drm_dbg(&dev_priv->drm, in bxt_dpio_phy_is_enabled()
371 drm_dbg(&dev_priv->drm, in bxt_dpio_phy_is_enabled()
392 drm_err(&dev_priv->drm, "timeout waiting for PHY%d GRC\n", in bxt_phy_wait_grc_done()
406 if (phy_info->rcomp_phy != -1) in _bxt_dpio_phy_init()
407 dev_priv->display.state.bxt_phy_grc = bxt_get_grc(dev_priv, phy); in _bxt_dpio_phy_init()
410 drm_dbg(&dev_priv->drm, "DDI PHY %d already enabled, " in _bxt_dpio_phy_init()
415 drm_dbg(&dev_priv->drm, in _bxt_dpio_phy_init()
420 intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, 0, phy_info->pwron_mask); in _bxt_dpio_phy_init()
432 drm_err(&dev_priv->drm, "timeout during PHY%d power on\n", in _bxt_dpio_phy_init()
446 if (phy_info->dual_channel) in _bxt_dpio_phy_init()
450 if (phy_info->rcomp_phy != -1) { in _bxt_dpio_phy_init()
453 bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy); in _bxt_dpio_phy_init()
460 val = bxt_get_grc(dev_priv, phy_info->rcomp_phy); in _bxt_dpio_phy_init()
461 dev_priv->display.state.bxt_phy_grc = val; in _bxt_dpio_phy_init()
471 if (phy_info->reset_delay) in _bxt_dpio_phy_init()
472 udelay(phy_info->reset_delay); in _bxt_dpio_phy_init()
485 intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, phy_info->pwron_mask, 0); in bxt_dpio_phy_uninit()
492 enum dpio_phy rcomp_phy = phy_info->rcomp_phy; in bxt_dpio_phy_init()
495 lockdep_assert_held(&dev_priv->display.power.domains.lock); in bxt_dpio_phy_init()
498 if (rcomp_phy != -1) in bxt_dpio_phy_init()
531 drm_dbg(&dev_priv->drm, "DDI PHY %d reg %pV [%08x] state mismatch: " in __phy_reg_verify_state()
572 if (phy_info->dual_channel) in bxt_dpio_phy_verify_state()
577 if (phy_info->rcomp_phy != -1) { in bxt_dpio_phy_verify_state()
578 u32 grc_code = dev_priv->display.state.bxt_phy_grc; in bxt_dpio_phy_verify_state()
603 case 2: in bxt_dpio_phy_calc_lane_lat_optim_mask()
604 return BIT(2) | BIT(0); in bxt_dpio_phy_calc_lane_lat_optim_mask()
606 return BIT(3) | BIT(2) | BIT(0); in bxt_dpio_phy_calc_lane_lat_optim_mask()
617 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in bxt_dpio_phy_set_lane_optim_mask()
618 enum port port = encoder->port; in bxt_dpio_phy_set_lane_optim_mask()
621 int lane; in bxt_dpio_phy_set_lane_optim_mask() local
625 for (lane = 0; lane < 4; lane++) { in bxt_dpio_phy_set_lane_optim_mask()
630 intel_de_rmw(dev_priv, BXT_PORT_TX_DW14_LN(phy, ch, lane), in bxt_dpio_phy_set_lane_optim_mask()
632 lane_lat_optim_mask & BIT(lane) ? LATENCY_OPTIM : 0); in bxt_dpio_phy_set_lane_optim_mask()
639 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in bxt_dpio_phy_get_lane_lat_optim_mask()
640 enum port port = encoder->port; in bxt_dpio_phy_get_lane_lat_optim_mask()
643 int lane; in bxt_dpio_phy_get_lane_lat_optim_mask() local
649 for (lane = 0; lane < 4; lane++) { in bxt_dpio_phy_get_lane_lat_optim_mask()
651 BXT_PORT_TX_DW14_LN(phy, ch, lane)); in bxt_dpio_phy_get_lane_lat_optim_mask()
654 mask |= BIT(lane); in bxt_dpio_phy_get_lane_lat_optim_mask()
662 switch (dig_port->base.port) { in vlv_dig_port_to_channel()
664 MISSING_CASE(dig_port->base.port); in vlv_dig_port_to_channel()
676 switch (dig_port->base.port) { in vlv_dig_port_to_phy()
678 MISSING_CASE(dig_port->base.port); in vlv_dig_port_to_phy()
721 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_set_phy_signal_level()
737 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
750 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
758 for (i = 0; i < crtc_state->lane_count; i++) { in chv_set_phy_signal_level()
766 for (i = 0; i < crtc_state->lane_count; i++) { in chv_set_phy_signal_level()
789 for (i = 0; i < crtc_state->lane_count; i++) { in chv_set_phy_signal_level()
803 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
816 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_data_lane_soft_reset()
829 if (crtc_state->lane_count > 2) { in chv_data_lane_soft_reset()
846 if (crtc_state->lane_count > 2) { in chv_data_lane_soft_reset()
861 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_phy_pre_pll_enable()
862 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in chv_phy_pre_pll_enable()
865 enum pipe pipe = crtc->pipe; in chv_phy_pre_pll_enable()
867 intel_dp_unused_lane_mask(crtc_state->lane_count); in chv_phy_pre_pll_enable()
871 * Must trick the second common lane into life. in chv_phy_pre_pll_enable()
875 dig_port->release_cl2_override = in chv_phy_pre_pll_enable()
882 /* Assert data lane reset */ in chv_phy_pre_pll_enable()
913 if (crtc_state->lane_count > 2) { in chv_phy_pre_pll_enable()
943 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_phy_pre_encoder_enable()
956 if (crtc_state->lane_count > 2) { in chv_phy_pre_encoder_enable()
962 /* Program Tx lane latency optimal setting*/ in chv_phy_pre_encoder_enable()
963 for (i = 0; i < crtc_state->lane_count; i++) { in chv_phy_pre_encoder_enable()
965 if (crtc_state->lane_count == 1) in chv_phy_pre_encoder_enable()
972 /* Data lane stagger programming */ in chv_phy_pre_encoder_enable()
973 if (crtc_state->port_clock > 270000) in chv_phy_pre_encoder_enable()
975 else if (crtc_state->port_clock > 135000) in chv_phy_pre_encoder_enable()
977 else if (crtc_state->port_clock > 67500) in chv_phy_pre_encoder_enable()
979 else if (crtc_state->port_clock > 33750) in chv_phy_pre_encoder_enable()
988 if (crtc_state->lane_count > 2) { in chv_phy_pre_encoder_enable()
1001 if (crtc_state->lane_count > 2) { in chv_phy_pre_encoder_enable()
1010 /* Deassert data lane reset */ in chv_phy_pre_encoder_enable()
1019 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_phy_release_cl2_override()
1021 if (dig_port->release_cl2_override) { in chv_phy_release_cl2_override()
1023 dig_port->release_cl2_override = false; in chv_phy_release_cl2_override()
1030 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_phy_post_pll_disable()
1032 enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe; in chv_phy_post_pll_disable()
1052 * lane so that chv_powergate_phy_ch() will power in chv_phy_post_pll_disable()
1067 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_set_phy_signal_level()
1094 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_phy_pre_pll_enable()
1098 /* Program Tx lane resets to default */ in vlv_phy_pre_pll_enable()
1110 /* Fix up inter-pair skew failure */ in vlv_phy_pre_pll_enable()
1123 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_phy_pre_encoder_enable()
1124 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in vlv_phy_pre_encoder_enable()
1127 enum pipe pipe = crtc->pipe; in vlv_phy_pre_encoder_enable()
1139 /* Program lane clock */ in vlv_phy_pre_encoder_enable()
1150 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_phy_reset_lanes()