58 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);  in intel_dp_mst_max_dpt_bpp()
60 		&crtc_state->hw.adjusted_mode;  in intel_dp_mst_max_dpt_bpp()
66 	 * DSC->DPT interface width:  in intel_dp_mst_max_dpt_bpp()
67 	 *   ICL-MTL: 72 bits (each branch has 72 bits, only left branch is used)  in intel_dp_mst_max_dpt_bpp()
74 	 * testing on MTL-P the  in intel_dp_mst_max_dpt_bpp()
75 	 * - DELL U3224KBA display  in intel_dp_mst_max_dpt_bpp()
76 	 * - Unigraf UCD-500 CTS test sink  in intel_dp_mst_max_dpt_bpp()
78 	 * - 5120x2880/995.59Mhz  in intel_dp_mst_max_dpt_bpp()
79 	 * - 6016x3384/1357.23Mhz  in intel_dp_mst_max_dpt_bpp()
80 	 * - 6144x3456/1413.39Mhz  in intel_dp_mst_max_dpt_bpp()
85 	return div64_u64(mul_u32_u32(intel_dp_link_symbol_clock(crtc_state->port_clock) * 72,  in intel_dp_mst_max_dpt_bpp()
87 			 mul_u32_u32(adjusted_mode->crtc_clock, 1030000));  in intel_dp_mst_max_dpt_bpp()
92 				    bool ssc, int dsc_slice_count, int bpp_x16)  in intel_dp_mst_bw_overhead()  argument
95 		&crtc_state->hw.adjusted_mode;  in intel_dp_mst_bw_overhead()
100 	flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0;  in intel_dp_mst_bw_overhead()
101 	flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;  in intel_dp_mst_bw_overhead()
106 	overhead = drm_dp_bw_overhead(crtc_state->lane_count,  in intel_dp_mst_bw_overhead()
107 				      adjusted_mode->hdisplay,  in intel_dp_mst_bw_overhead()
116 	return max(overhead, intel_dp_bw_fec_overhead(crtc_state->fec_enable));  in intel_dp_mst_bw_overhead()
126 		&crtc_state->hw.adjusted_mode;  in intel_dp_mst_compute_m_n()
129 	intel_link_compute_m_n(bpp_x16, crtc_state->lane_count,  in intel_dp_mst_compute_m_n()
130 			       adjusted_mode->crtc_clock,  in intel_dp_mst_compute_m_n()
131 			       crtc_state->port_clock,  in intel_dp_mst_compute_m_n()
135 	m_n->tu = DIV_ROUND_UP_ULL(mul_u32_u32(m_n->data_m, 64), m_n->data_n);  in intel_dp_mst_compute_m_n()
154 		&crtc_state->hw.adjusted_mode;  in intel_dp_mst_dsc_get_slice_count()
155 	int num_joined_pipes = crtc_state->joiner_pipes;  in intel_dp_mst_dsc_get_slice_count()
158 					    adjusted_mode->clock,  in intel_dp_mst_dsc_get_slice_count()
159 					    adjusted_mode->hdisplay,  in intel_dp_mst_dsc_get_slice_count()
172 	struct drm_atomic_state *state = crtc_state->uapi.state;  in intel_dp_mst_find_vcpi_slots_for_bpp()
174 	struct intel_dp *intel_dp = &intel_mst->primary->dp;  in intel_dp_mst_find_vcpi_slots_for_bpp()
177 		to_intel_connector(conn_state->connector);  in intel_dp_mst_find_vcpi_slots_for_bpp()
178 	struct drm_i915_private *i915 = to_i915(connector->base.dev);  in intel_dp_mst_find_vcpi_slots_for_bpp()
180 		&crtc_state->hw.adjusted_mode;  in intel_dp_mst_find_vcpi_slots_for_bpp()
181 	int bpp, slots = -EINVAL;  in intel_dp_mst_find_vcpi_slots_for_bpp()
186 	mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst_mgr);  in intel_dp_mst_find_vcpi_slots_for_bpp()
190 	crtc_state->lane_count = limits->max_lane_count;  in intel_dp_mst_find_vcpi_slots_for_bpp()
191 	crtc_state->port_clock = limits->max_rate;  in intel_dp_mst_find_vcpi_slots_for_bpp()
195 			return -EINVAL;  in intel_dp_mst_find_vcpi_slots_for_bpp()
197 		crtc_state->fec_enable = !intel_dp_is_uhbr(crtc_state);  in intel_dp_mst_find_vcpi_slots_for_bpp()
200 	mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr,  in intel_dp_mst_find_vcpi_slots_for_bpp()
201 						      crtc_state->port_clock,  in intel_dp_mst_find_vcpi_slots_for_bpp()
202 						      crtc_state->lane_count);  in intel_dp_mst_find_vcpi_slots_for_bpp()
206 		drm_dbg_kms(&i915->drm, "Limiting bpp to max DPT bpp (%d -> %d)\n",  in intel_dp_mst_find_vcpi_slots_for_bpp()
211 	drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp %d max bpp %d\n",  in intel_dp_mst_find_vcpi_slots_for_bpp()
217 			drm_dbg_kms(&i915->drm, "Can't get valid DSC slice count\n");  in intel_dp_mst_find_vcpi_slots_for_bpp()
219 			return -ENOSPC;  in intel_dp_mst_find_vcpi_slots_for_bpp()
223 	for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {  in intel_dp_mst_find_vcpi_slots_for_bpp()
230 		drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);  in intel_dp_mst_find_vcpi_slots_for_bpp()
233 					       intel_dp_output_bpp(crtc_state->output_format, bpp));  in intel_dp_mst_find_vcpi_slots_for_bpp()
243 					 &crtc_state->dp_m_n);  in intel_dp_mst_find_vcpi_slots_for_bpp()
252 		 * the ALLOCATE_PAYLOAD side-band message matches the payload  in intel_dp_mst_find_vcpi_slots_for_bpp()
256 		 * crtc_state->dp_m_n.tu), provided that the driver doesn't  in intel_dp_mst_find_vcpi_slots_for_bpp()
257 		 * enable SSC on the corresponding link.  in intel_dp_mst_find_vcpi_slots_for_bpp()
259 		pbn.full = dfixed_const(intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock,  in intel_dp_mst_find_vcpi_slots_for_bpp()
262 		remote_tu = DIV_ROUND_UP(pbn.full, mst_state->pbn_div.full);  in intel_dp_mst_find_vcpi_slots_for_bpp()
271 		remote_tu = ALIGN(remote_tu, 4 / crtc_state->lane_count);  in intel_dp_mst_find_vcpi_slots_for_bpp()
280 		pbn.full = remote_tu * mst_state->pbn_div.full;  in intel_dp_mst_find_vcpi_slots_for_bpp()
281 		crtc_state->pbn = dfixed_trunc(pbn);  in intel_dp_mst_find_vcpi_slots_for_bpp()
283 		drm_WARN_ON(&i915->drm, remote_tu < crtc_state->dp_m_n.tu);  in intel_dp_mst_find_vcpi_slots_for_bpp()
284 		crtc_state->dp_m_n.tu = remote_tu;  in intel_dp_mst_find_vcpi_slots_for_bpp()
286 		slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,  in intel_dp_mst_find_vcpi_slots_for_bpp()
287 						      connector->port,  in intel_dp_mst_find_vcpi_slots_for_bpp()
288 						      crtc_state->pbn);  in intel_dp_mst_find_vcpi_slots_for_bpp()
289 		if (slots == -EDEADLK)  in intel_dp_mst_find_vcpi_slots_for_bpp()
293 			drm_WARN_ON(&i915->drm, slots != crtc_state->dp_m_n.tu);  in intel_dp_mst_find_vcpi_slots_for_bpp()
304 		drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n",  in intel_dp_mst_find_vcpi_slots_for_bpp()
308 			crtc_state->pipe_bpp = bpp;  in intel_dp_mst_find_vcpi_slots_for_bpp()
310 			crtc_state->dsc.compressed_bpp_x16 = fxp_q4_from_int(bpp);  in intel_dp_mst_find_vcpi_slots_for_bpp()
311 		drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc %d\n", slots, bpp, dsc);  in intel_dp_mst_find_vcpi_slots_for_bpp()
322 	int slots = -EINVAL;  in intel_dp_mst_compute_link_config()
329 						     fxp_q4_to_int(limits->link.max_bpp_x16),  in intel_dp_mst_compute_link_config()
330 						     fxp_q4_to_int(limits->link.min_bpp_x16),  in intel_dp_mst_compute_link_config()
346 		to_intel_connector(conn_state->connector);  in intel_dp_dsc_mst_compute_link_config()
347 	struct drm_i915_private *i915 = to_i915(connector->base.dev);  in intel_dp_dsc_mst_compute_link_config()
348 	int slots = -EINVAL;  in intel_dp_dsc_mst_compute_link_config()
357 		dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);  in intel_dp_dsc_mst_compute_link_config()
359 		dsc_max_bpc = min_t(u8, 10, conn_state->max_requested_bpc);  in intel_dp_dsc_mst_compute_link_config()
361 	max_bpp = min_t(u8, dsc_max_bpc * 3, limits->pipe.max_bpp);  in intel_dp_dsc_mst_compute_link_config()
362 	min_bpp = limits->pipe.min_bpp;  in intel_dp_dsc_mst_compute_link_config()
364 	num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,  in intel_dp_dsc_mst_compute_link_config()
367 	drm_dbg_kms(&i915->drm, "DSC Source supported min bpp %d max bpp %d\n",  in intel_dp_dsc_mst_compute_link_config()
380 	drm_dbg_kms(&i915->drm, "DSC Sink supported min bpp %d max bpp %d\n",  in intel_dp_dsc_mst_compute_link_config()
389 	crtc_state->pipe_bpp = max_bpp;  in intel_dp_dsc_mst_compute_link_config()
395 				 fxp_q4_to_int(limits->link.max_bpp_x16));  in intel_dp_dsc_mst_compute_link_config()
399 				 fxp_q4_to_int_roundup(limits->link.min_bpp_x16));  in intel_dp_dsc_mst_compute_link_config()
401 	drm_dbg_kms(&i915->drm, "DSC Sink supported compressed min bpp %d compressed max bpp %d\n",  in intel_dp_dsc_mst_compute_link_config()
406 							    crtc_state->pipe_bpp);  in intel_dp_dsc_mst_compute_link_config()
408 							    crtc_state->pipe_bpp);  in intel_dp_dsc_mst_compute_link_config()
423 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_dp_mst_update_slots()
425 	struct intel_dp *intel_dp = &intel_mst->primary->dp;  in intel_dp_mst_update_slots()
426 	struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;  in intel_dp_mst_update_slots()
431 	topology_state = drm_atomic_get_mst_topology_state(conn_state->state, mgr);  in intel_dp_mst_update_slots()
433 		drm_dbg_kms(&i915->drm, "slot update failed\n");  in intel_dp_mst_update_slots()
444 	return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(mode->htotal - mode->hdisplay,  in mode_hblank_period_ns()
446 				     mode->crtc_clock);  in mode_hblank_period_ns()
455 		&crtc_state->hw.adjusted_mode;  in hblank_expansion_quirk_needs_dsc()
456 	bool is_uhbr_sink = connector->mst_port &&  in hblank_expansion_quirk_needs_dsc()
457 			    drm_dp_128b132b_supported(connector->mst_port->dpcd);  in hblank_expansion_quirk_needs_dsc()
460 	if (!connector->dp.dsc_hblank_expansion_quirk)  in hblank_expansion_quirk_needs_dsc()
463 	if (is_uhbr_sink && !drm_dp_is_uhbr_rate(limits->max_rate))  in hblank_expansion_quirk_needs_dsc()
481 	struct drm_i915_private *i915 = to_i915(connector->base.dev);  in adjust_limits_for_dsc_hblank_expansion_quirk()
482 	const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in adjust_limits_for_dsc_hblank_expansion_quirk()
483 	int min_bpp_x16 = limits->link.min_bpp_x16;  in adjust_limits_for_dsc_hblank_expansion_quirk()
490 			drm_dbg_kms(&i915->drm,  in adjust_limits_for_dsc_hblank_expansion_quirk()
492 				    crtc->base.base.id, crtc->base.name,  in adjust_limits_for_dsc_hblank_expansion_quirk()
493 				    connector->base.base.id, connector->base.name);  in adjust_limits_for_dsc_hblank_expansion_quirk()
497 		drm_dbg_kms(&i915->drm,  in adjust_limits_for_dsc_hblank_expansion_quirk()
499 			    crtc->base.base.id, crtc->base.name,  in adjust_limits_for_dsc_hblank_expansion_quirk()
500 			    connector->base.base.id, connector->base.name);  in adjust_limits_for_dsc_hblank_expansion_quirk()
502 		if (limits->link.max_bpp_x16 < fxp_q4_from_int(24))  in adjust_limits_for_dsc_hblank_expansion_quirk()
505 		limits->link.min_bpp_x16 = fxp_q4_from_int(24);  in adjust_limits_for_dsc_hblank_expansion_quirk()
510 	drm_WARN_ON(&i915->drm, limits->min_rate != limits->max_rate);  in adjust_limits_for_dsc_hblank_expansion_quirk()
512 	if (limits->max_rate < 540000)  in adjust_limits_for_dsc_hblank_expansion_quirk()
514 	else if (limits->max_rate < 810000)  in adjust_limits_for_dsc_hblank_expansion_quirk()
517 	if (limits->link.min_bpp_x16 >= min_bpp_x16)  in adjust_limits_for_dsc_hblank_expansion_quirk()
520 	drm_dbg_kms(&i915->drm,  in adjust_limits_for_dsc_hblank_expansion_quirk()
522 		    crtc->base.base.id, crtc->base.name,  in adjust_limits_for_dsc_hblank_expansion_quirk()
523 		    connector->base.base.id, connector->base.name,  in adjust_limits_for_dsc_hblank_expansion_quirk()
526 	if (limits->link.max_bpp_x16 < min_bpp_x16)  in adjust_limits_for_dsc_hblank_expansion_quirk()
529 	limits->link.min_bpp_x16 = min_bpp_x16;  in adjust_limits_for_dsc_hblank_expansion_quirk()
542 	 * for MST we always configure max link bw - the spec doesn't  in intel_dp_mst_compute_config_limits()
545 	limits->min_rate = limits->max_rate =  in intel_dp_mst_compute_config_limits()
548 	limits->min_lane_count = limits->max_lane_count =  in intel_dp_mst_compute_config_limits()
551 	limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);  in intel_dp_mst_compute_config_limits()
560 	limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24);  in intel_dp_mst_compute_config_limits()
580 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_dp_mst_compute_config()
581 	struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);  in intel_dp_mst_compute_config()
582 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);  in intel_dp_mst_compute_config()
584 	struct intel_dp *intel_dp = &intel_mst->primary->dp;  in intel_dp_mst_compute_config()
586 		to_intel_connector(conn_state->connector);  in intel_dp_mst_compute_config()
588 		&pipe_config->hw.adjusted_mode;  in intel_dp_mst_compute_config()
593 	if (pipe_config->fec_enable &&  in intel_dp_mst_compute_config()
595 		return -EINVAL;  in intel_dp_mst_compute_config()
597 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)  in intel_dp_mst_compute_config()
598 		return -EINVAL;  in intel_dp_mst_compute_config()
601 				 adjusted_mode->crtc_hdisplay,  in intel_dp_mst_compute_config()
602 				 adjusted_mode->crtc_clock))  in intel_dp_mst_compute_config()
603 		pipe_config->joiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);  in intel_dp_mst_compute_config()
605 	pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;  in intel_dp_mst_compute_config()
606 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;  in intel_dp_mst_compute_config()
607 	pipe_config->has_pch_encoder = false;  in intel_dp_mst_compute_config()
609 	joiner_needs_dsc = intel_dp_joiner_needs_dsc(dev_priv, pipe_config->joiner_pipes);  in intel_dp_mst_compute_config()
611 	dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||  in intel_dp_mst_compute_config()
622 		if (ret == -EDEADLK)  in intel_dp_mst_compute_config()
631 		drm_dbg_kms(&dev_priv->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",  in intel_dp_mst_compute_config()
633 			    str_yes_no(intel_dp->force_dsc_en));  in intel_dp_mst_compute_config()
636 			return -EINVAL;  in intel_dp_mst_compute_config()
643 			return -EINVAL;  in intel_dp_mst_compute_config()
649 		drm_WARN(&dev_priv->drm, intel_dp->force_dsc_bpc, "Cannot Force BPC for MST\n");  in intel_dp_mst_compute_config()
654 		drm_dbg_kms(&dev_priv->drm, "Trying to find VCPI slots in DSC mode\n");  in intel_dp_mst_compute_config()
663 						  pipe_config->dp_m_n.tu, false);  in intel_dp_mst_compute_config()
673 	pipe_config->limited_color_range =  in intel_dp_mst_compute_config()
677 		pipe_config->lane_lat_optim_mask =  in intel_dp_mst_compute_config()
678 			bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);  in intel_dp_mst_compute_config()
698 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_dp_mst_transcoder_mask()
711 		if (connector->mst_port != mst_port || !conn_state->base.crtc)  in intel_dp_mst_transcoder_mask()
714 		crtc = to_intel_crtc(conn_state->base.crtc);  in intel_dp_mst_transcoder_mask()
717 		if (!crtc_state->hw.active)  in intel_dp_mst_transcoder_mask()
720 		transcoders |= BIT(crtc_state->cpu_transcoder);  in intel_dp_mst_transcoder_mask()
736 		if (!conn_state->base.crtc)  in get_pipes_downstream_of_mst_port()
739 		if (&connector->mst_port->mst_mgr != mst_mgr)  in get_pipes_downstream_of_mst_port()
742 		if (connector->port != parent_port &&  in get_pipes_downstream_of_mst_port()
744 							  connector->port,  in get_pipes_downstream_of_mst_port()
748 		mask |= BIT(to_intel_crtc(conn_state->base.crtc)->pipe);  in get_pipes_downstream_of_mst_port()
758 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_dp_mst_check_fec_change()
766 	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, mst_pipe_mask) {  in intel_dp_mst_check_fec_change()
771 		if (drm_WARN_ON(&i915->drm, !crtc_state))  in intel_dp_mst_check_fec_change()
772 			return -EINVAL;  in intel_dp_mst_check_fec_change()
774 		if (crtc_state->fec_enable)  in intel_dp_mst_check_fec_change()
775 			fec_pipe_mask |= BIT(crtc->pipe);  in intel_dp_mst_check_fec_change()
781 	limits->force_fec_pipes |= mst_pipe_mask;  in intel_dp_mst_check_fec_change()
786 	return ret ? : -EAGAIN;  in intel_dp_mst_check_fec_change()
798 	ret = drm_dp_mst_atomic_check_mgr(&state->base, mst_mgr, mst_state, &mst_port);  in intel_dp_mst_check_bw()
799 	if (ret != -ENOSPC)  in intel_dp_mst_check_bw()
807 	return ret ? : -EAGAIN;  in intel_dp_mst_check_bw()
811  * intel_dp_mst_atomic_check_link - check all modeset MST link configuration
821  *   - 0 if the confugration is valid
822  *   - %-EAGAIN, if the configuration is invalid and @limits got updated
825  *   - Other negative error, if the configuration is invalid without a
836 	for_each_new_mst_mgr_in_state(&state->base, mgr, mst_state, i) {  in intel_dp_mst_atomic_check_link()
854 	struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);  in intel_dp_mst_compute_config_late()
856 	struct intel_dp *intel_dp = &intel_mst->primary->dp;  in intel_dp_mst_compute_config_late()
859 	crtc_state->mst_master_transcoder =  in intel_dp_mst_compute_config_late()
860 		ffs(intel_dp_mst_transcoder_mask(state, intel_dp)) - 1;  in intel_dp_mst_compute_config_late()
882 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_dp_mst_atomic_topology_check()
887 	if (!intel_connector_needs_modeset(state, &connector->base))  in intel_dp_mst_atomic_topology_check()
890 	drm_connector_list_iter_begin(&dev_priv->drm, &connector_list_iter);  in intel_dp_mst_atomic_topology_check()
896 		if (connector_iter->mst_port != connector->mst_port ||  in intel_dp_mst_atomic_topology_check()
907 		if (!conn_iter_state->base.crtc)  in intel_dp_mst_atomic_topology_check()
910 		crtc = to_intel_crtc(conn_iter_state->base.crtc);  in intel_dp_mst_atomic_topology_check()
911 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in intel_dp_mst_atomic_topology_check()
917 		ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);  in intel_dp_mst_atomic_topology_check()
920 		crtc_state->uapi.mode_changed = true;  in intel_dp_mst_atomic_topology_check()
936 	ret = intel_digital_connector_atomic_check(connector, &state->base);  in intel_dp_mst_atomic_check()
946 							 intel_connector->mst_port,  in intel_dp_mst_atomic_check()
952 	return drm_dp_atomic_release_time_slots(&state->base,  in intel_dp_mst_atomic_check()
953 						&intel_connector->mst_port->mst_mgr,  in intel_dp_mst_atomic_check()
954 						intel_connector->port);  in intel_dp_mst_atomic_check()
960 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in clear_act_sent()
969 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in wait_for_act_sent()
971 	struct intel_dp *intel_dp = &intel_mst->primary->dp;  in wait_for_act_sent()
975 		drm_err(&i915->drm, "Timed out waiting for ACT sent\n");  in wait_for_act_sent()
977 	drm_dp_check_act_status(&intel_dp->mst_mgr);  in wait_for_act_sent()
986 	struct intel_digital_port *dig_port = intel_mst->primary;  in intel_mst_disable_dp()
987 	struct intel_dp *intel_dp = &dig_port->dp;  in intel_mst_disable_dp()
989 		to_intel_connector(old_conn_state->connector);  in intel_mst_disable_dp()
990 	struct drm_i915_private *i915 = to_i915(connector->base.dev);  in intel_mst_disable_dp()
992 	drm_dbg_kms(&i915->drm, "active links %d\n",  in intel_mst_disable_dp()
993 		    intel_dp->active_mst_links);  in intel_mst_disable_dp()
995 	if (intel_dp->active_mst_links == 1)  in intel_mst_disable_dp()
996 		intel_dp->link_trained = false;  in intel_mst_disable_dp()
998 	intel_hdcp_disable(intel_mst->connector);  in intel_mst_disable_dp()
1009 	struct intel_digital_port *dig_port = intel_mst->primary;  in intel_mst_post_disable_dp()
1010 	struct intel_dp *intel_dp = &dig_port->dp;  in intel_mst_post_disable_dp()
1012 		to_intel_connector(old_conn_state->connector);  in intel_mst_post_disable_dp()
1014 		drm_atomic_get_old_mst_topology_state(&state->base, &intel_dp->mst_mgr);  in intel_mst_post_disable_dp()
1016 		drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);  in intel_mst_post_disable_dp()
1018 		drm_atomic_get_mst_payload_state(old_mst_state, connector->port);  in intel_mst_post_disable_dp()
1020 		drm_atomic_get_mst_payload_state(new_mst_state, connector->port);  in intel_mst_post_disable_dp()
1021 	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);  in intel_mst_post_disable_dp()
1025 	intel_dp->active_mst_links--;  in intel_mst_post_disable_dp()
1026 	last_mst_stream = intel_dp->active_mst_links == 0;  in intel_mst_post_disable_dp()
1027 	drm_WARN_ON(&dev_priv->drm,  in intel_mst_post_disable_dp()
1031 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc,  in intel_mst_post_disable_dp()
1041 	drm_dp_remove_payload_part1(&intel_dp->mst_mgr, new_mst_state, new_payload);  in intel_mst_post_disable_dp()
1046 		     TRANS_DDI_FUNC_CTL(dev_priv, old_crtc_state->cpu_transcoder),  in intel_mst_post_disable_dp()
1051 	drm_dp_remove_payload_part2(&intel_dp->mst_mgr, new_mst_state,  in intel_mst_post_disable_dp()
1056 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc,  in intel_mst_post_disable_dp()
1073 	drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port,  in intel_mst_post_disable_dp()
1080 	intel_dp_set_infoframes(&dig_port->base, false,  in intel_mst_post_disable_dp()
1083 	 * From TGL spec: "If multi-stream slave transcoder: Configure  in intel_mst_post_disable_dp()
1093 	intel_mst->connector = NULL;  in intel_mst_post_disable_dp()
1095 		dig_port->base.post_disable(state, &dig_port->base,  in intel_mst_post_disable_dp()
1098 	drm_dbg_kms(&dev_priv->drm, "active links %d\n",  in intel_mst_post_disable_dp()
1099 		    intel_dp->active_mst_links);  in intel_mst_post_disable_dp()
1108 	struct intel_digital_port *dig_port = intel_mst->primary;  in intel_mst_post_pll_disable_dp()
1109 	struct intel_dp *intel_dp = &dig_port->dp;  in intel_mst_post_pll_disable_dp()
1111 	if (intel_dp->active_mst_links == 0 &&  in intel_mst_post_pll_disable_dp()
1112 	    dig_port->base.post_pll_disable)  in intel_mst_post_pll_disable_dp()
1113 		dig_port->base.post_pll_disable(state, encoder, old_crtc_state, old_conn_state);  in intel_mst_post_pll_disable_dp()
1122 	struct intel_digital_port *dig_port = intel_mst->primary;  in intel_mst_pre_pll_enable_dp()
1123 	struct intel_dp *intel_dp = &dig_port->dp;  in intel_mst_pre_pll_enable_dp()
1125 	if (intel_dp->active_mst_links == 0)  in intel_mst_pre_pll_enable_dp()
1126 		dig_port->base.pre_pll_enable(state, &dig_port->base,  in intel_mst_pre_pll_enable_dp()
1133 		intel_ddi_update_active_dpll(state, &dig_port->base,  in intel_mst_pre_pll_enable_dp()
1134 					     to_intel_crtc(pipe_config->uapi.crtc));  in intel_mst_pre_pll_enable_dp()
1140 	return intel_dp->link.mst_probed_rate == link_rate &&  in intel_mst_probed_link_params_valid()
1141 		intel_dp->link.mst_probed_lane_count == lane_count;  in intel_mst_probed_link_params_valid()
1147 	intel_dp->link.mst_probed_rate = link_rate;  in intel_mst_set_probed_link_params()
1148 	intel_dp->link.mst_probed_lane_count = lane_count;  in intel_mst_set_probed_link_params()
1155 					       crtc_state->port_clock, crtc_state->lane_count))  in intel_mst_reprobe_topology()
1158 	drm_dp_mst_topology_queue_probe(&intel_dp->mst_mgr);  in intel_mst_reprobe_topology()
1161 					 crtc_state->port_clock, crtc_state->lane_count);  in intel_mst_reprobe_topology()
1170 	struct intel_digital_port *dig_port = intel_mst->primary;  in intel_mst_pre_enable_dp()
1171 	struct intel_dp *intel_dp = &dig_port->dp;  in intel_mst_pre_enable_dp()
1172 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_mst_pre_enable_dp()
1174 		to_intel_connector(conn_state->connector);  in intel_mst_pre_enable_dp()
1176 		drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);  in intel_mst_pre_enable_dp()
1183 	connector->encoder = encoder;  in intel_mst_pre_enable_dp()
1184 	intel_mst->connector = connector;  in intel_mst_pre_enable_dp()
1185 	first_mst_stream = intel_dp->active_mst_links == 0;  in intel_mst_pre_enable_dp()
1186 	drm_WARN_ON(&dev_priv->drm,  in intel_mst_pre_enable_dp()
1190 	drm_dbg_kms(&dev_priv->drm, "active links %d\n",  in intel_mst_pre_enable_dp()
1191 		    intel_dp->active_mst_links);  in intel_mst_pre_enable_dp()
1196 	drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);  in intel_mst_pre_enable_dp()
1201 		dig_port->base.pre_enable(state, &dig_port->base,  in intel_mst_pre_enable_dp()
1207 	intel_dp->active_mst_links++;  in intel_mst_pre_enable_dp()
1209 	ret = drm_dp_add_payload_part1(&intel_dp->mst_mgr, mst_state,  in intel_mst_pre_enable_dp()
1210 				       drm_atomic_get_mst_payload_state(mst_state, connector->port));  in intel_mst_pre_enable_dp()
1212 		intel_dp_queue_modeset_retry_for_link(state, &dig_port->base, pipe_config);  in intel_mst_pre_enable_dp()
1216 	 * dig_port->base.pre_enable() and should be done here. For  in intel_mst_pre_enable_dp()
1224 	intel_dsc_dp_pps_write(&dig_port->base, pipe_config);  in intel_mst_pre_enable_dp()
1230 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);  in enable_bs_jitter_was()
1241 	if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state))  in enable_bs_jitter_was()
1242 		set |= DP_MST_FEC_BS_JITTER_WA(crtc_state->cpu_transcoder);  in enable_bs_jitter_was()
1247 			set |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder);  in enable_bs_jitter_was()
1248 		else if (crtc_state->fec_enable)  in enable_bs_jitter_was()
1249 			clear |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder);  in enable_bs_jitter_was()
1251 		if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state))  in enable_bs_jitter_was()
1252 			set |= DP_MST_DPT_DPTP_ALIGN_WA(crtc_state->cpu_transcoder);  in enable_bs_jitter_was()
1267 	struct intel_digital_port *dig_port = intel_mst->primary;  in intel_mst_enable_dp()
1268 	struct intel_dp *intel_dp = &dig_port->dp;  in intel_mst_enable_dp()
1269 	struct intel_connector *connector = to_intel_connector(conn_state->connector);  in intel_mst_enable_dp()
1270 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_mst_enable_dp()
1272 		drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);  in intel_mst_enable_dp()
1273 	enum transcoder trans = pipe_config->cpu_transcoder;  in intel_mst_enable_dp()
1274 	bool first_mst_stream = intel_dp->active_mst_links == 1;  in intel_mst_enable_dp()
1278 	drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);  in intel_mst_enable_dp()
1282 			&pipe_config->hw.adjusted_mode;  in intel_mst_enable_dp()
1283 		u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);  in intel_mst_enable_dp()
1285 		intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder),  in intel_mst_enable_dp()
1287 		intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder),  in intel_mst_enable_dp()
1300 	drm_dbg_kms(&dev_priv->drm, "active links %d\n",  in intel_mst_enable_dp()
1301 		    intel_dp->active_mst_links);  in intel_mst_enable_dp()
1308 	ret = drm_dp_add_payload_part2(&intel_dp->mst_mgr,  in intel_mst_enable_dp()
1310 									connector->port));  in intel_mst_enable_dp()
1312 		intel_dp_queue_modeset_retry_for_link(state, &dig_port->base, pipe_config);  in intel_mst_enable_dp()
1317 			     pipe_config->fec_enable ? FECSTALL_DIS_DPTSTREAM_DPTTG : 0);  in intel_mst_enable_dp()
1323 	for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,  in intel_mst_enable_dp()
1338 	*pipe = intel_mst->pipe;  in intel_dp_mst_enc_get_hw_state()
1339 	if (intel_mst->connector)  in intel_dp_mst_enc_get_hw_state()
1348 	struct intel_digital_port *dig_port = intel_mst->primary;  in intel_dp_mst_enc_get_config()
1350 	dig_port->base.get_config(&dig_port->base, pipe_config);  in intel_dp_mst_enc_get_config()
1357 	struct intel_digital_port *dig_port = intel_mst->primary;  in intel_dp_mst_initial_fastset_check()
1359 	return intel_dp_initial_fastset_check(&dig_port->base, crtc_state);  in intel_dp_mst_initial_fastset_check()
1365 	struct drm_i915_private *i915 = to_i915(intel_connector->base.dev);  in intel_dp_mst_get_ddc_modes()
1366 	struct intel_dp *intel_dp = intel_connector->mst_port;  in intel_dp_mst_get_ddc_modes()
1376 	drm_edid = drm_dp_mst_edid_read(connector, &intel_dp->mst_mgr, intel_connector->port);  in intel_dp_mst_get_ddc_modes()
1392 						 intel_connector->port);  in intel_dp_mst_connector_late_register()
1399 						      intel_connector->port);  in intel_dp_mst_connector_late_register()
1411 					      intel_connector->port);  in intel_dp_mst_connector_early_unregister()
1436 	struct drm_i915_private *dev_priv = to_i915(connector->dev);  in intel_dp_mst_mode_valid_ctx()
1438 	struct intel_dp *intel_dp = intel_connector->mst_port;  in intel_dp_mst_mode_valid_ctx()
1439 	struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;  in intel_dp_mst_mode_valid_ctx()
1440 	struct drm_dp_mst_port *port = intel_connector->port;  in intel_dp_mst_mode_valid_ctx()
1442 	int max_dotclk = to_i915(connector->dev)->display.cdclk.max_dotclk_freq;  in intel_dp_mst_mode_valid_ctx()
1448 	int target_clock = mode->clock;  in intel_dp_mst_mode_valid_ctx()
1459 	if (mode->flags & DRM_MODE_FLAG_DBLCLK) {  in intel_dp_mst_mode_valid_ctx()
1464 	if (mode->clock < 10000) {  in intel_dp_mst_mode_valid_ctx()
1474 	mode_rate = intel_dp_link_required(mode->clock, min_bpp);  in intel_dp_mst_mode_valid_ctx()
1478 	 * - Also check if compression would allow for the mode  in intel_dp_mst_mode_valid_ctx()
1479 	 * - Calculate the overhead using drm_dp_bw_overhead() /  in intel_dp_mst_mode_valid_ctx()
1483 	 * - Check here and during compute config the BW reported by  in intel_dp_mst_mode_valid_ctx()
1489 				 mode->hdisplay, target_clock)) {  in intel_dp_mst_mode_valid_ctx()
1494 	ret = drm_modeset_lock(&mgr->base.lock, ctx);  in intel_dp_mst_mode_valid_ctx()
1498 	if (mode_rate > max_rate || mode->clock > max_dotclk ||  in intel_dp_mst_mode_valid_ctx()
1499 	    drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) {  in intel_dp_mst_mode_valid_ctx()
1511 		if (drm_dp_sink_supports_fec(intel_connector->dp.fec_capability)) {  in intel_dp_mst_mode_valid_ctx()
1517 								    mode->hdisplay,  in intel_dp_mst_mode_valid_ctx()
1524 							     mode->hdisplay,  in intel_dp_mst_mode_valid_ctx()
1551 	struct intel_dp *intel_dp = intel_connector->mst_port;  in intel_mst_atomic_best_encoder()
1552 	struct intel_crtc *crtc = to_intel_crtc(connector_state->crtc);  in intel_mst_atomic_best_encoder()
1554 	return &intel_dp->mst_encoders[crtc->pipe]->base.base;  in intel_mst_atomic_best_encoder()
1561 	struct drm_i915_private *i915 = to_i915(connector->dev);  in intel_dp_mst_detect()
1563 	struct intel_dp *intel_dp = intel_connector->mst_port;  in intel_dp_mst_detect()
1572 		return connector->status;  in intel_dp_mst_detect()
1574 	return drm_dp_mst_detect_port(connector, ctx, &intel_dp->mst_mgr,  in intel_dp_mst_detect()
1575 				      intel_connector->port);  in intel_dp_mst_detect()
1600 	if (intel_attached_encoder(connector) && connector->base.state->crtc) {  in intel_dp_mst_get_hw_state()
1602 		if (!intel_attached_encoder(connector)->get_hw_state(intel_attached_encoder(connector), &pipe))  in intel_dp_mst_get_hw_state()
1613 	struct drm_i915_private *i915 = to_i915(connector->dev);  in intel_dp_mst_add_properties()
1615 	drm_object_attach_property(&connector->base,  in intel_dp_mst_add_properties()
1616 				   i915->drm.mode_config.path_property, 0);  in intel_dp_mst_add_properties()
1617 	drm_object_attach_property(&connector->base,  in intel_dp_mst_add_properties()
1618 				   i915->drm.mode_config.tile_property, 0);  in intel_dp_mst_add_properties()
1627 	connector->max_bpc_property =  in intel_dp_mst_add_properties()
1628 		intel_dp->attached_connector->base.max_bpc_property;  in intel_dp_mst_add_properties()
1629 	if (connector->max_bpc_property)  in intel_dp_mst_add_properties()
1641 	if (!connector->dp.dsc_decompression_aux)  in intel_dp_mst_read_decompression_port_dsc_caps()
1644 	if (drm_dp_read_dpcd_caps(connector->dp.dsc_decompression_aux, dpcd_caps) < 0)  in intel_dp_mst_read_decompression_port_dsc_caps()
1652 	struct drm_i915_private *i915 = to_i915(connector->base.dev);  in detect_dsc_hblank_expansion_quirk()
1653 	struct drm_dp_aux *aux = connector->dp.dsc_decompression_aux;  in detect_dsc_hblank_expansion_quirk()
1664 	if (drm_dp_mst_port_is_logical(connector->port)) {  in detect_dsc_hblank_expansion_quirk()
1665 		aux = drm_dp_mst_aux_for_parent(connector->port);  in detect_dsc_hblank_expansion_quirk()
1667 			aux = &connector->mst_port->aux;  in detect_dsc_hblank_expansion_quirk()
1690 	drm_dbg_kms(&i915->drm,  in detect_dsc_hblank_expansion_quirk()
1692 		    connector->base.base.id, connector->base.name);  in detect_dsc_hblank_expansion_quirk()
1703 	struct drm_device *dev = dig_port->base.base.dev;  in intel_dp_add_mst_connector()
1714 	intel_connector->get_hw_state = intel_dp_mst_get_hw_state;  in intel_dp_add_mst_connector()
1715 	intel_connector->sync_state = intel_dp_connector_sync_state;  in intel_dp_add_mst_connector()
1716 	intel_connector->mst_port = intel_dp;  in intel_dp_add_mst_connector()
1717 	intel_connector->port = port;  in intel_dp_add_mst_connector()
1722 	intel_connector->dp.dsc_decompression_aux = drm_dp_mst_dsc_aux_for_port(port);  in intel_dp_add_mst_connector()
1724 	intel_connector->dp.dsc_hblank_expansion_quirk =  in intel_dp_add_mst_connector()
1727 	connector = &intel_connector->base;  in intel_dp_add_mst_connector()
1740 			&intel_dp->mst_encoders[pipe]->base.base;  in intel_dp_add_mst_connector()
1742 		ret = drm_connector_attach_encoder(&intel_connector->base, enc);  in intel_dp_add_mst_connector()
1753 		drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP MST init failed, skipping.\n",  in intel_dp_add_mst_connector()
1754 			    connector->name, connector->base.id);  in intel_dp_add_mst_connector()
1781 	struct drm_device *dev = dig_port->base.base.dev;  in intel_dp_create_fake_mst_encoder()
1788 	intel_mst->pipe = pipe;  in intel_dp_create_fake_mst_encoder()
1789 	intel_encoder = &intel_mst->base;  in intel_dp_create_fake_mst_encoder()
1790 	intel_mst->primary = dig_port;  in intel_dp_create_fake_mst_encoder()
1792 	drm_encoder_init(dev, &intel_encoder->base, &intel_dp_mst_enc_funcs,  in intel_dp_create_fake_mst_encoder()
1793 			 DRM_MODE_ENCODER_DPMST, "DP-MST %c", pipe_name(pipe));  in intel_dp_create_fake_mst_encoder()
1795 	intel_encoder->type = INTEL_OUTPUT_DP_MST;  in intel_dp_create_fake_mst_encoder()
1796 	intel_encoder->power_domain = dig_port->base.power_domain;  in intel_dp_create_fake_mst_encoder()
1797 	intel_encoder->port = dig_port->base.port;  in intel_dp_create_fake_mst_encoder()
1798 	intel_encoder->cloneable = 0;  in intel_dp_create_fake_mst_encoder()
1807 	intel_encoder->pipe_mask = ~0;  in intel_dp_create_fake_mst_encoder()
1809 	intel_encoder->compute_config = intel_dp_mst_compute_config;  in intel_dp_create_fake_mst_encoder()
1810 	intel_encoder->compute_config_late = intel_dp_mst_compute_config_late;  in intel_dp_create_fake_mst_encoder()
1811 	intel_encoder->disable = intel_mst_disable_dp;  in intel_dp_create_fake_mst_encoder()
1812 	intel_encoder->post_disable = intel_mst_post_disable_dp;  in intel_dp_create_fake_mst_encoder()
1813 	intel_encoder->post_pll_disable = intel_mst_post_pll_disable_dp;  in intel_dp_create_fake_mst_encoder()
1814 	intel_encoder->update_pipe = intel_ddi_update_pipe;  in intel_dp_create_fake_mst_encoder()
1815 	intel_encoder->pre_pll_enable = intel_mst_pre_pll_enable_dp;  in intel_dp_create_fake_mst_encoder()
1816 	intel_encoder->pre_enable = intel_mst_pre_enable_dp;  in intel_dp_create_fake_mst_encoder()
1817 	intel_encoder->enable = intel_mst_enable_dp;  in intel_dp_create_fake_mst_encoder()
1818 	intel_encoder->audio_enable = intel_audio_codec_enable;  in intel_dp_create_fake_mst_encoder()
1819 	intel_encoder->audio_disable = intel_audio_codec_disable;  in intel_dp_create_fake_mst_encoder()
1820 	intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;  in intel_dp_create_fake_mst_encoder()
1821 	intel_encoder->get_config = intel_dp_mst_enc_get_config;  in intel_dp_create_fake_mst_encoder()
1822 	intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;  in intel_dp_create_fake_mst_encoder()
1831 	struct intel_dp *intel_dp = &dig_port->dp;  in intel_dp_create_fake_mst_encoders()
1832 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);  in intel_dp_create_fake_mst_encoders()
1836 		intel_dp->mst_encoders[pipe] = intel_dp_create_fake_mst_encoder(dig_port, pipe);  in intel_dp_create_fake_mst_encoders()
1843 	return dig_port->dp.active_mst_links;  in intel_dp_mst_encoder_active_links()
1849 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);  in intel_dp_mst_encoder_init()
1850 	struct intel_dp *intel_dp = &dig_port->dp;  in intel_dp_mst_encoder_init()
1851 	enum port port = dig_port->base.port;  in intel_dp_mst_encoder_init()
1863 	intel_dp->mst_mgr.cbs = &mst_cbs;  in intel_dp_mst_encoder_init()
1867 	ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm,  in intel_dp_mst_encoder_init()
1868 					   &intel_dp->aux, 16, 3, conn_base_id);  in intel_dp_mst_encoder_init()
1870 		intel_dp->mst_mgr.cbs = NULL;  in intel_dp_mst_encoder_init()
1879 	return intel_dp->mst_mgr.cbs;  in intel_dp_mst_source_support()
1885 	struct intel_dp *intel_dp = &dig_port->dp;  in intel_dp_mst_encoder_cleanup()
1890 	drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr);  in intel_dp_mst_encoder_cleanup()
1893 	intel_dp->mst_mgr.cbs = NULL;  in intel_dp_mst_encoder_cleanup()
1898 	return crtc_state->mst_master_transcoder == crtc_state->cpu_transcoder;  in intel_dp_mst_is_master_trans()
1903 	return crtc_state->mst_master_transcoder != INVALID_TRANSCODER &&  in intel_dp_mst_is_slave_trans()
1904 	       crtc_state->mst_master_transcoder != crtc_state->cpu_transcoder;  in intel_dp_mst_is_slave_trans()
1908  * intel_dp_mst_add_topology_state_for_connector - add MST topology state for a connector
1924 	if (!connector->mst_port)  in intel_dp_mst_add_topology_state_for_connector()
1927 	mst_state = drm_atomic_get_mst_topology_state(&state->base,  in intel_dp_mst_add_topology_state_for_connector()
1928 						      &connector->mst_port->mst_mgr);  in intel_dp_mst_add_topology_state_for_connector()
1932 	mst_state->pending_crtc_mask |= drm_crtc_mask(&crtc->base);  in intel_dp_mst_add_topology_state_for_connector()
1938  * intel_dp_mst_add_topology_state_for_crtc - add MST topology state for a CRTC
1953 	for_each_new_connector_in_state(&state->base, _connector, conn_state, i) {  in intel_dp_mst_add_topology_state_for_crtc()
1957 		if (conn_state->crtc != &crtc->base)  in intel_dp_mst_add_topology_state_for_crtc()
1977 	for_each_oldnew_connector_in_state(&state->base, _connector,  in get_connector_in_state_for_crtc()
1982 		if (old_conn_state->crtc == &crtc->base ||  in get_connector_in_state_for_crtc()
1983 		    new_conn_state->crtc == &crtc->base)  in get_connector_in_state_for_crtc()
1991  * intel_dp_mst_crtc_needs_modeset - check if changes in topology need to modeset the given CRTC
2019 	for_each_new_connector_in_state(&state->base, _connector, conn_state, i) {  in intel_dp_mst_crtc_needs_modeset()
2026 		if (connector->mst_port != crtc_connector->mst_port ||  in intel_dp_mst_crtc_needs_modeset()
2027 		    !conn_state->crtc)  in intel_dp_mst_crtc_needs_modeset()
2030 		crtc_iter = to_intel_crtc(conn_state->crtc);  in intel_dp_mst_crtc_needs_modeset()
2038 		if (old_crtc_state->dsc.compression_enable ==  in intel_dp_mst_crtc_needs_modeset()
2039 		    new_crtc_state->dsc.compression_enable)  in intel_dp_mst_crtc_needs_modeset()
2048 		if (connector->dp.dsc_decompression_aux ==  in intel_dp_mst_crtc_needs_modeset()
2049 		    &connector->mst_port->aux)  in intel_dp_mst_crtc_needs_modeset()
2057  * intel_dp_mst_prepare_probe - Prepare an MST link for topology probing
2071 	if (intel_dp->link_trained)  in intel_dp_mst_prepare_probe()
2081 				      drm_dp_enhanced_frame_cap(intel_dp->dpcd));  in intel_dp_mst_prepare_probe()
2087  * intel_dp_mst_verify_dpcd_state - verify the MST SW enabled state wrt. the DPCD
2091  * state. A long HPD pulse - not long enough to be detected as a disconnected
2092  * state - could've reset the DPCD state, which requires tearing
2101 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_mst_verify_dpcd_state()
2103 	struct intel_encoder *encoder = &dig_port->base;  in intel_dp_mst_verify_dpcd_state()
2107 	if (!intel_dp->is_mst)  in intel_dp_mst_verify_dpcd_state()
2110 	ret = drm_dp_dpcd_readb(intel_dp->mst_mgr.aux, DP_MSTM_CTRL, &val);  in intel_dp_mst_verify_dpcd_state()
2114 		drm_dbg_kms(display->drm,  in intel_dp_mst_verify_dpcd_state()
2116 			    connector->base.base.id, connector->base.name,  in intel_dp_mst_verify_dpcd_state()
2117 			    encoder->base.base.id, encoder->base.name,  in intel_dp_mst_verify_dpcd_state()