900 					u32 timeslots)  in intel_dp_dsc_get_max_compressed_bpp()  argument
920 	bits_per_pixel = ((link_clock * lane_count) * timeslots) /  in intel_dp_dsc_get_max_compressed_bpp()
938 				bits_per_pixel, timeslots,  in intel_dp_dsc_get_max_compressed_bpp()
1891 					    int timeslots)  in is_bw_sufficient_for_dsc_config()  argument
1895 	available_bw = (link_clock * lane_count * timeslots * 16)  / 8;  in is_bw_sufficient_for_dsc_config()
1905 				   int timeslots)  in dsc_compute_link_config()  argument
1922 							     timeslots))  in dsc_compute_link_config()
2018 			    int timeslots)  in icl_dsc_compute_link_config()  argument
2035 					      timeslots);  in icl_dsc_compute_link_config()
2060 			      int timeslots)  in xelpd_dsc_compute_link_config()  argument
2087 					      timeslots);  in xelpd_dsc_compute_link_config()
2105 				      int timeslots)  in dsc_compute_compressed_bpp()  argument
2132 						     dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);  in dsc_compute_compressed_bpp()
2134 					   dsc_max_bpp, dsc_min_bpp, pipe_bpp, timeslots);  in dsc_compute_compressed_bpp()
2190 					 int timeslots)  in intel_dp_dsc_compute_pipe_bpp()  argument
2206 						 limits, forced_bpp, timeslots);  in intel_dp_dsc_compute_pipe_bpp()
2235 						 limits, pipe_bpp, timeslots);  in intel_dp_dsc_compute_pipe_bpp()
2302 				int timeslots,  in intel_dp_dsc_compute_config()  argument
2335 							    conn_state, limits, timeslots);  in intel_dp_dsc_compute_config()