792 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)  in intel_dp_mode_to_fec_clock()  argument
794 	return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR),  in intel_dp_mode_to_fec_clock()
870 				       u32 mode_clock, u32 mode_hdisplay,  in get_max_compressed_bpp_with_joiner()  argument
884 			intel_dp_mode_to_fec_clock(mode_clock);  in get_max_compressed_bpp_with_joiner()
896 					u32 mode_clock, u32 mode_hdisplay,  in intel_dp_dsc_get_max_compressed_bpp()  argument
921 			 (intel_dp_mode_to_fec_clock(mode_clock) * 8);  in intel_dp_dsc_get_max_compressed_bpp()
940 				intel_dp_mode_to_fec_clock(mode_clock));  in intel_dp_dsc_get_max_compressed_bpp()
942 	joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, mode_clock,  in intel_dp_dsc_get_max_compressed_bpp()
952 				int mode_clock, int mode_hdisplay,  in intel_dp_dsc_get_slice_count()  argument
959 	if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)  in intel_dp_dsc_get_slice_count()
960 		min_slice_count = DIV_ROUND_UP(mode_clock,  in intel_dp_dsc_get_slice_count()
963 		min_slice_count = DIV_ROUND_UP(mode_clock,  in intel_dp_dsc_get_slice_count()
970 	if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100))  in intel_dp_dsc_get_slice_count()
1889 					    u32 lane_count, u32 mode_clock,  in is_bw_sufficient_for_dsc_config()  argument
1896 	required_bw = compressed_bppx16 * (intel_dp_mode_to_fec_clock(mode_clock));  in is_bw_sufficient_for_dsc_config()