93 #define dp_to_i915(__intel_dp) to_i915(dp_to_dig_port(__intel_dp)->base.base.dev)
122  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
134 	return dig_port->base.type == INTEL_OUTPUT_EDP;  in intel_dp_is_edp()
142 	return drm_dp_is_uhbr_rate(crtc_state->port_clock);  in intel_dp_is_uhbr()
146  * intel_dp_link_symbol_size - get the link symbol size for a given link rate
150  * rate -> channel coding.
158  * intel_dp_link_symbol_clock - convert link rate to link symbol clock
172 		return drm_dp_tunnel_max_dprx_rate(intel_dp->tunnel);  in max_dprx_rate()
174 	return drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);  in max_dprx_rate()
180 		return drm_dp_tunnel_max_dprx_lane_count(intel_dp->tunnel);  in max_dprx_lane_count()
182 	return drm_dp_max_lane_count(intel_dp->dpcd);  in max_dprx_lane_count()
187 	intel_dp->sink_rates[0] = 162000;  in intel_dp_set_default_sink_rates()
188 	intel_dp->num_sink_rates = 1;  in intel_dp_set_default_sink_rates()
200 	if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {  in intel_dp_set_dpcd_sink_rates()
201 		/* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */  in intel_dp_set_dpcd_sink_rates()
204 		memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));  in intel_dp_set_dpcd_sink_rates()
205 		intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);  in intel_dp_set_dpcd_sink_rates()
214 	max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);  in intel_dp_set_dpcd_sink_rates()
221 		intel_dp->sink_rates[i] = dp_rates[i];  in intel_dp_set_dpcd_sink_rates()
228 	if (drm_dp_128b132b_supported(intel_dp->dpcd)) {  in intel_dp_set_dpcd_sink_rates()
231 		BUILD_BUG_ON(ARRAY_SIZE(intel_dp->sink_rates) < ARRAY_SIZE(dp_rates) + 3);  in intel_dp_set_dpcd_sink_rates()
233 		drm_dp_dpcd_readb(&intel_dp->aux,  in intel_dp_set_dpcd_sink_rates()
236 		if (drm_dp_lttpr_count(intel_dp->lttpr_common_caps)) {  in intel_dp_set_dpcd_sink_rates()
238 			if (intel_dp->lttpr_common_caps[0] >= 0x20 &&  in intel_dp_set_dpcd_sink_rates()
239 			    intel_dp->lttpr_common_caps[DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER -  in intel_dp_set_dpcd_sink_rates()
243 				uhbr_rates &= intel_dp->lttpr_common_caps[DP_PHY_REPEATER_128B132B_RATES -  in intel_dp_set_dpcd_sink_rates()
252 			intel_dp->sink_rates[i++] = 1000000;  in intel_dp_set_dpcd_sink_rates()
254 			intel_dp->sink_rates[i++] = 1350000;  in intel_dp_set_dpcd_sink_rates()
256 			intel_dp->sink_rates[i++] = 2000000;  in intel_dp_set_dpcd_sink_rates()
259 	intel_dp->num_sink_rates = i;  in intel_dp_set_dpcd_sink_rates()
264 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_set_sink_rates()
266 	struct intel_encoder *encoder = &intel_dig_port->base;  in intel_dp_set_sink_rates()
270 	if (intel_dp->num_sink_rates)  in intel_dp_set_sink_rates()
273 	drm_err(&dp_to_i915(intel_dp)->drm,  in intel_dp_set_sink_rates()
275 		connector->base.base.id, connector->base.name,  in intel_dp_set_sink_rates()
276 		encoder->base.base.id, encoder->base.name);  in intel_dp_set_sink_rates()
283 	intel_dp->max_sink_lane_count = 1;  in intel_dp_set_default_max_sink_lane_count()
288 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_set_max_sink_lane_count()
290 	struct intel_encoder *encoder = &intel_dig_port->base;  in intel_dp_set_max_sink_lane_count()
292 	intel_dp->max_sink_lane_count = max_dprx_lane_count(intel_dp);  in intel_dp_set_max_sink_lane_count()
294 	switch (intel_dp->max_sink_lane_count) {  in intel_dp_set_max_sink_lane_count()
301 	drm_err(&dp_to_i915(intel_dp)->drm,  in intel_dp_set_max_sink_lane_count()
303 		connector->base.base.id, connector->base.name,  in intel_dp_set_max_sink_lane_count()
304 		encoder->base.base.id, encoder->base.name,  in intel_dp_set_max_sink_lane_count()
305 		intel_dp->max_sink_lane_count);  in intel_dp_set_max_sink_lane_count()
317 		if (rates[len - i - 1] <= max_rate)  in intel_dp_rate_limit_len()
318 			return len - i;  in intel_dp_rate_limit_len()
328 	return intel_dp_rate_limit_len(intel_dp->common_rates,  in intel_dp_common_len_rate_limit()
329 				       intel_dp->num_common_rates, max_rate);  in intel_dp_common_len_rate_limit()
334 	if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm,  in intel_dp_common_rate()
335 			index < 0 || index >= intel_dp->num_common_rates))  in intel_dp_common_rate()
338 	return intel_dp->common_rates[index];  in intel_dp_common_rate()
344 	return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1);  in intel_dp_max_common_rate()
349 	int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata);  in intel_dp_max_source_lane_count()
350 	int max_lanes = dig_port->max_lanes;  in intel_dp_max_source_lane_count()
363 	int sink_max = intel_dp->max_sink_lane_count;  in intel_dp_max_common_lane_count()
365 	int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);  in intel_dp_max_common_lane_count()
375 	return clamp(intel_dp->link.force_lane_count, 1, intel_dp_max_common_lane_count(intel_dp));  in forced_lane_count()
382 	if (intel_dp->link.force_lane_count)  in intel_dp_max_lane_count()
385 		lane_count = intel_dp->link.max_lane_count;  in intel_dp_max_lane_count()
400 	if (intel_dp->link.force_lane_count)  in intel_dp_min_lane_count()
421  * intel_dp_effective_data_rate - Return the pixel data rate accounting for BW allocation overhead
454 			       drm_dp_tunnel_available_bw(intel_dp->tunnel));  in intel_dp_max_link_data_rate()
462 	struct intel_encoder *encoder = &intel_dig_port->base;  in intel_dp_has_joiner()
463 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_dp_has_joiner()
466 	if (intel_dp->mso_link_count)  in intel_dp_has_joiner()
471 		 encoder->port != PORT_A);  in intel_dp_has_joiner()
481 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in icl_max_source_rate()
499 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in mtl_max_source_rate()
504 	if (DISPLAY_VER_FULL(to_i915(encoder->base.dev)) == IP_VER(14, 1))  in mtl_max_source_rate()
512 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in vbt_max_link_rate()
515 	max_rate = intel_bios_dp_max_link_rate(encoder->devdata);  in vbt_max_link_rate()
518 		struct intel_connector *connector = intel_dp->attached_connector;  in vbt_max_link_rate()
519 		int edp_max_rate = connector->panel.vbt.edp.max_link_rate;  in vbt_max_link_rate()
559 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);  in intel_dp_set_source_rates()
564 	drm_WARN_ON(&dev_priv->drm,  in intel_dp_set_source_rates()
565 		    intel_dp->source_rates || intel_dp->num_source_rates);  in intel_dp_set_source_rates()
591 	} else if (DISPLAY_VER(dev_priv) == 9) {  in intel_dp_set_source_rates()
612 	intel_dp->source_rates = source_rates;  in intel_dp_set_source_rates()
613 	intel_dp->num_source_rates = size;  in intel_dp_set_source_rates()
639 /* return index of rate in rates array, or -1 if not found */
648 	return -1;  in intel_dp_rate_index()
654 	return intel_dp_common_rate(intel_dp, lc->link_rate_idx);  in intel_dp_link_config_rate()
659 	return 1 << lc->lane_count_exp;  in intel_dp_link_config_lane_count()
678 		return bw_a - bw_b;  in link_config_cmp_by_bw()
680 	return intel_dp_link_config_rate(intel_dp, lc_a) -  in link_config_cmp_by_bw()
692 	if (drm_WARN_ON(&i915->drm, !is_power_of_2(intel_dp_max_common_lane_count(intel_dp))))  in intel_dp_link_config_init()
697 	if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates * num_common_lane_configs >  in intel_dp_link_config_init()
698 				    ARRAY_SIZE(intel_dp->link.configs)))  in intel_dp_link_config_init()
701 	intel_dp->link.num_configs = intel_dp->num_common_rates * num_common_lane_configs;  in intel_dp_link_config_init()
703 	lc = &intel_dp->link.configs[0];  in intel_dp_link_config_init()
704 	for (i = 0; i < intel_dp->num_common_rates; i++) {  in intel_dp_link_config_init()
706 			lc->lane_count_exp = j;  in intel_dp_link_config_init()
707 			lc->link_rate_idx = i;  in intel_dp_link_config_init()
713 	sort_r(intel_dp->link.configs, intel_dp->link.num_configs,  in intel_dp_link_config_init()
714 	       sizeof(intel_dp->link.configs[0]),  in intel_dp_link_config_init()
724 	if (drm_WARN_ON(&i915->drm, idx < 0 || idx >= intel_dp->link.num_configs))  in intel_dp_link_config_get()
727 	lc = &intel_dp->link.configs[idx];  in intel_dp_link_config_get()
735 	int link_rate_idx = intel_dp_rate_index(intel_dp->common_rates, intel_dp->num_common_rates,  in intel_dp_link_config_index()
740 	for (i = 0; i < intel_dp->link.num_configs; i++) {  in intel_dp_link_config_index()
741 		const struct intel_dp_link_config *lc = &intel_dp->link.configs[i];  in intel_dp_link_config_index()
743 		if (lc->lane_count_exp == lane_count_exp &&  in intel_dp_link_config_index()
744 		    lc->link_rate_idx == link_rate_idx)  in intel_dp_link_config_index()
748 	return -1;  in intel_dp_link_config_index()
755 	drm_WARN_ON(&i915->drm,  in intel_dp_set_common_rates()
756 		    !intel_dp->num_source_rates || !intel_dp->num_sink_rates);  in intel_dp_set_common_rates()
758 	intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,  in intel_dp_set_common_rates()
759 						     intel_dp->num_source_rates,  in intel_dp_set_common_rates()
760 						     intel_dp->sink_rates,  in intel_dp_set_common_rates()
761 						     intel_dp->num_sink_rates,  in intel_dp_set_common_rates()
762 						     intel_dp->common_rates);  in intel_dp_set_common_rates()
765 	if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {  in intel_dp_set_common_rates()
766 		intel_dp->common_rates[0] = 162000;  in intel_dp_set_common_rates()
767 		intel_dp->num_common_rates = 1;  in intel_dp_set_common_rates()
779 	 * boot-up.  in intel_dp_link_params_valid()
782 	    link_rate > intel_dp->link.max_rate)  in intel_dp_link_params_valid()
802 	 * The hard-coded 1/0.972261=2.853% overhead factor  in intel_dp_bw_fec_overhead()
830 		drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",  in intel_dp_dsc_nearest_valid_bpp()
835 	/* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */  in intel_dp_dsc_nearest_valid_bpp()
837 		bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);  in intel_dp_dsc_nearest_valid_bpp()
848 			drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min 8\n",  in intel_dp_dsc_nearest_valid_bpp()
855 		for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {  in intel_dp_dsc_nearest_valid_bpp()
859 		drm_dbg_kms(&i915->drm, "Set dsc bpp from %d to VESA %d\n",  in intel_dp_dsc_nearest_valid_bpp()
883 			i915->display.cdclk.max_cdclk_freq * ppc * bigjoiner_interface_bits /  in get_max_compressed_bpp_with_joiner()
907 	 * for SST -> TimeSlots is 64(i.e all TimeSlots that are available)  in intel_dp_dsc_get_max_compressed_bpp()
908 	 * for MST -> TimeSlots has to be calculated, based on mode requirements  in intel_dp_dsc_get_max_compressed_bpp()
936 	drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots "  in intel_dp_dsc_get_max_compressed_bpp()
955 	struct drm_i915_private *i915 = to_i915(connector->base.dev);  in intel_dp_dsc_get_slice_count()
970 	if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100))  in intel_dp_dsc_get_slice_count()
973 	max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd);  in intel_dp_dsc_get_slice_count()
975 		drm_dbg_kms(&i915->drm,  in intel_dp_dsc_get_slice_count()
990 		    drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false))  in intel_dp_dsc_get_slice_count()
1001 	drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",  in intel_dp_dsc_get_slice_count()
1037 	if (!drm_dp_is_branch(intel_dp->dpcd))  in dfp_can_convert_from_rgb()
1041 		return intel_dp->dfp.rgb_to_ycbcr;  in dfp_can_convert_from_rgb()
1044 		return intel_dp->dfp.rgb_to_ycbcr &&  in dfp_can_convert_from_rgb()
1045 			intel_dp->dfp.ycbcr_444_to_420;  in dfp_can_convert_from_rgb()
1054 	if (!drm_dp_is_branch(intel_dp->dpcd))  in dfp_can_convert_from_ycbcr444()
1058 		return intel_dp->dfp.ycbcr_444_to_420;  in dfp_can_convert_from_ycbcr444()
1088 		intel_dp->force_dsc_output_format;  in intel_dp_output_format()
1092 		    (!drm_dp_is_branch(intel_dp->dpcd) ||  in intel_dp_output_format()
1097 		drm_dbg_kms(&i915->drm, "Cannot force DSC output format\n");  in intel_dp_output_format()
1111 	drm_WARN_ON(&i915->drm, !source_can_output(intel_dp, output_format));  in intel_dp_output_format()
1141 	const struct drm_display_info *info = &connector->base.display_info;  in intel_dp_sink_format()
1183 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_max_tmds_clock()
1184 	const struct drm_display_info *info = &connector->base.display_info;  in intel_dp_max_tmds_clock()
1185 	int max_tmds_clock = intel_dp->dfp.max_tmds_clock;  in intel_dp_max_tmds_clock()
1188 	if (max_tmds_clock && info->max_tmds_clock)  in intel_dp_max_tmds_clock()
1189 		max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock);  in intel_dp_max_tmds_clock()
1207 	min_tmds_clock = intel_dp->dfp.min_tmds_clock;  in intel_dp_tmds_clock_valid()
1225 	const struct drm_display_info *info = &connector->base.display_info;  in intel_dp_mode_valid_downstream()
1230 	if (intel_dp->dfp.pcon_max_frl_bw) {  in intel_dp_mode_valid_downstream()
1237 		max_frl_bw = intel_dp->dfp.pcon_max_frl_bw;  in intel_dp_mode_valid_downstream()
1248 	if (intel_dp->dfp.max_dotclock &&  in intel_dp_mode_valid_downstream()
1249 	    target_clock > intel_dp->dfp.max_dotclock)  in intel_dp_mode_valid_downstream()
1260 		    !connector->base.ycbcr_420_allowed ||  in intel_dp_mode_valid_downstream()
1282 	return clock > i915->display.cdclk.max_dotclk_freq || hdisplay > 5120 ||  in intel_dp_need_joiner()
1283 	       connector->force_bigjoiner_enable;  in intel_dp_need_joiner()
1288 	struct drm_i915_private *i915 = to_i915(connector->base.dev);  in intel_dp_has_dsc()
1293 	if (connector->mst_port && !HAS_DSC_MST(i915))  in intel_dp_has_dsc()
1296 	if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP &&  in intel_dp_has_dsc()
1297 	    connector->panel.vbt.edp.dsc_disable)  in intel_dp_has_dsc()
1300 	if (!drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd))  in intel_dp_has_dsc()
1312 	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);  in intel_dp_mode_valid()
1314 	int target_clock = mode->clock;  in intel_dp_mode_valid()
1316 	int max_dotclk = dev_priv->display.cdclk.max_dotclk_freq;  in intel_dp_mode_valid()
1326 	if (mode->flags & DRM_MODE_FLAG_DBLCLK)  in intel_dp_mode_valid()
1329 	if (mode->clock < 10000)  in intel_dp_mode_valid()
1338 		target_clock = fixed_mode->clock;  in intel_dp_mode_valid()
1342 				 mode->hdisplay, target_clock)) {  in intel_dp_mode_valid()
1349 	if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))  in intel_dp_mode_valid()
1378 				drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4;  in intel_dp_mode_valid()
1380 				drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,  in intel_dp_mode_valid()
1382 		} else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {  in intel_dp_mode_valid()
1388 								    mode->hdisplay,  in intel_dp_mode_valid()
1395 							     mode->hdisplay,  in intel_dp_mode_valid()
1417 	return DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915) || IS_HASWELL(i915);  in intel_dp_source_supports_tps3()
1437 		len -= r;  in snprintf_int_array()
1450 			   intel_dp->source_rates, intel_dp->num_source_rates);  in intel_dp_print_rates()
1451 	drm_dbg_kms(&i915->drm, "source rates: %s\n", str);  in intel_dp_print_rates()
1454 			   intel_dp->sink_rates, intel_dp->num_sink_rates);  in intel_dp_print_rates()
1455 	drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);  in intel_dp_print_rates()
1458 			   intel_dp->common_rates, intel_dp->num_common_rates);  in intel_dp_print_rates()
1459 	drm_dbg_kms(&i915->drm, "common rates: %s\n", str);  in intel_dp_print_rates()
1464 	int len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.force_rate);  in forced_link_rate()
1469 	return intel_dp_common_rate(intel_dp, len - 1);  in forced_link_rate()
1477 	if (intel_dp->link.force_rate)  in intel_dp_max_link_rate()
1480 	len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.max_rate);  in intel_dp_max_link_rate()
1482 	return intel_dp_common_rate(intel_dp, len - 1);  in intel_dp_max_link_rate()
1488 	if (intel_dp->link.force_rate)  in intel_dp_min_link_rate()
1497 	int i = intel_dp_rate_index(intel_dp->sink_rates,  in intel_dp_rate_select()
1498 				    intel_dp->num_sink_rates, rate);  in intel_dp_rate_select()
1500 	if (drm_WARN_ON(&i915->drm, i < 0))  in intel_dp_rate_select()
1510 	if (intel_dp->use_rate_select) {  in intel_dp_compute_rate()
1522 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_has_hdmi_sink()
1524 	return connector->base.display_info.is_hdmi;  in intel_dp_has_hdmi_sink()
1530 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in intel_dp_source_supports_fec()
1536 	if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A &&  in intel_dp_source_supports_fec()
1548 		drm_dp_sink_supports_fec(connector->dp.fec_capability);  in intel_dp_supports_fec()
1557 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)  in intel_dp_supports_dsc()
1567 	int clock = crtc_state->hw.adjusted_mode.crtc_clock;  in intel_dp_hdmi_compute_bpc()
1584 	for (; bpc >= 8; bpc -= 2) {  in intel_dp_hdmi_compute_bpc()
1587 		    intel_dp_tmds_clock_valid(intel_dp, clock, bpc, crtc_state->sink_format,  in intel_dp_hdmi_compute_bpc()
1592 	return -EINVAL;  in intel_dp_hdmi_compute_bpc()
1600 	struct intel_connector *intel_connector = intel_dp->attached_connector;  in intel_dp_max_bpp()
1603 	bpc = crtc_state->pipe_bpp / 3;  in intel_dp_max_bpp()
1605 	if (intel_dp->dfp.max_bpc)  in intel_dp_max_bpp()
1606 		bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);  in intel_dp_max_bpp()
1608 	if (intel_dp->dfp.min_tmds_clock) {  in intel_dp_max_bpp()
1622 		if (intel_connector->base.display_info.bpc == 0 &&  in intel_dp_max_bpp()
1623 		    intel_connector->panel.vbt.edp.bpp &&  in intel_dp_max_bpp()
1624 		    intel_connector->panel.vbt.edp.bpp < bpp) {  in intel_dp_max_bpp()
1625 			drm_dbg_kms(&dev_priv->drm,  in intel_dp_max_bpp()
1626 				    "clamping bpp for eDP panel to BIOS-provided %i\n",  in intel_dp_max_bpp()
1627 				    intel_connector->panel.vbt.edp.bpp);  in intel_dp_max_bpp()
1628 			bpp = intel_connector->panel.vbt.edp.bpp;  in intel_dp_max_bpp()
1644 	if (intel_dp->compliance.test_data.bpc != 0) {  in intel_dp_adjust_compliance_config()
1645 		int bpp = 3 * intel_dp->compliance.test_data.bpc;  in intel_dp_adjust_compliance_config()
1647 		limits->pipe.min_bpp = limits->pipe.max_bpp = bpp;  in intel_dp_adjust_compliance_config()
1648 		pipe_config->dither_force_disable = bpp == 6 * 3;  in intel_dp_adjust_compliance_config()
1650 		drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);  in intel_dp_adjust_compliance_config()
1654 	if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {  in intel_dp_adjust_compliance_config()
1660 		if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,  in intel_dp_adjust_compliance_config()
1661 					       intel_dp->compliance.test_lane_count)) {  in intel_dp_adjust_compliance_config()
1662 			index = intel_dp_rate_index(intel_dp->common_rates,  in intel_dp_adjust_compliance_config()
1663 						    intel_dp->num_common_rates,  in intel_dp_adjust_compliance_config()
1664 						    intel_dp->compliance.test_link_rate);  in intel_dp_adjust_compliance_config()
1666 				limits->min_rate = limits->max_rate =  in intel_dp_adjust_compliance_config()
1667 					intel_dp->compliance.test_link_rate;  in intel_dp_adjust_compliance_config()
1668 			limits->min_lane_count = limits->max_lane_count =  in intel_dp_adjust_compliance_config()
1669 				intel_dp->compliance.test_lane_count;  in intel_dp_adjust_compliance_config()
1676 	struct drm_i915_private *i915 = to_i915(connector->base.dev);  in has_seamless_m_n()
1689 	struct intel_connector *connector = to_intel_connector(conn_state->connector);  in intel_dp_mode_clock()
1690 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_dp_mode_clock()
1694 		return intel_panel_highest_mode(connector, adjusted_mode)->clock;  in intel_dp_mode_clock()
1696 		return adjusted_mode->crtc_clock;  in intel_dp_mode_clock()
1709 	for (bpp = fxp_q4_to_int(limits->link.max_bpp_x16);  in intel_dp_compute_link_config_wide()
1710 	     bpp >= fxp_q4_to_int(limits->link.min_bpp_x16);  in intel_dp_compute_link_config_wide()
1711 	     bpp -= 2 * 3) {  in intel_dp_compute_link_config_wide()
1712 		int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);  in intel_dp_compute_link_config_wide()
1716 		for (i = 0; i < intel_dp->num_common_rates; i++) {  in intel_dp_compute_link_config_wide()
1718 			if (link_rate < limits->min_rate ||  in intel_dp_compute_link_config_wide()
1719 			    link_rate > limits->max_rate)  in intel_dp_compute_link_config_wide()
1722 			for (lane_count = limits->min_lane_count;  in intel_dp_compute_link_config_wide()
1723 			     lane_count <= limits->max_lane_count;  in intel_dp_compute_link_config_wide()
1731 					pipe_config->lane_count = lane_count;  in intel_dp_compute_link_config_wide()
1732 					pipe_config->pipe_bpp = bpp;  in intel_dp_compute_link_config_wide()
1733 					pipe_config->port_clock = link_rate;  in intel_dp_compute_link_config_wide()
1741 	return -EINVAL;  in intel_dp_compute_link_config_wide()
1759 	struct drm_i915_private *i915 = to_i915(connector->base.dev);  in intel_dp_dsc_compute_max_bpp()
1771 	num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,  in intel_dp_dsc_compute_max_bpp()
1788 	return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >>  in intel_dp_sink_dsc_version_minor()
1817 	struct drm_i915_private *i915 = to_i915(connector->base.dev);  in intel_dp_dsc_compute_params()
1818 	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;  in intel_dp_dsc_compute_params()
1827 	vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;  in intel_dp_dsc_compute_params()
1828 	vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;  in intel_dp_dsc_compute_params()
1830 	vdsc_cfg->slice_height = intel_dp_get_slice_height(vdsc_cfg->pic_height);  in intel_dp_dsc_compute_params()
1836 	vdsc_cfg->dsc_version_major =  in intel_dp_dsc_compute_params()
1837 		(connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &  in intel_dp_dsc_compute_params()
1839 	vdsc_cfg->dsc_version_minor =  in intel_dp_dsc_compute_params()
1841 		    intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd));  in intel_dp_dsc_compute_params()
1842 	if (vdsc_cfg->convert_rgb)  in intel_dp_dsc_compute_params()
1843 		vdsc_cfg->convert_rgb =  in intel_dp_dsc_compute_params()
1844 			connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &  in intel_dp_dsc_compute_params()
1847 	vdsc_cfg->line_buf_depth = min(INTEL_DP_DSC_MAX_LINE_BUF_DEPTH,  in intel_dp_dsc_compute_params()
1848 				       drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd));  in intel_dp_dsc_compute_params()
1849 	if (!vdsc_cfg->line_buf_depth) {  in intel_dp_dsc_compute_params()
1850 		drm_dbg_kms(&i915->drm,  in intel_dp_dsc_compute_params()
1852 		return -EINVAL;  in intel_dp_dsc_compute_params()
1855 	vdsc_cfg->block_pred_enable =  in intel_dp_dsc_compute_params()
1856 		connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &  in intel_dp_dsc_compute_params()
1865 	struct drm_i915_private *i915 = to_i915(connector->base.dev);  in intel_dp_dsc_supports_format()
1877 			intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2)  in intel_dp_dsc_supports_format()
1885 	return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format);  in intel_dp_dsc_supports_format()
1907 	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;  in dsc_compute_link_config()
1911 	for (i = 0; i < intel_dp->num_common_rates; i++) {  in dsc_compute_link_config()
1913 		if (link_rate < limits->min_rate || link_rate > limits->max_rate)  in dsc_compute_link_config()
1916 		for (lane_count = limits->min_lane_count;  in dsc_compute_link_config()
1917 		     lane_count <= limits->max_lane_count;  in dsc_compute_link_config()
1920 							     lane_count, adjusted_mode->clock,  in dsc_compute_link_config()
1921 							     pipe_config->output_format,  in dsc_compute_link_config()
1925 			pipe_config->lane_count = lane_count;  in dsc_compute_link_config()
1926 			pipe_config->port_clock = link_rate;  in dsc_compute_link_config()
1932 	return -EINVAL;  in dsc_compute_link_config()
1940 	u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd);  in intel_dp_dsc_max_sink_compressed_bppx16()
1946 	 * values as given in spec Table 2-157 DP v2.0  in intel_dp_dsc_max_sink_compressed_bppx16()
1948 	switch (pipe_config->output_format) {  in intel_dp_dsc_max_sink_compressed_bppx16()
1955 		MISSING_CASE(pipe_config->output_format);  in intel_dp_dsc_max_sink_compressed_bppx16()
1964 	/* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */  in intel_dp_dsc_sink_min_compressed_bpp()
1965 	switch (pipe_config->output_format) {  in intel_dp_dsc_sink_min_compressed_bpp()
1972 		MISSING_CASE(pipe_config->output_format);  in intel_dp_dsc_sink_min_compressed_bpp()
2023 	dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);  in icl_dsc_compute_link_config()
2037 			pipe_config->dsc.compressed_bpp_x16 =  in icl_dsc_compute_link_config()
2043 	return -EINVAL;  in icl_dsc_compute_link_config()
2048  * uncompressed bpp-1. So we start from max compressed bpp and see if any
2062 	u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd);  in xelpd_dsc_compute_link_config()
2074 	dsc_max_bpp = min(dsc_max_bpp << 4, (pipe_bpp << 4) - bppx16_step);  in xelpd_dsc_compute_link_config()
2079 	     compressed_bppx16 -= bppx16_step) {  in xelpd_dsc_compute_link_config()
2080 		if (intel_dp->force_dsc_fractional_bpp_en &&  in xelpd_dsc_compute_link_config()
2089 			pipe_config->dsc.compressed_bpp_x16 = compressed_bppx16;  in xelpd_dsc_compute_link_config()
2090 			if (intel_dp->force_dsc_fractional_bpp_en &&  in xelpd_dsc_compute_link_config()
2092 				drm_dbg_kms(&i915->drm, "Forcing DSC fractional bpp\n");  in xelpd_dsc_compute_link_config()
2097 	return -EINVAL;  in xelpd_dsc_compute_link_config()
2107 	const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;  in dsc_compute_compressed_bpp()
2116 	dsc_min_bpp = max(dsc_min_bpp, fxp_q4_to_int_roundup(limits->link.min_bpp_x16));  in dsc_compute_compressed_bpp()
2124 	dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock,  in dsc_compute_compressed_bpp()
2125 								adjusted_mode->hdisplay,  in dsc_compute_compressed_bpp()
2126 								pipe_config->joiner_pipes);  in dsc_compute_compressed_bpp()
2128 	dsc_max_bpp = min(dsc_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16));  in dsc_compute_compressed_bpp()
2152 	dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915), conn_state->max_requested_bpc);  in is_dsc_pipe_bpp_sufficient()
2155 	dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);  in is_dsc_pipe_bpp_sufficient()
2156 	dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);  in is_dsc_pipe_bpp_sufficient()
2170 	if (!intel_dp->force_dsc_bpc)  in intel_dp_force_dsc_pipe_bpp()
2173 	forced_bpp = intel_dp->force_dsc_bpc * 3;  in intel_dp_force_dsc_pipe_bpp()
2176 		drm_dbg_kms(&i915->drm, "Input DSC BPC forced to %d\n", intel_dp->force_dsc_bpc);  in intel_dp_force_dsc_pipe_bpp()
2180 	drm_dbg_kms(&i915->drm, "Cannot force DSC BPC:%d, due to DSC BPC limits\n",  in intel_dp_force_dsc_pipe_bpp()
2181 		    intel_dp->force_dsc_bpc);  in intel_dp_force_dsc_pipe_bpp()
2194 		to_intel_connector(conn_state->connector);  in intel_dp_dsc_compute_pipe_bpp()
2195 	u8 max_req_bpc = conn_state->max_requested_bpc;  in intel_dp_dsc_compute_pipe_bpp()
2208 			pipe_config->pipe_bpp = forced_bpp;  in intel_dp_dsc_compute_pipe_bpp()
2215 		return -EINVAL;  in intel_dp_dsc_compute_pipe_bpp()
2218 	dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);  in intel_dp_dsc_compute_pipe_bpp()
2221 	dsc_min_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);  in intel_dp_dsc_compute_pipe_bpp()
2227 	num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc);  in intel_dp_dsc_compute_pipe_bpp()
2237 			pipe_config->pipe_bpp = pipe_bpp;  in intel_dp_dsc_compute_pipe_bpp()
2242 	return -EINVAL;  in intel_dp_dsc_compute_pipe_bpp()
2252 		to_intel_connector(conn_state->connector);  in intel_edp_dsc_compute_pipe_bpp()
2262 		int max_bpc = min(limits->pipe.max_bpp / 3, (int)conn_state->max_requested_bpc);  in intel_edp_dsc_compute_pipe_bpp()
2267 			drm_dbg_kms(&i915->drm,  in intel_edp_dsc_compute_pipe_bpp()
2269 			return -EINVAL;  in intel_edp_dsc_compute_pipe_bpp()
2272 	pipe_config->port_clock = limits->max_rate;  in intel_edp_dsc_compute_pipe_bpp()
2273 	pipe_config->lane_count = limits->max_lane_count;  in intel_edp_dsc_compute_pipe_bpp()
2278 	dsc_min_bpp = max(dsc_min_bpp, fxp_q4_to_int_roundup(limits->link.min_bpp_x16));  in intel_edp_dsc_compute_pipe_bpp()
2285 	dsc_max_bpp = min(dsc_max_bpp, fxp_q4_to_int(limits->link.max_bpp_x16));  in intel_edp_dsc_compute_pipe_bpp()
2288 	dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);  in intel_edp_dsc_compute_pipe_bpp()
2290 	pipe_config->dsc.compressed_bpp_x16 =  in intel_edp_dsc_compute_pipe_bpp()
2293 	pipe_config->pipe_bpp = pipe_bpp;  in intel_edp_dsc_compute_pipe_bpp()
2306 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);  in intel_dp_dsc_compute_config()
2308 		to_intel_connector(conn_state->connector);  in intel_dp_dsc_compute_config()
2310 		&pipe_config->hw.adjusted_mode;  in intel_dp_dsc_compute_config()
2313 	pipe_config->fec_enable = pipe_config->fec_enable ||  in intel_dp_dsc_compute_config()
2318 		return -EINVAL;  in intel_dp_dsc_compute_config()
2320 	if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format))  in intel_dp_dsc_compute_config()
2321 		return -EINVAL;  in intel_dp_dsc_compute_config()
2337 			drm_dbg_kms(&dev_priv->drm,  in intel_dp_dsc_compute_config()
2345 		pipe_config->dsc.slice_count =  in intel_dp_dsc_compute_config()
2346 			drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,  in intel_dp_dsc_compute_config()
2348 		if (!pipe_config->dsc.slice_count) {  in intel_dp_dsc_compute_config()
2349 			drm_dbg_kms(&dev_priv->drm, "Unsupported Slice Count %d\n",  in intel_dp_dsc_compute_config()
2350 				    pipe_config->dsc.slice_count);  in intel_dp_dsc_compute_config()
2351 			return -EINVAL;  in intel_dp_dsc_compute_config()
2358 						     adjusted_mode->crtc_clock,  in intel_dp_dsc_compute_config()
2359 						     adjusted_mode->crtc_hdisplay,  in intel_dp_dsc_compute_config()
2360 						     pipe_config->joiner_pipes);  in intel_dp_dsc_compute_config()
2362 			drm_dbg_kms(&dev_priv->drm,  in intel_dp_dsc_compute_config()
2364 			return -EINVAL;  in intel_dp_dsc_compute_config()
2367 		pipe_config->dsc.slice_count = dsc_dp_slice_count;  in intel_dp_dsc_compute_config()
2374 	if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1)  in intel_dp_dsc_compute_config()
2375 		pipe_config->dsc.dsc_split = true;  in intel_dp_dsc_compute_config()
2379 		drm_dbg_kms(&dev_priv->drm,  in intel_dp_dsc_compute_config()
2382 			    pipe_config->pipe_bpp,  in intel_dp_dsc_compute_config()
2383 			    FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16));  in intel_dp_dsc_compute_config()
2387 	pipe_config->dsc.compression_enable = true;  in intel_dp_dsc_compute_config()
2388 	drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "  in intel_dp_dsc_compute_config()
2390 		    pipe_config->pipe_bpp,  in intel_dp_dsc_compute_config()
2391 		    FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),  in intel_dp_dsc_compute_config()
2392 		    pipe_config->dsc.slice_count);  in intel_dp_dsc_compute_config()
2398  * intel_dp_compute_config_link_bpp_limits - compute output link bpp limits
2415 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);  in intel_dp_compute_config_link_bpp_limits()
2417 		&crtc_state->hw.adjusted_mode;  in intel_dp_compute_config_link_bpp_limits()
2418 	const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_dp_compute_config_link_bpp_limits()
2419 	const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in intel_dp_compute_config_link_bpp_limits()
2422 	max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,  in intel_dp_compute_config_link_bpp_limits()
2423 			       fxp_q4_from_int(limits->pipe.max_bpp));  in intel_dp_compute_config_link_bpp_limits()
2428 		if (max_link_bpp_x16 < fxp_q4_from_int(limits->pipe.min_bpp))  in intel_dp_compute_config_link_bpp_limits()
2431 		limits->link.min_bpp_x16 = fxp_q4_from_int(limits->pipe.min_bpp);  in intel_dp_compute_config_link_bpp_limits()
2438 		limits->link.min_bpp_x16 = 0;  in intel_dp_compute_config_link_bpp_limits()
2441 	limits->link.max_bpp_x16 = max_link_bpp_x16;  in intel_dp_compute_config_link_bpp_limits()
2443 	drm_dbg_kms(&i915->drm,  in intel_dp_compute_config_link_bpp_limits()
2445 		    encoder->base.base.id, encoder->base.name,  in intel_dp_compute_config_link_bpp_limits()
2446 		    crtc->base.base.id, crtc->base.name,  in intel_dp_compute_config_link_bpp_limits()
2447 		    adjusted_mode->crtc_clock,  in intel_dp_compute_config_link_bpp_limits()
2449 		    limits->max_lane_count,  in intel_dp_compute_config_link_bpp_limits()
2450 		    limits->max_rate,  in intel_dp_compute_config_link_bpp_limits()
2451 		    limits->pipe.max_bpp,  in intel_dp_compute_config_link_bpp_limits()
2452 		    FXP_Q4_ARGS(limits->link.max_bpp_x16));  in intel_dp_compute_config_link_bpp_limits()
2464 	limits->min_rate = intel_dp_min_link_rate(intel_dp);  in intel_dp_compute_config_limits()
2465 	limits->max_rate = intel_dp_max_link_rate(intel_dp);  in intel_dp_compute_config_limits()
2468 	limits->max_rate = min(limits->max_rate, 810000);  in intel_dp_compute_config_limits()
2469 	limits->min_rate = min(limits->min_rate, limits->max_rate);  in intel_dp_compute_config_limits()
2471 	limits->min_lane_count = intel_dp_min_lane_count(intel_dp);  in intel_dp_compute_config_limits()
2472 	limits->max_lane_count = intel_dp_max_lane_count(intel_dp);  in intel_dp_compute_config_limits()
2474 	limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);  in intel_dp_compute_config_limits()
2475 	limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,  in intel_dp_compute_config_limits()
2478 	if (intel_dp->use_max_params) {  in intel_dp_compute_config_limits()
2487 		limits->min_lane_count = limits->max_lane_count;  in intel_dp_compute_config_limits()
2488 		limits->min_rate = limits->max_rate;  in intel_dp_compute_config_limits()
2502 		&crtc_state->hw.adjusted_mode;  in intel_dp_config_required_rate()
2503 	int bpp = crtc_state->dsc.compression_enable ?  in intel_dp_config_required_rate()
2504 		fxp_q4_to_int_roundup(crtc_state->dsc.compressed_bpp_x16) :  in intel_dp_config_required_rate()
2505 		crtc_state->pipe_bpp;  in intel_dp_config_required_rate()
2507 	return intel_dp_link_required(adjusted_mode->crtc_clock, bpp);  in intel_dp_config_required_rate()
2526 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_dp_compute_link_config()
2527 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);  in intel_dp_compute_link_config()
2529 		to_intel_connector(conn_state->connector);  in intel_dp_compute_link_config()
2531 		&pipe_config->hw.adjusted_mode;  in intel_dp_compute_link_config()
2537 	if (pipe_config->fec_enable &&  in intel_dp_compute_link_config()
2539 		return -EINVAL;  in intel_dp_compute_link_config()
2542 				 adjusted_mode->crtc_hdisplay,  in intel_dp_compute_link_config()
2543 				 adjusted_mode->crtc_clock))  in intel_dp_compute_link_config()
2544 		pipe_config->joiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);  in intel_dp_compute_link_config()
2546 	joiner_needs_dsc = intel_dp_joiner_needs_dsc(i915, pipe_config->joiner_pipes);  in intel_dp_compute_link_config()
2548 	dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||  in intel_dp_compute_link_config()
2566 		drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",  in intel_dp_compute_link_config()
2568 			    str_yes_no(intel_dp->force_dsc_en));  in intel_dp_compute_link_config()
2574 			return -EINVAL;  in intel_dp_compute_link_config()
2582 	drm_dbg_kms(&i915->drm,  in intel_dp_compute_link_config()
2584 		    pipe_config->lane_count, pipe_config->port_clock,  in intel_dp_compute_link_config()
2585 		    pipe_config->pipe_bpp,  in intel_dp_compute_link_config()
2586 		    FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),  in intel_dp_compute_link_config()
2589 						pipe_config->port_clock,  in intel_dp_compute_link_config()
2590 						pipe_config->lane_count));  in intel_dp_compute_link_config()
2601 		&crtc_state->hw.adjusted_mode;  in intel_dp_limited_color_range()
2605 	 * crtc_state->limited_color_range only applies to RGB,  in intel_dp_limited_color_range()
2610 	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)  in intel_dp_limited_color_range()
2613 	if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {  in intel_dp_limited_color_range()
2616 		 * CEA-861-E - 5.1 Default Encoding Parameters  in intel_dp_limited_color_range()
2617 		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry  in intel_dp_limited_color_range()
2619 		return crtc_state->pipe_bpp != 18 &&  in intel_dp_limited_color_range()
2623 		return intel_conn_state->broadcast_rgb ==  in intel_dp_limited_color_range()
2643 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_dp_compute_vsc_colorimetry()
2644 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_dp_compute_vsc_colorimetry()
2646 	if (crtc_state->has_panel_replay) {  in intel_dp_compute_vsc_colorimetry()
2648 		 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223  in intel_dp_compute_vsc_colorimetry()
2652 		vsc->revision = 0x7;  in intel_dp_compute_vsc_colorimetry()
2655 		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118  in intel_dp_compute_vsc_colorimetry()
2659 		vsc->revision = 0x5;  in intel_dp_compute_vsc_colorimetry()
2662 	vsc->length = 0x13;  in intel_dp_compute_vsc_colorimetry()
2664 	/* DP 1.4a spec, Table 2-120 */  in intel_dp_compute_vsc_colorimetry()
2665 	switch (crtc_state->output_format) {  in intel_dp_compute_vsc_colorimetry()
2667 		vsc->pixelformat = DP_PIXELFORMAT_YUV444;  in intel_dp_compute_vsc_colorimetry()
2670 		vsc->pixelformat = DP_PIXELFORMAT_YUV420;  in intel_dp_compute_vsc_colorimetry()
2674 		vsc->pixelformat = DP_PIXELFORMAT_RGB;  in intel_dp_compute_vsc_colorimetry()
2677 	switch (conn_state->colorspace) {  in intel_dp_compute_vsc_colorimetry()
2679 		vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;  in intel_dp_compute_vsc_colorimetry()
2682 		vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;  in intel_dp_compute_vsc_colorimetry()
2685 		vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;  in intel_dp_compute_vsc_colorimetry()
2688 		vsc->colorimetry = DP_COLORIMETRY_SYCC_601;  in intel_dp_compute_vsc_colorimetry()
2691 		vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;  in intel_dp_compute_vsc_colorimetry()
2694 		vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;  in intel_dp_compute_vsc_colorimetry()
2697 		vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;  in intel_dp_compute_vsc_colorimetry()
2700 		vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;  in intel_dp_compute_vsc_colorimetry()
2704 		vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;  in intel_dp_compute_vsc_colorimetry()
2708 		 * RGB->YCBCR color conversion uses the BT.709  in intel_dp_compute_vsc_colorimetry()
2711 		if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)  in intel_dp_compute_vsc_colorimetry()
2712 			vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;  in intel_dp_compute_vsc_colorimetry()
2714 			vsc->colorimetry = DP_COLORIMETRY_DEFAULT;  in intel_dp_compute_vsc_colorimetry()
2718 	vsc->bpc = crtc_state->pipe_bpp / 3;  in intel_dp_compute_vsc_colorimetry()
2721 	drm_WARN_ON(&dev_priv->drm,  in intel_dp_compute_vsc_colorimetry()
2722 		    vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);  in intel_dp_compute_vsc_colorimetry()
2725 	vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;  in intel_dp_compute_vsc_colorimetry()
2726 	vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;  in intel_dp_compute_vsc_colorimetry()
2732 	struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;  in intel_dp_compute_as_sdp()
2734 		&crtc_state->hw.adjusted_mode;  in intel_dp_compute_as_sdp()
2736 	if (!crtc_state->vrr.enable || !intel_dp->as_sdp_supported)  in intel_dp_compute_as_sdp()
2739 	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);  in intel_dp_compute_as_sdp()
2742 	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;  in intel_dp_compute_as_sdp()
2743 	as_sdp->length = 0x9;  in intel_dp_compute_as_sdp()
2744 	as_sdp->duration_incr_ms = 0;  in intel_dp_compute_as_sdp()
2745 	as_sdp->duration_incr_ms = 0;  in intel_dp_compute_as_sdp()
2747 	if (crtc_state->cmrr.enable) {  in intel_dp_compute_as_sdp()
2748 		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;  in intel_dp_compute_as_sdp()
2749 		as_sdp->vtotal = adjusted_mode->vtotal;  in intel_dp_compute_as_sdp()
2750 		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);  in intel_dp_compute_as_sdp()
2751 		as_sdp->target_rr_divider = true;  in intel_dp_compute_as_sdp()
2753 		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;  in intel_dp_compute_as_sdp()
2754 		as_sdp->vtotal = adjusted_mode->vtotal;  in intel_dp_compute_as_sdp()
2755 		as_sdp->target_rr = 0;  in intel_dp_compute_as_sdp()
2765 	if ((!intel_dp->colorimetry_support ||  in intel_dp_compute_vsc_sdp()
2767 	    !crtc_state->has_psr)  in intel_dp_compute_vsc_sdp()
2770 	vsc = &crtc_state->infoframes.vsc;  in intel_dp_compute_vsc_sdp()
2772 	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);  in intel_dp_compute_vsc_sdp()
2773 	vsc->sdp_type = DP_SDP_VSC;  in intel_dp_compute_vsc_sdp()
2779 	} else if (crtc_state->has_panel_replay) {  in intel_dp_compute_vsc_sdp()
2782 		 * Prepare VSC Header for SU as per DP 2.0 spec, Table 2-223  in intel_dp_compute_vsc_sdp()
2785 		vsc->revision = 0x6;  in intel_dp_compute_vsc_sdp()
2786 		vsc->length = 0x10;  in intel_dp_compute_vsc_sdp()
2787 	} else if (crtc_state->has_sel_update) {  in intel_dp_compute_vsc_sdp()
2790 		 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11  in intel_dp_compute_vsc_sdp()
2791 		 * 3D stereo + PSR/PSR2 + Y-coordinate.  in intel_dp_compute_vsc_sdp()
2793 		vsc->revision = 0x4;  in intel_dp_compute_vsc_sdp()
2794 		vsc->length = 0xe;  in intel_dp_compute_vsc_sdp()
2798 		 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118  in intel_dp_compute_vsc_sdp()
2802 		vsc->revision = 0x2;  in intel_dp_compute_vsc_sdp()
2803 		vsc->length = 0x8;  in intel_dp_compute_vsc_sdp()
2814 	struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;  in intel_dp_compute_hdr_metadata_infoframe_sdp()
2816 	if (!conn_state->hdr_output_metadata)  in intel_dp_compute_hdr_metadata_infoframe_sdp()
2822 		drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");  in intel_dp_compute_hdr_metadata_infoframe_sdp()
2826 	crtc_state->infoframes.enable |=  in intel_dp_compute_hdr_metadata_infoframe_sdp()
2834 	struct drm_i915_private *i915 = to_i915(connector->base.dev);  in can_enable_drrs()
2836 	if (pipe_config->vrr.enable)  in can_enable_drrs()
2841 	 * as it allows more power-savings by complete shutting down display,  in can_enable_drrs()
2845 	if (pipe_config->has_psr)  in can_enable_drrs()
2849 	if (pipe_config->has_pch_encoder)  in can_enable_drrs()
2852 	if (!intel_cpu_transcoder_has_drrs(i915, pipe_config->cpu_transcoder))  in can_enable_drrs()
2864 	struct drm_i915_private *i915 = to_i915(connector->base.dev);  in intel_dp_drrs_compute_config()
2866 		intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);  in intel_dp_drrs_compute_config()
2873 	if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes)  in intel_dp_drrs_compute_config()
2874 		pipe_config->update_m_n = true;  in intel_dp_drrs_compute_config()
2877 		if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder))  in intel_dp_drrs_compute_config()
2878 			intel_zero_m_n(&pipe_config->dp_m2_n2);  in intel_dp_drrs_compute_config()
2883 		pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;  in intel_dp_drrs_compute_config()
2885 	pipe_config->has_drrs = true;  in intel_dp_drrs_compute_config()
2887 	pixel_clock = downclock_mode->clock;  in intel_dp_drrs_compute_config()
2888 	if (pipe_config->splitter.enable)  in intel_dp_drrs_compute_config()
2889 		pixel_clock /= pipe_config->splitter.link_count;  in intel_dp_drrs_compute_config()
2891 	intel_link_compute_m_n(link_bpp_x16, pipe_config->lane_count, pixel_clock,  in intel_dp_drrs_compute_config()
2892 			       pipe_config->port_clock,  in intel_dp_drrs_compute_config()
2893 			       intel_dp_bw_fec_overhead(pipe_config->fec_enable),  in intel_dp_drrs_compute_config()
2894 			       &pipe_config->dp_m2_n2);  in intel_dp_drrs_compute_config()
2897 	if (pipe_config->splitter.enable)  in intel_dp_drrs_compute_config()
2898 		pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count;  in intel_dp_drrs_compute_config()
2904 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_dp_has_audio()
2908 		to_intel_connector(conn_state->connector);  in intel_dp_has_audio()
2910 	if (!intel_dp_port_has_audio(i915, encoder->port))  in intel_dp_has_audio()
2913 	if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)  in intel_dp_has_audio()
2914 		return connector->base.display_info.has_audio;  in intel_dp_has_audio()
2916 		return intel_conn_state->force_audio == HDMI_AUDIO_ON;  in intel_dp_has_audio()
2925 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_dp_compute_output_format()
2927 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_compute_output_format()
2928 	const struct drm_display_info *info = &connector->base.display_info;  in intel_dp_compute_output_format()
2929 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_dp_compute_output_format()
2935 	if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {  in intel_dp_compute_output_format()
2936 		drm_dbg_kms(&i915->drm,  in intel_dp_compute_output_format()
2938 		crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;  in intel_dp_compute_output_format()
2940 		crtc_state->sink_format = intel_dp_sink_format(connector, adjusted_mode);  in intel_dp_compute_output_format()
2943 	crtc_state->output_format = intel_dp_output_format(connector, crtc_state->sink_format);  in intel_dp_compute_output_format()
2948 		if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||  in intel_dp_compute_output_format()
2949 		    !connector->base.ycbcr_420_allowed ||  in intel_dp_compute_output_format()
2953 		crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;  in intel_dp_compute_output_format()
2954 		crtc_state->output_format = intel_dp_output_format(connector,  in intel_dp_compute_output_format()
2955 								   crtc_state->sink_format);  in intel_dp_compute_output_format()
2968 	pipe_config->has_audio =  in intel_dp_audio_compute_config()
2972 	pipe_config->sdp_split_enable = pipe_config->has_audio &&  in intel_dp_audio_compute_config()
2978 	struct drm_i915_private *i915 = to_i915(connector->base.dev);  in intel_dp_queue_modeset_retry_work()
2980 	drm_connector_get(&connector->base);  in intel_dp_queue_modeset_retry_work()
2981 	if (!queue_work(i915->unordered_wq, &connector->modeset_retry_work))  in intel_dp_queue_modeset_retry_work()
2982 		drm_connector_put(&connector->base);  in intel_dp_queue_modeset_retry_work()
2995 	if (intel_dp->needs_modeset_retry)  in intel_dp_queue_modeset_retry_for_link()
2998 	intel_dp->needs_modeset_retry = true;  in intel_dp_queue_modeset_retry_for_link()
3001 		intel_dp_queue_modeset_retry_work(intel_dp->attached_connector);  in intel_dp_queue_modeset_retry_for_link()
3007 		if (!conn_state->base.crtc)  in intel_dp_queue_modeset_retry_for_link()
3010 		if (connector->mst_port == intel_dp)  in intel_dp_queue_modeset_retry_for_link()
3020 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_dp_compute_config()
3021 	struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);  in intel_dp_compute_config()
3022 	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;  in intel_dp_compute_config()
3025 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_compute_config()
3028 	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A)  in intel_dp_compute_config()
3029 		pipe_config->has_pch_encoder = true;  in intel_dp_compute_config()
3038 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)  in intel_dp_compute_config()
3039 		return -EINVAL;  in intel_dp_compute_config()
3041 	if (!connector->base.interlace_allowed &&  in intel_dp_compute_config()
3042 	    adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)  in intel_dp_compute_config()
3043 		return -EINVAL;  in intel_dp_compute_config()
3045 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)  in intel_dp_compute_config()
3046 		return -EINVAL;  in intel_dp_compute_config()
3048 	if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))  in intel_dp_compute_config()
3049 		return -EINVAL;  in intel_dp_compute_config()
3062 	    pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {  in intel_dp_compute_config()
3068 	pipe_config->limited_color_range =  in intel_dp_compute_config()
3071 	pipe_config->enhanced_framing =  in intel_dp_compute_config()
3072 		drm_dp_enhanced_frame_cap(intel_dp->dpcd);  in intel_dp_compute_config()
3074 	if (pipe_config->dsc.compression_enable)  in intel_dp_compute_config()
3075 		link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;  in intel_dp_compute_config()
3077 		link_bpp_x16 = fxp_q4_from_int(intel_dp_output_bpp(pipe_config->output_format,  in intel_dp_compute_config()
3078 								   pipe_config->pipe_bpp));  in intel_dp_compute_config()
3080 	if (intel_dp->mso_link_count) {  in intel_dp_compute_config()
3081 		int n = intel_dp->mso_link_count;  in intel_dp_compute_config()
3082 		int overlap = intel_dp->mso_pixel_overlap;  in intel_dp_compute_config()
3084 		pipe_config->splitter.enable = true;  in intel_dp_compute_config()
3085 		pipe_config->splitter.link_count = n;  in intel_dp_compute_config()
3086 		pipe_config->splitter.pixel_overlap = overlap;  in intel_dp_compute_config()
3088 		drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n",  in intel_dp_compute_config()
3091 		adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;  in intel_dp_compute_config()
3092 		adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap;  in intel_dp_compute_config()
3093 		adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap;  in intel_dp_compute_config()
3094 		adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap;  in intel_dp_compute_config()
3095 		adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap;  in intel_dp_compute_config()
3096 		adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap;  in intel_dp_compute_config()
3097 		adjusted_mode->crtc_clock /= n;  in intel_dp_compute_config()
3103 			       pipe_config->lane_count,  in intel_dp_compute_config()
3104 			       adjusted_mode->crtc_clock,  in intel_dp_compute_config()
3105 			       pipe_config->port_clock,  in intel_dp_compute_config()
3106 			       intel_dp_bw_fec_overhead(pipe_config->fec_enable),  in intel_dp_compute_config()
3107 			       &pipe_config->dp_m_n);  in intel_dp_compute_config()
3110 	if (pipe_config->splitter.enable)  in intel_dp_compute_config()
3111 		pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;  in intel_dp_compute_config()
3131 	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));  in intel_dp_set_link_params()
3132 	intel_dp->link_trained = false;  in intel_dp_set_link_params()
3133 	intel_dp->needs_modeset_retry = false;  in intel_dp_set_link_params()
3134 	intel_dp->link_rate = link_rate;  in intel_dp_set_link_params()
3135 	intel_dp->lane_count = lane_count;  in intel_dp_set_link_params()
3140 	intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp);  in intel_dp_reset_link_params()
3141 	intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp);  in intel_dp_reset_link_params()
3142 	intel_dp->link.mst_probed_lane_count = 0;  in intel_dp_reset_link_params()
3143 	intel_dp->link.mst_probed_rate = 0;  in intel_dp_reset_link_params()
3144 	intel_dp->link.retrain_disabled = false;  in intel_dp_reset_link_params()
3145 	intel_dp->link.seq_train_failures = 0;  in intel_dp_reset_link_params()
3152 	struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));  in intel_edp_backlight_on()
3158 	drm_dbg_kms(&i915->drm, "\n");  in intel_edp_backlight_on()
3167 	struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));  in intel_edp_backlight_off()
3173 	drm_dbg_kms(&i915->drm, "\n");  in intel_edp_backlight_off()
3189 	return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&  in downstream_hpd_needs_d0()
3190 		drm_dp_is_branch(intel_dp->dpcd) &&  in downstream_hpd_needs_d0()
3191 		intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;  in downstream_hpd_needs_d0()
3216 	struct drm_i915_private *i915 = to_i915(connector->base.dev);  in intel_dp_sink_set_dsc_decompression()
3218 	if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux,  in intel_dp_sink_set_dsc_decompression()
3220 		drm_dbg_kms(&i915->drm,  in intel_dp_sink_set_dsc_decompression()
3229 	struct drm_i915_private *i915 = to_i915(connector->base.dev);  in intel_dp_sink_set_dsc_passthrough()
3230 	struct drm_dp_aux *aux = connector->port ?  in intel_dp_sink_set_dsc_passthrough()
3231 				 connector->port->passthrough_aux : NULL;  in intel_dp_sink_set_dsc_passthrough()
3238 		drm_dbg_kms(&i915->drm,  in intel_dp_sink_set_dsc_passthrough()
3247 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_dp_dsc_aux_ref_count()
3258 	if (!connector->mst_port)  in intel_dp_dsc_aux_ref_count()
3259 		return connector->dp.dsc_decompression_enabled ? 1 : 0;  in intel_dp_dsc_aux_ref_count()
3261 	for_each_oldnew_connector_in_state(&state->base, _connector_iter,  in intel_dp_dsc_aux_ref_count()
3266 		if (connector_iter->mst_port != connector->mst_port)  in intel_dp_dsc_aux_ref_count()
3269 		if (!connector_iter->dp.dsc_decompression_enabled)  in intel_dp_dsc_aux_ref_count()
3272 		drm_WARN_ON(&i915->drm,  in intel_dp_dsc_aux_ref_count()
3273 			    (for_get_ref && !new_conn_state->crtc) ||  in intel_dp_dsc_aux_ref_count()
3274 			    (!for_get_ref && !old_conn_state->crtc));  in intel_dp_dsc_aux_ref_count()
3276 		if (connector_iter->dp.dsc_decompression_aux ==  in intel_dp_dsc_aux_ref_count()
3277 		    connector->dp.dsc_decompression_aux)  in intel_dp_dsc_aux_ref_count()
3289 	connector->dp.dsc_decompression_enabled = true;  in intel_dp_dsc_aux_get_ref()
3297 	connector->dp.dsc_decompression_enabled = false;  in intel_dp_dsc_aux_put_ref()
3303  * intel_dp_sink_enable_decompression - Enable DSC decompression in sink/last branch device
3319 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_dp_sink_enable_decompression()
3321 	if (!new_crtc_state->dsc.compression_enable)  in intel_dp_sink_enable_decompression()
3324 	if (drm_WARN_ON(&i915->drm,  in intel_dp_sink_enable_decompression()
3325 			!connector->dp.dsc_decompression_aux ||  in intel_dp_sink_enable_decompression()
3326 			connector->dp.dsc_decompression_enabled))  in intel_dp_sink_enable_decompression()
3337  * intel_dp_sink_disable_decompression - Disable DSC decompression in sink/last branch device
3350 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_dp_sink_disable_decompression()
3352 	if (!old_crtc_state->dsc.compression_enable)  in intel_dp_sink_disable_decompression()
3355 	if (drm_WARN_ON(&i915->drm,  in intel_dp_sink_disable_decompression()
3356 			!connector->dp.dsc_decompression_aux ||  in intel_dp_sink_disable_decompression()
3357 			!connector->dp.dsc_decompression_enabled))  in intel_dp_sink_disable_decompression()
3379 		if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)  in intel_edp_init_source_oui()
3380 			drm_err(&i915->drm, "Failed to read source OUI\n");  in intel_edp_init_source_oui()
3386 	if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)  in intel_edp_init_source_oui()
3387 		drm_err(&i915->drm, "Failed to write source OUI\n");  in intel_edp_init_source_oui()
3389 	intel_dp->last_oui_write = jiffies;  in intel_edp_init_source_oui()
3394 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_wait_source_oui()
3397 	drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Performing OUI wait (%u ms)\n",  in intel_dp_wait_source_oui()
3398 		    connector->base.base.id, connector->base.name,  in intel_dp_wait_source_oui()
3399 		    connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);  in intel_dp_wait_source_oui()
3401 	wait_remaining_ms_from_jiffies(intel_dp->last_oui_write,  in intel_dp_wait_source_oui()
3402 				       connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);  in intel_dp_wait_source_oui()
3408 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in intel_dp_set_power()
3409 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_dp_set_power()
3413 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)  in intel_dp_set_power()
3420 		ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);  in intel_dp_set_power()
3435 			ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);  in intel_dp_set_power()
3441 		if (ret == 1 && lspcon->active)  in intel_dp_set_power()
3446 		drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",  in intel_dp_set_power()
3447 			    encoder->base.base.id, encoder->base.name,  in intel_dp_set_power()
3455  * intel_dp_sync_state - sync the encoder state during init/resume
3472 	if (crtc_state && intel_dp->dpcd[DP_DPCD_REV] == 0) {  in intel_dp_sync_state()
3481 		intel_dp_set_link_params(intel_dp, crtc_state->port_clock, crtc_state->lane_count);  in intel_dp_sync_state()
3482 		intel_dp->link_trained = true;  in intel_dp_sync_state()
3489 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_dp_initial_fastset_check()
3494 	 * If BIOS has set an unsupported or non-standard link rate for some  in intel_dp_initial_fastset_check()
3497 	if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,  in intel_dp_initial_fastset_check()
3498 				crtc_state->port_clock) < 0) {  in intel_dp_initial_fastset_check()
3499 		drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to unsupported link rate\n",  in intel_dp_initial_fastset_check()
3500 			    encoder->base.base.id, encoder->base.name);  in intel_dp_initial_fastset_check()
3501 		crtc_state->uapi.connectors_changed = true;  in intel_dp_initial_fastset_check()
3509 	 * of crtc_state->dsc, we have no way to ensure reliable fastset.  in intel_dp_initial_fastset_check()
3512 	if (crtc_state->dsc.compression_enable) {  in intel_dp_initial_fastset_check()
3513 		drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to DSC being enabled\n",  in intel_dp_initial_fastset_check()
3514 			    encoder->base.base.id, encoder->base.name);  in intel_dp_initial_fastset_check()
3515 		crtc_state->uapi.mode_changed = true;  in intel_dp_initial_fastset_check()
3520 		drm_dbg_kms(&i915->drm,  in intel_dp_initial_fastset_check()
3522 			    encoder->base.base.id, encoder->base.name);  in intel_dp_initial_fastset_check()
3523 		crtc_state->uapi.mode_changed = true;  in intel_dp_initial_fastset_check()
3536 	memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd));  in intel_dp_get_pcon_dsc_cap()
3538 	if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,  in intel_dp_get_pcon_dsc_cap()
3539 			     intel_dp->pcon_dsc_dpcd,  in intel_dp_get_pcon_dsc_cap()
3540 			     sizeof(intel_dp->pcon_dsc_dpcd)) < 0)  in intel_dp_get_pcon_dsc_cap()
3541 		drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n",  in intel_dp_get_pcon_dsc_cap()
3544 	drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n",  in intel_dp_get_pcon_dsc_cap()
3545 		    (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);  in intel_dp_get_pcon_dsc_cap()
3550 	static const int bw_gbps[] = {9, 18, 24, 32, 40, 48};  in intel_dp_pcon_get_frl_mask()
3553 	for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) {  in intel_dp_pcon_get_frl_mask()
3573 	case 9:  in intel_dp_pcon_set_frl_mask()
3582 	struct intel_connector *intel_connector = intel_dp->attached_connector;  in intel_dp_hdmi_sink_max_frl()
3583 	struct drm_connector *connector = &intel_connector->base;  in intel_dp_hdmi_sink_max_frl()
3588 	max_lanes = connector->display_info.hdmi.max_lanes;  in intel_dp_hdmi_sink_max_frl()
3589 	rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane;  in intel_dp_hdmi_sink_max_frl()
3592 	if (connector->display_info.hdmi.dsc_cap.v_1p2) {  in intel_dp_hdmi_sink_max_frl()
3593 		max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes;  in intel_dp_hdmi_sink_max_frl()
3594 		dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane;  in intel_dp_hdmi_sink_max_frl()
3606 	if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&  in intel_dp_pcon_is_frl_trained()
3607 	    drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) == DP_PCON_HDMI_MODE_FRL &&  in intel_dp_pcon_is_frl_trained()
3624 	max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;  in intel_dp_pcon_start_frl_training()
3625 	drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);  in intel_dp_pcon_start_frl_training()
3628 	drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw);  in intel_dp_pcon_start_frl_training()
3633 		return -EINVAL;  in intel_dp_pcon_start_frl_training()
3636 	drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);  in intel_dp_pcon_start_frl_training()
3641 	ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);  in intel_dp_pcon_start_frl_training()
3645 	wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS);  in intel_dp_pcon_start_frl_training()
3648 		return -ETIMEDOUT;  in intel_dp_pcon_start_frl_training()
3650 	ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,  in intel_dp_pcon_start_frl_training()
3654 	ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask,  in intel_dp_pcon_start_frl_training()
3658 	ret = drm_dp_pcon_frl_enable(&intel_dp->aux);  in intel_dp_pcon_start_frl_training()
3670 		return -ETIMEDOUT;  in intel_dp_pcon_start_frl_training()
3673 	drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);  in intel_dp_pcon_start_frl_training()
3674 	intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);  in intel_dp_pcon_start_frl_training()
3675 	intel_dp->frl.is_trained = true;  in intel_dp_pcon_start_frl_training()
3676 	drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps);  in intel_dp_pcon_start_frl_training()
3683 	if (drm_dp_is_branch(intel_dp->dpcd) &&  in intel_dp_is_hdmi_2_1_sink()
3700 	ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);  in intel_dp_pcon_set_tmds_mode()
3706 	ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);  in intel_dp_pcon_set_tmds_mode()
3719 	 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7)  in intel_dp_check_frl_training()
3720 	 * -sink is HDMI2.1  in intel_dp_check_frl_training()
3722 	if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) ||  in intel_dp_check_frl_training()
3724 	    intel_dp->frl.is_trained)  in intel_dp_check_frl_training()
3730 		drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n");  in intel_dp_check_frl_training()
3732 		mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);  in intel_dp_check_frl_training()
3735 			drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n");  in intel_dp_check_frl_training()
3737 		drm_dbg(&dev_priv->drm, "FRL training Completed\n");  in intel_dp_check_frl_training()
3744 	int vactive = crtc_state->hw.adjusted_mode.vdisplay;  in intel_dp_pcon_dsc_enc_slice_height()
3753 	struct intel_connector *intel_connector = intel_dp->attached_connector;  in intel_dp_pcon_dsc_enc_slices()
3754 	struct drm_connector *connector = &intel_connector->base;  in intel_dp_pcon_dsc_enc_slices()
3755 	int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice;  in intel_dp_pcon_dsc_enc_slices()
3756 	int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices;  in intel_dp_pcon_dsc_enc_slices()
3757 	int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);  in intel_dp_pcon_dsc_enc_slices()
3758 	int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);  in intel_dp_pcon_dsc_enc_slices()
3770 	struct intel_connector *intel_connector = intel_dp->attached_connector;  in intel_dp_pcon_dsc_enc_bpp()
3771 	struct drm_connector *connector = &intel_connector->base;  in intel_dp_pcon_dsc_enc_bpp()
3772 	int output_format = crtc_state->output_format;  in intel_dp_pcon_dsc_enc_bpp()
3773 	bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp;  in intel_dp_pcon_dsc_enc_bpp()
3774 	int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);  in intel_dp_pcon_dsc_enc_bpp()
3776 		connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024;  in intel_dp_pcon_dsc_enc_bpp()
3793 	struct intel_connector *intel_connector = intel_dp->attached_connector;  in intel_dp_pcon_dsc_configure()
3803 	connector = &intel_connector->base;  in intel_dp_pcon_dsc_configure()
3804 	hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2;  in intel_dp_pcon_dsc_configure()
3806 	if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||  in intel_dp_pcon_dsc_configure()
3818 	slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay,  in intel_dp_pcon_dsc_configure()
3833 	ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);  in intel_dp_pcon_dsc_configure()
3835 		drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n");  in intel_dp_pcon_dsc_configure()
3846 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)  in intel_dp_configure_protocol_converter()
3849 	if (!drm_dp_is_branch(intel_dp->dpcd))  in intel_dp_configure_protocol_converter()
3854 	if (drm_dp_dpcd_writeb(&intel_dp->aux,  in intel_dp_configure_protocol_converter()
3856 		drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n",  in intel_dp_configure_protocol_converter()
3859 	if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {  in intel_dp_configure_protocol_converter()
3860 		switch (crtc_state->output_format) {  in intel_dp_configure_protocol_converter()
3871 			MISSING_CASE(crtc_state->output_format);  in intel_dp_configure_protocol_converter()
3874 	} else if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR444) {  in intel_dp_configure_protocol_converter()
3875 		switch (crtc_state->output_format) {  in intel_dp_configure_protocol_converter()
3882 			MISSING_CASE(crtc_state->output_format);  in intel_dp_configure_protocol_converter()
3889 	if (drm_dp_dpcd_writeb(&intel_dp->aux,  in intel_dp_configure_protocol_converter()
3891 		drm_dbg_kms(&i915->drm,  in intel_dp_configure_protocol_converter()
3893 			    str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));  in intel_dp_configure_protocol_converter()
3897 	if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)  in intel_dp_configure_protocol_converter()
3898 		drm_dbg_kms(&i915->drm,  in intel_dp_configure_protocol_converter()
3899 			    "Failed to %s protocol converter RGB->YCbCr conversion mode\n",  in intel_dp_configure_protocol_converter()
3907 	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,  in intel_dp_get_colorimetry_status()
3918 		drm_err(aux->drm_dev,  in intel_dp_read_dsc_dpcd()
3924 	drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n",  in intel_dp_read_dsc_dpcd()
3931 	struct drm_i915_private *i915 = to_i915(connector->base.dev);  in intel_dp_get_dsc_sink_cap()
3937 	memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd));  in intel_dp_get_dsc_sink_cap()
3940 	connector->dp.fec_capability = 0;  in intel_dp_get_dsc_sink_cap()
3945 	intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux,  in intel_dp_get_dsc_sink_cap()
3946 			       connector->dp.dsc_dpcd);  in intel_dp_get_dsc_sink_cap()
3948 	if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY,  in intel_dp_get_dsc_sink_cap()
3949 			      &connector->dp.fec_capability) < 0) {  in intel_dp_get_dsc_sink_cap()
3950 		drm_err(&i915->drm, "Failed to read FEC DPCD register\n");  in intel_dp_get_dsc_sink_cap()
3954 	drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",  in intel_dp_get_dsc_sink_cap()
3955 		    connector->dp.fec_capability);  in intel_dp_get_dsc_sink_cap()
3963 	intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd);  in intel_edp_get_dsc_sink_cap()
3970 	struct drm_i915_private *i915 = to_i915(connector->base.dev);  in intel_edp_mso_mode_fixup()
3971 	int n = intel_dp->mso_link_count;  in intel_edp_mso_mode_fixup()
3972 	int overlap = intel_dp->mso_pixel_overlap;  in intel_edp_mso_mode_fixup()
3977 	mode->hdisplay = (mode->hdisplay - overlap) * n;  in intel_edp_mso_mode_fixup()
3978 	mode->hsync_start = (mode->hsync_start - overlap) * n;  in intel_edp_mso_mode_fixup()
3979 	mode->hsync_end = (mode->hsync_end - overlap) * n;  in intel_edp_mso_mode_fixup()
3980 	mode->htotal = (mode->htotal - overlap) * n;  in intel_edp_mso_mode_fixup()
3981 	mode->clock *= n;  in intel_edp_mso_mode_fixup()
3985 	drm_dbg_kms(&i915->drm,  in intel_edp_mso_mode_fixup()
3987 		    connector->base.base.id, connector->base.name,  in intel_edp_mso_mode_fixup()
3993 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_edp_fixup_vbt_bpp()
3995 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_edp_fixup_vbt_bpp()
3997 	if (connector->panel.vbt.edp.bpp && pipe_bpp > connector->panel.vbt.edp.bpp) {  in intel_edp_fixup_vbt_bpp()
4011 		drm_dbg_kms(&dev_priv->drm,  in intel_edp_fixup_vbt_bpp()
4012 			    "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",  in intel_edp_fixup_vbt_bpp()
4013 			    pipe_bpp, connector->panel.vbt.edp.bpp);  in intel_edp_fixup_vbt_bpp()
4014 		connector->panel.vbt.edp.bpp = pipe_bpp;  in intel_edp_fixup_vbt_bpp()
4021 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_edp_mso_init()
4022 	struct drm_display_info *info = &connector->base.display_info;  in intel_edp_mso_init()
4025 	if (intel_dp->edp_dpcd[0] < DP_EDP_14)  in intel_edp_mso_init()
4028 	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {  in intel_edp_mso_init()
4029 		drm_err(&i915->drm, "Failed to read MSO cap\n");  in intel_edp_mso_init()
4035 	if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {  in intel_edp_mso_init()
4036 		drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso);  in intel_edp_mso_init()
4041 		drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration, pixel overlap %u\n",  in intel_edp_mso_init()
4042 			    mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,  in intel_edp_mso_init()
4043 			    info->mso_pixel_overlap);  in intel_edp_mso_init()
4045 			drm_err(&i915->drm, "No source MSO support, disabling\n");  in intel_edp_mso_init()
4050 	intel_dp->mso_link_count = mso;  in intel_edp_mso_init()
4051 	intel_dp->mso_pixel_overlap = mso ? info->mso_pixel_overlap : 0;  in intel_edp_mso_init()
4058 		to_i915(dp_to_dig_port(intel_dp)->base.base.dev);  in intel_edp_init_dpcd()
4061 	drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);  in intel_edp_init_dpcd()
4063 	if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)  in intel_edp_init_dpcd()
4066 	drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,  in intel_edp_init_dpcd()
4067 			 drm_dp_is_branch(intel_dp->dpcd));  in intel_edp_init_dpcd()
4068 	intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident);  in intel_edp_init_dpcd()
4070 	intel_dp->colorimetry_support =  in intel_edp_init_dpcd()
4082 	if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,  in intel_edp_init_dpcd()
4083 			     intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==  in intel_edp_init_dpcd()
4084 			     sizeof(intel_dp->edp_dpcd)) {  in intel_edp_init_dpcd()
4085 		drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",  in intel_edp_init_dpcd()
4086 			    (int)sizeof(intel_dp->edp_dpcd),  in intel_edp_init_dpcd()
4087 			    intel_dp->edp_dpcd);  in intel_edp_init_dpcd()
4089 		intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14;  in intel_edp_init_dpcd()
4093 	 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks  in intel_edp_init_dpcd()
4094 	 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]  in intel_edp_init_dpcd()
4099 	intel_dp->num_sink_rates = 0;  in intel_edp_init_dpcd()
4102 	if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {  in intel_edp_init_dpcd()
4106 		drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,  in intel_edp_init_dpcd()
4115 			/* Value read multiplied by 200kHz gives the per-lane  in intel_edp_init_dpcd()
4121 			intel_dp->sink_rates[i] = (val * 200) / 10;  in intel_edp_init_dpcd()
4123 		intel_dp->num_sink_rates = i;  in intel_edp_init_dpcd()
4130 	if (intel_dp->num_sink_rates)  in intel_edp_init_dpcd()
4131 		intel_dp->use_rate_select = true;  in intel_edp_init_dpcd()
4138 		intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],  in intel_edp_init_dpcd()
4142 	 * If needed, program our source OUI so we can make various Intel-specific AUX services  in intel_edp_init_dpcd()
4153 	if (!intel_dp->attached_connector)  in intel_dp_has_sink_count()
4156 	return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,  in intel_dp_has_sink_count()
4157 					  intel_dp->dpcd,  in intel_dp_has_sink_count()
4158 					  &intel_dp->desc);  in intel_dp_has_sink_count()
4177 	 * Don't clobber cached eDP rates. Also skip re-reading  in intel_dp_get_dpcd()
4181 		drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,  in intel_dp_get_dpcd()
4182 				 drm_dp_is_branch(intel_dp->dpcd));  in intel_dp_get_dpcd()
4184 		intel_init_dpcd_quirks(intel_dp, &intel_dp->desc.ident);  in intel_dp_get_dpcd()
4186 		intel_dp->colorimetry_support =  in intel_dp_get_dpcd()
4193 		ret = drm_dp_read_sink_count(&intel_dp->aux);  in intel_dp_get_dpcd()
4202 		intel_dp->sink_count = ret;  in intel_dp_get_dpcd()
4211 		if (!intel_dp->sink_count)  in intel_dp_get_dpcd()
4215 	return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,  in intel_dp_get_dpcd()
4216 					   intel_dp->downstream_ports) == 0;  in intel_dp_get_dpcd()
4235 	if (!i915->display.params.enable_dp_mst)  in intel_dp_mst_mode_choose()
4242 	    !(intel_dp->dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_128B132B))  in intel_dp_mst_mode_choose()
4252 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in intel_dp_mst_detect()
4256 	sink_mst_mode = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);  in intel_dp_mst_detect()
4260 	drm_dbg_kms(&i915->drm,  in intel_dp_mst_detect()
4261 		    "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s -> enable: %s\n",  in intel_dp_mst_detect()
4262 		    encoder->base.base.id, encoder->base.name,  in intel_dp_mst_detect()
4265 		    str_yes_no(i915->display.params.enable_dp_mst),  in intel_dp_mst_detect()
4277 	intel_dp->is_mst = intel_dp->mst_detect != DRM_DP_SST;  in intel_dp_mst_configure()
4279 	if (intel_dp->is_mst)  in intel_dp_mst_configure()
4282 	drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);  in intel_dp_mst_configure()
4285 	intel_dp->mst_detect = DRM_DP_SST;  in intel_dp_mst_configure()
4293 	if (!intel_dp->is_mst)  in intel_dp_mst_disconnect()
4296 	drm_dbg_kms(&i915->drm, "MST device may have disappeared %d vs %d\n",  in intel_dp_mst_disconnect()
4297 		    intel_dp->is_mst, intel_dp->mst_mgr.mst_state);  in intel_dp_mst_disconnect()
4298 	intel_dp->is_mst = false;  in intel_dp_mst_disconnect()
4299 	drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);  in intel_dp_mst_disconnect()
4305 	return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, esi, 4) == 4;  in intel_dp_get_sink_irq_esi()
4313 		if (drm_dp_dpcd_write(&intel_dp->aux, DP_SINK_COUNT_ESI + 1,  in intel_dp_ack_sink_irq_esi()
4330 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)  in intel_dp_needs_vsc_sdp()
4333 	switch (conn_state->colorspace) {  in intel_dp_needs_vsc_sdp()
4353 		return -ENOSPC;  in intel_dp_as_sdp_pack()
4358 	sdp->sdp_header.HB0 = 0;  in intel_dp_as_sdp_pack()
4359 	sdp->sdp_header.HB1 = as_sdp->sdp_type;  in intel_dp_as_sdp_pack()
4360 	sdp->sdp_header.HB2 = 0x02;  in intel_dp_as_sdp_pack()
4361 	sdp->sdp_header.HB3 = as_sdp->length;  in intel_dp_as_sdp_pack()
4364 	sdp->db[0] = as_sdp->mode;  in intel_dp_as_sdp_pack()
4365 	sdp->db[1] = as_sdp->vtotal & 0xFF;  in intel_dp_as_sdp_pack()
4366 	sdp->db[2] = (as_sdp->vtotal >> 8) & 0xFF;  in intel_dp_as_sdp_pack()
4367 	sdp->db[3] = as_sdp->target_rr & 0xFF;  in intel_dp_as_sdp_pack()
4368 	sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3;  in intel_dp_as_sdp_pack()
4370 	if (as_sdp->target_rr_divider)  in intel_dp_as_sdp_pack()
4371 		sdp->db[4] |= 0x20;  in intel_dp_as_sdp_pack()
4388 		return -ENOSPC;  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4394 		drm_dbg_kms(&i915->drm, "buffer size is smaller than hdr metadata infoframe\n");  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4395 		return -ENOSPC;  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4399 		drm_dbg_kms(&i915->drm, "wrong static hdr metadata size\n");  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4400 		return -ENOSPC;  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4406 	 * Table 2-100 and Table 2-101  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4409 	/* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4410 	sdp->sdp_header.HB0 = 0;  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4412 	 * Packet Type 80h + Non-audio INFOFRAME Type value  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4414 	 * - 80h + Non-audio INFOFRAME Type value  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4415 	 * - InfoFrame Type: 0x07  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4416 	 *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4418 	sdp->sdp_header.HB1 = drm_infoframe->type;  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4421 	 * infoframe_size - 1  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4423 	sdp->sdp_header.HB2 = 0x1D;  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4425 	sdp->sdp_header.HB3 = (0x13 << 2);  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4427 	sdp->db[0] = drm_infoframe->version;  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4429 	sdp->db[1] = drm_infoframe->length;  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4434 	BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4435 	memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4440 	 * - DP SDP Header(struct dp_sdp_header): 4 bytes  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4441 	 * - Two Data Blocks: 2 bytes  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4444 	 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes  in intel_dp_hdr_metadata_infoframe_sdp_pack()
4458 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_write_dp_sdp()
4462 	if ((crtc_state->infoframes.enable &  in intel_write_dp_sdp()
4468 		len = drm_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp);  in intel_write_dp_sdp()
4472 							       &crtc_state->infoframes.drm.drm,  in intel_write_dp_sdp()
4476 		len = intel_dp_as_sdp_pack(&crtc_state->infoframes.as_sdp, &sdp,  in intel_write_dp_sdp()
4484 	if (drm_WARN_ON(&dev_priv->drm, len < 0))  in intel_write_dp_sdp()
4487 	dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);  in intel_write_dp_sdp()
4495 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_dp_set_infoframes()
4497 					    crtc_state->cpu_transcoder);  in intel_dp_set_infoframes()
4515 	if (!enable || !crtc_state->has_psr)  in intel_dp_set_infoframes()
4537 		return -EINVAL;  in intel_dp_as_sdp_unpack()
4541 	if (sdp->sdp_header.HB0 != 0)  in intel_dp_as_sdp_unpack()
4542 		return -EINVAL;  in intel_dp_as_sdp_unpack()
4544 	if (sdp->sdp_header.HB1 != DP_SDP_ADAPTIVE_SYNC)  in intel_dp_as_sdp_unpack()
4545 		return -EINVAL;  in intel_dp_as_sdp_unpack()
4547 	if (sdp->sdp_header.HB2 != 0x02)  in intel_dp_as_sdp_unpack()
4548 		return -EINVAL;  in intel_dp_as_sdp_unpack()
4550 	if ((sdp->sdp_header.HB3 & 0x3F) != 9)  in intel_dp_as_sdp_unpack()
4551 		return -EINVAL;  in intel_dp_as_sdp_unpack()
4553 	as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH;  in intel_dp_as_sdp_unpack()
4554 	as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE;  in intel_dp_as_sdp_unpack()
4555 	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];  in intel_dp_as_sdp_unpack()
4556 	as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);  in intel_dp_as_sdp_unpack()
4557 	as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;  in intel_dp_as_sdp_unpack()
4568 		return -EINVAL;  in intel_dp_vsc_sdp_unpack()
4572 	if (sdp->sdp_header.HB0 != 0)  in intel_dp_vsc_sdp_unpack()
4573 		return -EINVAL;  in intel_dp_vsc_sdp_unpack()
4575 	if (sdp->sdp_header.HB1 != DP_SDP_VSC)  in intel_dp_vsc_sdp_unpack()
4576 		return -EINVAL;  in intel_dp_vsc_sdp_unpack()
4578 	vsc->sdp_type = sdp->sdp_header.HB1;  in intel_dp_vsc_sdp_unpack()
4579 	vsc->revision = sdp->sdp_header.HB2;  in intel_dp_vsc_sdp_unpack()
4580 	vsc->length = sdp->sdp_header.HB3;  in intel_dp_vsc_sdp_unpack()
4582 	if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||  in intel_dp_vsc_sdp_unpack()
4583 	    (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe) ||  in intel_dp_vsc_sdp_unpack()
4584 	    (sdp->sdp_header.HB2 == 0x6 && sdp->sdp_header.HB3 == 0x10)) {  in intel_dp_vsc_sdp_unpack()
4586 		 * - HB2 = 0x2, HB3 = 0x8  in intel_dp_vsc_sdp_unpack()
4588 		 * - HB2 = 0x4, HB3 = 0xe  in intel_dp_vsc_sdp_unpack()
4589 		 *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of  in intel_dp_vsc_sdp_unpack()
4592 		 * - HB2 = 0x6, HB3 = 0x10  in intel_dp_vsc_sdp_unpack()
4596 	} else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {  in intel_dp_vsc_sdp_unpack()
4598 		 * - HB2 = 0x5, HB3 = 0x13  in intel_dp_vsc_sdp_unpack()
4602 		vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;  in intel_dp_vsc_sdp_unpack()
4603 		vsc->colorimetry = sdp->db[16] & 0xf;  in intel_dp_vsc_sdp_unpack()
4604 		vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;  in intel_dp_vsc_sdp_unpack()
4606 		switch (sdp->db[17] & 0x7) {  in intel_dp_vsc_sdp_unpack()
4608 			vsc->bpc = 6;  in intel_dp_vsc_sdp_unpack()
4611 			vsc->bpc = 8;  in intel_dp_vsc_sdp_unpack()
4614 			vsc->bpc = 10;  in intel_dp_vsc_sdp_unpack()
4617 			vsc->bpc = 12;  in intel_dp_vsc_sdp_unpack()
4620 			vsc->bpc = 16;  in intel_dp_vsc_sdp_unpack()
4623 			MISSING_CASE(sdp->db[17] & 0x7);  in intel_dp_vsc_sdp_unpack()
4624 			return -EINVAL;  in intel_dp_vsc_sdp_unpack()
4627 		vsc->content_type = sdp->db[18] & 0x7;  in intel_dp_vsc_sdp_unpack()
4629 		return -EINVAL;  in intel_dp_vsc_sdp_unpack()
4641 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_read_dp_as_sdp()
4646 	if ((crtc_state->infoframes.enable &  in intel_read_dp_as_sdp()
4650 	dig_port->read_infoframe(encoder, crtc_state, type, &sdp,  in intel_read_dp_as_sdp()
4655 		drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP AS SDP\n");  in intel_read_dp_as_sdp()
4667 		return -EINVAL;  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4669 	if (sdp->sdp_header.HB0 != 0)  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4670 		return -EINVAL;  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4672 	if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4673 		return -EINVAL;  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4679 	if (sdp->sdp_header.HB2 != 0x1D)  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4680 		return -EINVAL;  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4683 	if ((sdp->sdp_header.HB3 & 0x3) != 0)  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4684 		return -EINVAL;  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4687 	if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4688 		return -EINVAL;  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4691 	if (sdp->db[0] != 1)  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4692 		return -EINVAL;  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4695 	if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4696 		return -EINVAL;  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4698 	ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],  in intel_dp_hdr_metadata_infoframe_sdp_unpack()
4709 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_read_dp_vsc_sdp()
4714 	if ((crtc_state->infoframes.enable &  in intel_read_dp_vsc_sdp()
4718 	dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));  in intel_read_dp_vsc_sdp()
4723 		drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");  in intel_read_dp_vsc_sdp()
4731 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_read_dp_hdr_metadata_infoframe_sdp()
4736 	if ((crtc_state->infoframes.enable &  in intel_read_dp_hdr_metadata_infoframe_sdp()
4740 	dig_port->read_infoframe(encoder, crtc_state, type, &sdp,  in intel_read_dp_hdr_metadata_infoframe_sdp()
4747 		drm_dbg_kms(&dev_priv->drm,  in intel_read_dp_hdr_metadata_infoframe_sdp()
4758 				      &crtc_state->infoframes.vsc);  in intel_read_dp_sdp()
4762 							 &crtc_state->infoframes.drm.drm);  in intel_read_dp_sdp()
4766 				     &crtc_state->infoframes.as_sdp);  in intel_read_dp_sdp()
4784 	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,  in intel_dp_autotest_link_training()
4788 		drm_dbg_kms(&i915->drm, "Lane count read failed\n");  in intel_dp_autotest_link_training()
4793 	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,  in intel_dp_autotest_link_training()
4796 		drm_dbg_kms(&i915->drm, "Link Rate read failed\n");  in intel_dp_autotest_link_training()
4806 	intel_dp->compliance.test_lane_count = test_lane_count;  in intel_dp_autotest_link_training()
4807 	intel_dp->compliance.test_link_rate = test_link_rate;  in intel_dp_autotest_link_training()
4821 	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,  in intel_dp_autotest_video_pattern()
4824 		drm_dbg_kms(&i915->drm, "Test pattern read failed\n");  in intel_dp_autotest_video_pattern()
4830 	status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,  in intel_dp_autotest_video_pattern()
4833 		drm_dbg_kms(&i915->drm, "H Width read failed\n");  in intel_dp_autotest_video_pattern()
4837 	status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,  in intel_dp_autotest_video_pattern()
4840 		drm_dbg_kms(&i915->drm, "V Height read failed\n");  in intel_dp_autotest_video_pattern()
4844 	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,  in intel_dp_autotest_video_pattern()
4847 		drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");  in intel_dp_autotest_video_pattern()
4856 		intel_dp->compliance.test_data.bpc = 6;  in intel_dp_autotest_video_pattern()
4859 		intel_dp->compliance.test_data.bpc = 8;  in intel_dp_autotest_video_pattern()
4865 	intel_dp->compliance.test_data.video_pattern = test_pattern;  in intel_dp_autotest_video_pattern()
4866 	intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);  in intel_dp_autotest_video_pattern()
4867 	intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);  in intel_dp_autotest_video_pattern()
4869 	intel_dp->compliance.test_active = true;  in intel_dp_autotest_video_pattern()
4878 	struct intel_connector *intel_connector = intel_dp->attached_connector;  in intel_dp_autotest_edid()
4879 	struct drm_connector *connector = &intel_connector->base;  in intel_dp_autotest_edid()
4881 	if (intel_connector->detect_edid == NULL ||  in intel_dp_autotest_edid()
4882 	    connector->edid_corrupt ||  in intel_dp_autotest_edid()
4883 	    intel_dp->aux.i2c_defer_count > 6) {  in intel_dp_autotest_edid()
4891 		if (intel_dp->aux.i2c_nack_count > 0 ||  in intel_dp_autotest_edid()
4892 			intel_dp->aux.i2c_defer_count > 0)  in intel_dp_autotest_edid()
4893 			drm_dbg_kms(&i915->drm,  in intel_dp_autotest_edid()
4895 				    intel_dp->aux.i2c_nack_count,  in intel_dp_autotest_edid()
4896 				    intel_dp->aux.i2c_defer_count);  in intel_dp_autotest_edid()
4897 		intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;  in intel_dp_autotest_edid()
4900 		const struct edid *block = drm_edid_raw(intel_connector->detect_edid);  in intel_dp_autotest_edid()
4903 		block += block->extensions;  in intel_dp_autotest_edid()
4905 		if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,  in intel_dp_autotest_edid()
4906 				       block->checksum) <= 0)  in intel_dp_autotest_edid()
4907 			drm_dbg_kms(&i915->drm,  in intel_dp_autotest_edid()
4911 		intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;  in intel_dp_autotest_edid()
4915 	intel_dp->compliance.test_active = true;  in intel_dp_autotest_edid()
4924 			to_i915(dp_to_dig_port(intel_dp)->base.base.dev);  in intel_dp_phy_pattern_update()
4926 			&intel_dp->compliance.test_data.phytest;  in intel_dp_phy_pattern_update()
4927 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_dp_phy_pattern_update()
4928 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in intel_dp_phy_pattern_update()
4929 	enum pipe pipe = crtc->pipe;  in intel_dp_phy_pattern_update()
4932 	switch (data->phy_pattern) {  in intel_dp_phy_pattern_update()
4934 		drm_dbg_kms(&dev_priv->drm, "Disable Phy Test Pattern\n");  in intel_dp_phy_pattern_update()
4942 		drm_dbg_kms(&dev_priv->drm, "Set D10.2 Phy Test Pattern\n");  in intel_dp_phy_pattern_update()
4947 		drm_dbg_kms(&dev_priv->drm, "Set Error Count Phy Test Pattern\n");  in intel_dp_phy_pattern_update()
4953 		drm_dbg_kms(&dev_priv->drm, "Set PRBS7 Phy Test Pattern\n");  in intel_dp_phy_pattern_update()
4960 		 * current firmware of DPR-100 could not set it, so hardcoding  in intel_dp_phy_pattern_update()
4963 		drm_dbg_kms(&dev_priv->drm,  in intel_dp_phy_pattern_update()
4978 		 * current firmware of DPR-100 could not set it, so hardcoding  in intel_dp_phy_pattern_update()
4981 		drm_dbg_kms(&dev_priv->drm, "Set HBR2 compliance Phy Test Pattern\n");  in intel_dp_phy_pattern_update()
4989 			drm_warn(&dev_priv->drm, "Platform does not support TPS4\n");  in intel_dp_phy_pattern_update()
4992 		drm_dbg_kms(&dev_priv->drm, "Set TPS4 compliance Phy Test Pattern\n");  in intel_dp_phy_pattern_update()
4999 		drm_warn(&dev_priv->drm, "Invalid Phy Test Pattern\n");  in intel_dp_phy_pattern_update()
5008 		&intel_dp->compliance.test_data.phytest;  in intel_dp_process_phy_request()
5011 	if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,  in intel_dp_process_phy_request()
5013 		drm_dbg_kms(&i915->drm, "failed to get link status\n");  in intel_dp_process_phy_request()
5017 	/* retrieve vswing & pre-emphasis setting */  in intel_dp_process_phy_request()
5025 	drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,  in intel_dp_process_phy_request()
5026 			  intel_dp->train_set, crtc_state->lane_count);  in intel_dp_process_phy_request()
5028 	drm_dp_set_phy_test_pattern(&intel_dp->aux, data,  in intel_dp_process_phy_request()
5029 				    intel_dp->dpcd[DP_DPCD_REV]);  in intel_dp_process_phy_request()
5036 		&intel_dp->compliance.test_data.phytest;  in intel_dp_autotest_phy_pattern()
5038 	if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {  in intel_dp_autotest_phy_pattern()
5039 		drm_dbg_kms(&i915->drm, "DP Phy Test pattern AUX read failure\n");  in intel_dp_autotest_phy_pattern()
5044 	intel_dp->compliance.test_active = true;  in intel_dp_autotest_phy_pattern()
5056 	status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);  in intel_dp_handle_test_request()
5058 		drm_dbg_kms(&i915->drm,  in intel_dp_handle_test_request()
5065 		drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");  in intel_dp_handle_test_request()
5069 		drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");  in intel_dp_handle_test_request()
5073 		drm_dbg_kms(&i915->drm, "EDID test requested\n");  in intel_dp_handle_test_request()
5077 		drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");  in intel_dp_handle_test_request()
5081 		drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",  in intel_dp_handle_test_request()
5087 		intel_dp->compliance.test_type = request;  in intel_dp_handle_test_request()
5090 	status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);  in intel_dp_handle_test_request()
5092 		drm_dbg_kms(&i915->drm,  in intel_dp_handle_test_request()
5099 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in intel_dp_link_ok()
5100 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_dp_link_ok()
5101 	bool uhbr = intel_dp->link_rate >= 1000000;  in intel_dp_link_ok()
5106 							  intel_dp->lane_count);  in intel_dp_link_ok()
5108 		ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);  in intel_dp_link_ok()
5114 	drm_dbg_kms(&i915->drm,  in intel_dp_link_ok()
5116 		    encoder->base.base.id, encoder->base.name,  in intel_dp_link_ok()
5127 	drm_dp_mst_hpd_irq_handle_event(&intel_dp->mst_mgr, esi, ack, &handled);  in intel_dp_mst_hpd_irq()
5130 		intel_hdcp_handle_cp_irq(intel_dp->attached_connector);  in intel_dp_mst_hpd_irq()
5137 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in intel_dp_mst_link_status()
5138 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_dp_mst_link_status()
5140 	const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;  in intel_dp_mst_link_status()
5142 	if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,  in intel_dp_mst_link_status()
5144 		drm_err(&i915->drm,  in intel_dp_mst_link_status()
5146 			encoder->base.base.id, encoder->base.name);  in intel_dp_mst_link_status()
5154  * intel_dp_check_mst_status - service any pending MST interrupts, check link status
5161  * - %true if pending interrupts were serviced (or no interrupts were
5163  * - %false if an error condition - like AUX failure or a loss of link - is
5164  *   detected, or another condition - like a DP tunnel BW state change - needs
5172 	struct intel_encoder *encoder = &dig_port->base;  in intel_dp_check_mst_status()
5176 	drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);  in intel_dp_check_mst_status()
5183 			drm_dbg_kms(&i915->drm,  in intel_dp_check_mst_status()
5184 				    "failed to get ESI - device may have failed\n");  in intel_dp_check_mst_status()
5190 		drm_dbg_kms(&i915->drm, "DPRX ESI: %4ph\n", esi);  in intel_dp_check_mst_status()
5192 		if (intel_dp->active_mst_links > 0 && link_ok &&  in intel_dp_check_mst_status()
5202 			if (drm_dp_tunnel_handle_irq(i915->display.dp_tunnel_mgr,  in intel_dp_check_mst_status()
5203 						     &intel_dp->aux))  in intel_dp_check_mst_status()
5212 			drm_dbg_kms(&i915->drm, "Failed to ack ESI\n");  in intel_dp_check_mst_status()
5215 			drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr);  in intel_dp_check_mst_status()
5218 	if (!link_ok || intel_dp->link.force_retrain)  in intel_dp_check_mst_status()
5230 	is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux);  in intel_dp_handle_hdmi_link_status_change()
5231 	if (intel_dp->frl.is_trained && !is_active) {  in intel_dp_handle_hdmi_link_status_change()
5232 		if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0)  in intel_dp_handle_hdmi_link_status_change()
5236 		if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0)  in intel_dp_handle_hdmi_link_status_change()
5239 		drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base);  in intel_dp_handle_hdmi_link_status_change()
5241 		intel_dp->frl.is_trained = false;  in intel_dp_handle_hdmi_link_status_change()
5253 	if (!intel_dp->link_trained)  in intel_dp_needs_link_retrain()
5257 	 * While PSR source HW is enabled, it will control main-link sending  in intel_dp_needs_link_retrain()
5267 	if (intel_dp->link.force_retrain)  in intel_dp_needs_link_retrain()
5270 	if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,  in intel_dp_needs_link_retrain()
5275 	 * Validate the cached values of intel_dp->link_rate and  in intel_dp_needs_link_retrain()
5276 	 * intel_dp->lane_count before attempting to retrain.  in intel_dp_needs_link_retrain()
5282 	if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,  in intel_dp_needs_link_retrain()
5283 					intel_dp->lane_count))  in intel_dp_needs_link_retrain()
5286 	if (intel_dp->link.retrain_disabled)  in intel_dp_needs_link_retrain()
5289 	if (intel_dp->link.seq_train_failures)  in intel_dp_needs_link_retrain()
5303 	if (!conn_state->best_encoder)  in intel_dp_has_connector()
5307 	encoder = &dp_to_dig_port(intel_dp)->base;  in intel_dp_has_connector()
5308 	if (conn_state->best_encoder == &encoder->base)  in intel_dp_has_connector()
5313 		encoder = &intel_dp->mst_encoders[pipe]->base;  in intel_dp_has_connector()
5314 		if (conn_state->best_encoder == &encoder->base)  in intel_dp_has_connector()
5332 	drm_connector_list_iter_begin(&i915->drm, &conn_iter);  in intel_dp_get_active_pipes()
5335 			connector->base.state;  in intel_dp_get_active_pipes()
5342 		crtc = to_intel_crtc(conn_state->crtc);  in intel_dp_get_active_pipes()
5346 		ret = drm_modeset_lock(&crtc->base.mutex, ctx);  in intel_dp_get_active_pipes()
5350 		crtc_state = to_intel_crtc_state(crtc->base.state);  in intel_dp_get_active_pipes()
5352 		drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));  in intel_dp_get_active_pipes()
5354 		if (!crtc_state->hw.active)  in intel_dp_get_active_pipes()
5357 		if (conn_state->commit)  in intel_dp_get_active_pipes()
5358 			drm_WARN_ON(&i915->drm,  in intel_dp_get_active_pipes()
5359 				    !wait_for_completion_timeout(&conn_state->commit->hw_done,  in intel_dp_get_active_pipes()
5362 		*pipe_mask |= BIT(crtc->pipe);  in intel_dp_get_active_pipes()
5371 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_is_connected()
5373 	return connector->base.status == connector_status_connected ||  in intel_dp_is_connected()
5374 		intel_dp->is_mst;  in intel_dp_is_connected()
5380 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_dp_retrain_link()
5388 	ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,  in intel_dp_retrain_link()
5406 	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link (forced %s)\n",  in intel_dp_retrain_link()
5407 		    encoder->base.base.id, encoder->base.name,  in intel_dp_retrain_link()
5408 		    str_yes_no(intel_dp->link.force_retrain));  in intel_dp_retrain_link()
5411 	if (ret == -EDEADLK)  in intel_dp_retrain_link()
5414 	intel_dp->link.force_retrain = false;  in intel_dp_retrain_link()
5417 		drm_dbg_kms(&dev_priv->drm,  in intel_dp_retrain_link()
5419 			    encoder->base.base.id, encoder->base.name,  in intel_dp_retrain_link()
5437 	struct intel_encoder *encoder = &dig_port->base;  in intel_dp_check_link_state()
5459 	drm_connector_list_iter_begin(&i915->drm, &conn_iter);  in intel_dp_prep_phy_test()
5462 			connector->base.state;  in intel_dp_prep_phy_test()
5469 		crtc = to_intel_crtc(conn_state->crtc);  in intel_dp_prep_phy_test()
5473 		ret = drm_modeset_lock(&crtc->base.mutex, ctx);  in intel_dp_prep_phy_test()
5477 		crtc_state = to_intel_crtc_state(crtc->base.state);  in intel_dp_prep_phy_test()
5479 		drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));  in intel_dp_prep_phy_test()
5481 		if (!crtc_state->hw.active)  in intel_dp_prep_phy_test()
5484 		if (conn_state->commit &&  in intel_dp_prep_phy_test()
5485 		    !try_wait_for_completion(&conn_state->commit->hw_done))  in intel_dp_prep_phy_test()
5488 		*pipe_mask |= BIT(crtc->pipe);  in intel_dp_prep_phy_test()
5498 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_dp_do_phy_test()
5504 	ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,  in intel_dp_do_phy_test()
5516 	drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",  in intel_dp_do_phy_test()
5517 		    encoder->base.base.id, encoder->base.name);  in intel_dp_do_phy_test()
5519 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) {  in intel_dp_do_phy_test()
5521 			to_intel_crtc_state(crtc->base.state);  in intel_dp_do_phy_test()
5546 		if (ret == -EDEADLK) {  in intel_dp_phy_test()
5556 	drm_WARN(encoder->base.dev, ret,  in intel_dp_phy_test()
5565 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)  in intel_dp_check_device_service_irq()
5568 	if (drm_dp_dpcd_readb(&intel_dp->aux,  in intel_dp_check_device_service_irq()
5572 	drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);  in intel_dp_check_device_service_irq()
5578 		intel_hdcp_handle_cp_irq(intel_dp->attached_connector);  in intel_dp_check_device_service_irq()
5581 		drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");  in intel_dp_check_device_service_irq()
5590 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)  in intel_dp_check_link_service_irq()
5593 	if (drm_dp_dpcd_readb(&intel_dp->aux,  in intel_dp_check_link_service_irq()
5598 	    drm_dp_tunnel_handle_irq(i915->display.dp_tunnel_mgr,  in intel_dp_check_link_service_irq()
5599 				     &intel_dp->aux))  in intel_dp_check_link_service_irq()
5602 	if (drm_dp_dpcd_writeb(&intel_dp->aux,  in intel_dp_check_link_service_irq()
5618  *  4. Check link status on receipt of hot-plug interrupt
5620  * intel_dp_short_pulse -  handles short pulse interrupts
5629 	u8 old_sink_count = intel_dp->sink_count;  in intel_dp_short_pulse()
5637 	memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));  in intel_dp_short_pulse()
5647 	if ((old_sink_count != intel_dp->sink_count) || !ret) {  in intel_dp_short_pulse()
5656 	drm_dp_cec_irq(&intel_dp->aux);  in intel_dp_short_pulse()
5662 	switch (intel_dp->compliance.test_type) {  in intel_dp_short_pulse()
5664 		drm_dbg_kms(&dev_priv->drm,  in intel_dp_short_pulse()
5667 		drm_kms_helper_hotplug_event(&dev_priv->drm);  in intel_dp_short_pulse()
5670 		drm_dbg_kms(&dev_priv->drm,  in intel_dp_short_pulse()
5675 		 * FIXME get rid of the ad-hoc phy test modeset code  in intel_dp_short_pulse()
5690 	u8 *dpcd = intel_dp->dpcd;  in intel_dp_detect_dpcd()
5693 	if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))  in intel_dp_detect_dpcd()
5701 	intel_dp->mst_detect = intel_dp_mst_detect(intel_dp);  in intel_dp_detect_dpcd()
5707 	/* If we're HPD-aware, SINK_COUNT changes dynamically */  in intel_dp_detect_dpcd()
5709 	    intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {  in intel_dp_detect_dpcd()
5710 		return intel_dp->sink_count ?  in intel_dp_detect_dpcd()
5714 	if (intel_dp->mst_detect == DRM_DP_MST)  in intel_dp_detect_dpcd()
5718 	if (drm_probe_ddc(&intel_dp->aux.ddc))  in intel_dp_detect_dpcd()
5722 	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {  in intel_dp_detect_dpcd()
5723 		type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;  in intel_dp_detect_dpcd()
5728 		type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &  in intel_dp_detect_dpcd()
5736 	drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");  in intel_dp_detect_dpcd()
5750 	if (dig_port->lock)  in intel_digital_port_lock()
5751 		dig_port->lock(dig_port);  in intel_digital_port_lock()
5758 	if (dig_port->unlock)  in intel_digital_port_unlock()
5759 		dig_port->unlock(dig_port);  in intel_digital_port_unlock()
5763  * intel_digital_port_connected_locked - is the specified port connected?
5768  * pretty much treat the port as disconnected. This is relevant for type-C
5778 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_digital_port_connected_locked()
5788 			is_connected = dig_port->connected(encoder);  in intel_digital_port_connected_locked()
5812 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_get_edid()
5813 	const struct drm_edid *fixed_edid = connector->panel.fixed_edid;  in intel_dp_get_edid()
5824 	return drm_edid_read_ddc(&connector->base, &intel_dp->aux.ddc);  in intel_dp_get_edid()
5832 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_update_dfp()
5834 	intel_dp->dfp.max_bpc =  in intel_dp_update_dfp()
5835 		drm_dp_downstream_max_bpc(intel_dp->dpcd,  in intel_dp_update_dfp()
5836 					  intel_dp->downstream_ports, drm_edid);  in intel_dp_update_dfp()
5838 	intel_dp->dfp.max_dotclock =  in intel_dp_update_dfp()
5839 		drm_dp_downstream_max_dotclock(intel_dp->dpcd,  in intel_dp_update_dfp()
5840 					       intel_dp->downstream_ports);  in intel_dp_update_dfp()
5842 	intel_dp->dfp.min_tmds_clock =  in intel_dp_update_dfp()
5843 		drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,  in intel_dp_update_dfp()
5844 						 intel_dp->downstream_ports,  in intel_dp_update_dfp()
5846 	intel_dp->dfp.max_tmds_clock =  in intel_dp_update_dfp()
5847 		drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,  in intel_dp_update_dfp()
5848 						 intel_dp->downstream_ports,  in intel_dp_update_dfp()
5851 	intel_dp->dfp.pcon_max_frl_bw =  in intel_dp_update_dfp()
5852 		drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,  in intel_dp_update_dfp()
5853 					   intel_dp->downstream_ports);  in intel_dp_update_dfp()
5855 	drm_dbg_kms(&i915->drm,  in intel_dp_update_dfp()
5856 …   "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",  in intel_dp_update_dfp()
5857 		    connector->base.base.id, connector->base.name,  in intel_dp_update_dfp()
5858 		    intel_dp->dfp.max_bpc,  in intel_dp_update_dfp()
5859 		    intel_dp->dfp.max_dotclock,  in intel_dp_update_dfp()
5860 		    intel_dp->dfp.min_tmds_clock,  in intel_dp_update_dfp()
5861 		    intel_dp->dfp.max_tmds_clock,  in intel_dp_update_dfp()
5862 		    intel_dp->dfp.pcon_max_frl_bw);  in intel_dp_update_dfp()
5871 	    (!drm_dp_is_branch(intel_dp->dpcd) || intel_dp->dfp.ycbcr420_passthrough))  in intel_dp_can_ycbcr420()
5889 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_update_420()
5891 	intel_dp->dfp.ycbcr420_passthrough =  in intel_dp_update_420()
5892 		drm_dp_downstream_420_passthrough(intel_dp->dpcd,  in intel_dp_update_420()
5893 						  intel_dp->downstream_ports);  in intel_dp_update_420()
5894 	/* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */  in intel_dp_update_420()
5895 	intel_dp->dfp.ycbcr_444_to_420 =  in intel_dp_update_420()
5896 		dp_to_dig_port(intel_dp)->lspcon.active ||  in intel_dp_update_420()
5897 		drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,  in intel_dp_update_420()
5898 							intel_dp->downstream_ports);  in intel_dp_update_420()
5899 	intel_dp->dfp.rgb_to_ycbcr =  in intel_dp_update_420()
5900 		drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd,  in intel_dp_update_420()
5901 							  intel_dp->downstream_ports,  in intel_dp_update_420()
5904 	connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);  in intel_dp_update_420()
5906 	drm_dbg_kms(&i915->drm,  in intel_dp_update_420()
5907 …"[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversi…  in intel_dp_update_420()
5908 		    connector->base.base.id, connector->base.name,  in intel_dp_update_420()
5909 		    str_yes_no(intel_dp->dfp.rgb_to_ycbcr),  in intel_dp_update_420()
5910 		    str_yes_no(connector->base.ycbcr_420_allowed),  in intel_dp_update_420()
5911 		    str_yes_no(intel_dp->dfp.ycbcr_444_to_420));  in intel_dp_update_420()
5918 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_set_edid()
5924 	connector->detect_edid = drm_edid;  in intel_dp_set_edid()
5927 	drm_edid_connector_update(&connector->base, drm_edid);  in intel_dp_set_edid()
5930 	drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",  in intel_dp_set_edid()
5931 		    connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));  in intel_dp_set_edid()
5932 	drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);  in intel_dp_set_edid()
5937 	drm_dp_cec_attach(&intel_dp->aux,  in intel_dp_set_edid()
5938 			  connector->base.display_info.source_physical_address);  in intel_dp_set_edid()
5944 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_dp_unset_edid()
5946 	drm_dp_cec_unset_edid(&intel_dp->aux);  in intel_dp_unset_edid()
5947 	drm_edid_free(connector->detect_edid);  in intel_dp_unset_edid()
5948 	connector->detect_edid = NULL;  in intel_dp_unset_edid()
5950 	intel_dp->dfp.max_bpc = 0;  in intel_dp_unset_edid()
5951 	intel_dp->dfp.max_dotclock = 0;  in intel_dp_unset_edid()
5952 	intel_dp->dfp.min_tmds_clock = 0;  in intel_dp_unset_edid()
5953 	intel_dp->dfp.max_tmds_clock = 0;  in intel_dp_unset_edid()
5955 	intel_dp->dfp.pcon_max_frl_bw = 0;  in intel_dp_unset_edid()
5957 	intel_dp->dfp.ycbcr_444_to_420 = false;  in intel_dp_unset_edid()
5958 	connector->base.ycbcr_420_allowed = false;  in intel_dp_unset_edid()
5960 	drm_connector_set_vrr_capable_property(&connector->base,  in intel_dp_unset_edid()
5974 		intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0],  in intel_dp_detect_dsc_caps()
5977 		intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV],  in intel_dp_detect_dsc_caps()
5986 	intel_dp->as_sdp_supported = HAS_AS_SDP(i915) &&  in intel_dp_detect_sdp_caps()
5987 		drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);  in intel_dp_detect_sdp_caps()
5995 	struct drm_i915_private *dev_priv = to_i915(connector->dev);  in intel_dp_detect()
6000 	struct intel_encoder *encoder = &dig_port->base;  in intel_dp_detect()
6004 	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",  in intel_dp_detect()
6005 		    connector->base.id, connector->name);  in intel_dp_detect()
6006 	drm_WARN_ON(&dev_priv->drm,  in intel_dp_detect()
6007 		    !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));  in intel_dp_detect()
6013 		return connector->status;  in intel_dp_detect()
6026 		 * This requires retrying detection for instance to re-enable  in intel_dp_detect()
6036 		memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));  in intel_dp_detect()
6037 		memset(intel_connector->dp.dsc_dpcd, 0, sizeof(intel_connector->dp.dsc_dpcd));  in intel_dp_detect()
6038 		intel_dp->psr.sink_panel_replay_support = false;  in intel_dp_detect()
6039 		intel_dp->psr.sink_panel_replay_su_support = false;  in intel_dp_detect()
6049 	if (ret == -EDEADLK)  in intel_dp_detect()
6053 		intel_connector->base.epoch_counter++;  in intel_dp_detect()
6062 	if (intel_dp->reset_link_params) {  in intel_dp_detect()
6064 		intel_dp->reset_link_params = false;  in intel_dp_detect()
6071 	if (intel_dp->is_mst) {  in intel_dp_detect()
6097 	intel_dp->aux.i2c_nack_count = 0;  in intel_dp_detect()
6098 	intel_dp->aux.i2c_defer_count = 0;  in intel_dp_detect()
6102 	    to_intel_connector(connector)->detect_edid)  in intel_dp_detect()
6108 	if (status != connector_status_connected && !intel_dp->is_mst)  in intel_dp_detect()
6114 						 intel_dp->dpcd,  in intel_dp_detect()
6115 						 intel_dp->downstream_ports);  in intel_dp_detect()
6124 	struct intel_encoder *intel_encoder = &dig_port->base;  in intel_dp_force()
6125 	struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);  in intel_dp_force()
6127 	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",  in intel_dp_force()
6128 		    connector->base.id, connector->name);  in intel_dp_force()
6135 	if (connector->status != connector_status_connected)  in intel_dp_force()
6146 	/* drm_edid_connector_update() done in ->detect() or ->force() */  in intel_dp_get_modes()
6156 	if (!intel_connector->detect_edid) {  in intel_dp_get_modes()
6160 		mode = drm_dp_downstream_mode(connector->dev,  in intel_dp_get_modes()
6161 					      intel_dp->dpcd,  in intel_dp_get_modes()
6162 					      intel_dp->downstream_ports);  in intel_dp_get_modes()
6175 	struct drm_i915_private *i915 = to_i915(connector->dev);  in intel_dp_connector_register()
6178 	struct intel_lspcon *lspcon = &dig_port->lspcon;  in intel_dp_connector_register()
6185 	drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",  in intel_dp_connector_register()
6186 		    intel_dp->aux.name, connector->kdev->kobj.name);  in intel_dp_connector_register()
6188 	intel_dp->aux.dev = connector->kdev;  in intel_dp_connector_register()
6189 	ret = drm_dp_aux_register(&intel_dp->aux);  in intel_dp_connector_register()
6191 		drm_dp_cec_register_connector(&intel_dp->aux, connector);  in intel_dp_connector_register()
6193 	if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata))  in intel_dp_connector_register()
6202 		if (lspcon->hdr_supported)  in intel_dp_connector_register()
6214 	drm_dp_cec_unregister_connector(&intel_dp->aux);  in intel_dp_connector_unregister()
6215 	drm_dp_aux_unregister(&intel_dp->aux);  in intel_dp_connector_unregister()
6222 	struct drm_i915_private *i915 = to_i915(connector->base.dev);  in intel_dp_connector_sync_state()
6224 	if (crtc_state && crtc_state->dsc.compression_enable) {  in intel_dp_connector_sync_state()
6225 		drm_WARN_ON(&i915->drm, !connector->dp.dsc_decompression_aux);  in intel_dp_connector_sync_state()
6226 		connector->dp.dsc_decompression_enabled = true;  in intel_dp_connector_sync_state()
6228 		connector->dp.dsc_decompression_enabled = false;  in intel_dp_connector_sync_state()
6236 	struct intel_dp *intel_dp = &dig_port->dp;  in intel_dp_encoder_flush_work()
6274 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_modeset_tile_group()
6279 	drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);  in intel_modeset_tile_group()
6285 		if (!connector->has_tile ||  in intel_modeset_tile_group()
6286 		    connector->tile_group->id != tile_group_id)  in intel_modeset_tile_group()
6289 		conn_state = drm_atomic_get_connector_state(&state->base,  in intel_modeset_tile_group()
6296 		crtc = to_intel_crtc(conn_state->crtc);  in intel_modeset_tile_group()
6302 		crtc_state->uapi.mode_changed = true;  in intel_modeset_tile_group()
6304 		ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);  in intel_modeset_tile_group()
6315 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_modeset_affected_transcoders()
6321 	for_each_intel_crtc(&dev_priv->drm, crtc) {  in intel_modeset_affected_transcoders()
6325 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in intel_modeset_affected_transcoders()
6329 		if (!crtc_state->hw.enable)  in intel_modeset_affected_transcoders()
6332 		if (!(transcoders & BIT(crtc_state->cpu_transcoder)))  in intel_modeset_affected_transcoders()
6335 		crtc_state->uapi.mode_changed = true;  in intel_modeset_affected_transcoders()
6337 		ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);  in intel_modeset_affected_transcoders()
6341 		ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);  in intel_modeset_affected_transcoders()
6345 		transcoders &= ~BIT(crtc_state->cpu_transcoder);  in intel_modeset_affected_transcoders()
6348 	drm_WARN_ON(&dev_priv->drm, transcoders != 0);  in intel_modeset_affected_transcoders()
6357 		drm_atomic_get_old_connector_state(&state->base, connector);  in intel_modeset_synced_crtcs()
6362 	crtc = to_intel_crtc(old_conn_state->crtc);  in intel_modeset_synced_crtcs()
6368 	if (!old_crtc_state->hw.active)  in intel_modeset_synced_crtcs()
6371 	transcoders = old_crtc_state->sync_mode_slaves_mask;  in intel_modeset_synced_crtcs()
6372 	if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)  in intel_modeset_synced_crtcs()
6373 		transcoders |= BIT(old_crtc_state->master_transcoder);  in intel_modeset_synced_crtcs()
6382 	struct drm_i915_private *dev_priv = to_i915(conn->dev);  in intel_dp_connector_atomic_check()
6386 	struct intel_dp *intel_dp = enc_to_intel_dp(intel_conn->encoder);  in intel_dp_connector_atomic_check()
6389 	ret = intel_digital_connector_atomic_check(conn, &state->base);  in intel_dp_connector_atomic_check()
6394 		ret = drm_dp_mst_root_conn_atomic_check(conn_state, &intel_dp->mst_mgr);  in intel_dp_connector_atomic_check()
6412 	if (DISPLAY_VER(dev_priv) < 9)  in intel_dp_connector_atomic_check()
6415 	if (conn->has_tile) {  in intel_dp_connector_atomic_check()
6416 		ret = intel_modeset_tile_group(state, conn->tile_group->id);  in intel_dp_connector_atomic_check()
6428 	struct drm_i915_private *i915 = to_i915(connector->dev);  in intel_dp_oob_hotplug_event()
6430 	unsigned int hpd_pin = encoder->hpd_pin;  in intel_dp_oob_hotplug_event()
6433 	spin_lock_irq(&i915->irq_lock);  in intel_dp_oob_hotplug_event()
6434 	if (hpd_high != test_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state)) {  in intel_dp_oob_hotplug_event()
6435 		i915->display.hotplug.event_bits |= BIT(hpd_pin);  in intel_dp_oob_hotplug_event()
6437 		__assign_bit(hpd_pin, &i915->display.hotplug.oob_hotplug_last_state, hpd_high);  in intel_dp_oob_hotplug_event()
6440 	spin_unlock_irq(&i915->irq_lock);  in intel_dp_oob_hotplug_event()
6469 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);  in intel_dp_hpd_pulse()
6470 	struct intel_dp *intel_dp = &dig_port->dp;  in intel_dp_hpd_pulse()
6473 	if (dig_port->base.type == INTEL_OUTPUT_EDP &&  in intel_dp_hpd_pulse()
6479 		 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."  in intel_dp_hpd_pulse()
6481 		drm_dbg_kms(&i915->drm,  in intel_dp_hpd_pulse()
6484 			    dig_port->base.base.base.id,  in intel_dp_hpd_pulse()
6485 			    dig_port->base.base.name);  in intel_dp_hpd_pulse()
6489 	drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",  in intel_dp_hpd_pulse()
6490 		    dig_port->base.base.base.id,  in intel_dp_hpd_pulse()
6491 		    dig_port->base.base.name,  in intel_dp_hpd_pulse()
6506 		intel_dp->reset_link_params = true;  in intel_dp_hpd_pulse()
6510 	if (intel_dp->is_mst) {  in intel_dp_hpd_pulse()
6531 	if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A)  in _intel_dp_is_port_edp()
6539 	struct intel_display *display = &i915->display;  in intel_dp_is_port_edp()
6549 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_dp_has_gamut_metadata_dip()
6550 	enum port port = encoder->port;  in intel_dp_has_gamut_metadata_dip()
6552 	if (intel_bios_encoder_is_lspcon(encoder->devdata))  in intel_dp_has_gamut_metadata_dip()
6562 	    DISPLAY_VER(i915) >= 9)  in intel_dp_has_gamut_metadata_dip()
6571 	struct drm_i915_private *dev_priv = to_i915(connector->dev);  in intel_dp_add_properties()
6572 	enum port port = dp_to_dig_port(intel_dp)->base.port;  in intel_dp_add_properties()
6587 	if (intel_bios_encoder_is_lspcon(dp_to_dig_port(intel_dp)->base.devdata)) {  in intel_dp_add_properties()
6594 	if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))  in intel_dp_add_properties()
6604 	struct intel_connector *connector = intel_dp->attached_connector;  in intel_edp_add_properties()
6605 	struct drm_i915_private *i915 = to_i915(connector->base.dev);  in intel_edp_add_properties()
6609 	intel_attach_scaling_mode_property(&connector->base);  in intel_edp_add_properties()
6611 	drm_connector_set_panel_orientation_with_quirk(&connector->base,  in intel_edp_add_properties()
6612 						       i915->display.vbt.orientation,  in intel_edp_add_properties()
6613 						       fixed_mode->hdisplay,  in intel_edp_add_properties()
6614 						       fixed_mode->vdisplay);  in intel_edp_add_properties()
6632 			pipe = intel_dp->pps.pps_pipe;  in intel_edp_backlight_setup()
6646 	struct drm_connector *connector = &intel_connector->base;  in intel_edp_init_connector()
6648 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;  in intel_edp_init_connector()
6659 	 * with an already powered-on LVDS power sequencer.  in intel_edp_init_connector()
6662 		drm_WARN_ON(&dev_priv->drm,  in intel_edp_init_connector()
6664 		drm_info(&dev_priv->drm,  in intel_edp_init_connector()
6670 	intel_bios_init_panel_early(display, &intel_connector->panel,  in intel_edp_init_connector()
6671 				    encoder->devdata);  in intel_edp_init_connector()
6674 		drm_info(&dev_priv->drm,  in intel_edp_init_connector()
6676 			 encoder->base.base.id, encoder->base.name);  in intel_edp_init_connector()
6701 		drm_info(&dev_priv->drm,  in intel_edp_init_connector()
6703 			 encoder->base.base.id, encoder->base.name);  in intel_edp_init_connector()
6715 	if (intel_bios_dp_has_shared_aux_ch(encoder->devdata)) {  in intel_edp_init_connector()
6724 			drm_info(&dev_priv->drm,  in intel_edp_init_connector()
6726 				 encoder->base.base.id, encoder->base.name);  in intel_edp_init_connector()
6732 		 * eg. Asus B360M-A (CFL+CNP), so as a last resort fall  in intel_edp_init_connector()
6736 		if (DISPLAY_VER(dev_priv) == 9 && drm_dp_is_branch(intel_dp->dpcd) &&  in intel_edp_init_connector()
6737 		    (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) ==  in intel_edp_init_connector()
6739 			drm_info(&dev_priv->drm,  in intel_edp_init_connector()
6741 				 encoder->base.base.id, encoder->base.name);  in intel_edp_init_connector()
6746 	mutex_lock(&dev_priv->drm.mode_config.mutex);  in intel_edp_init_connector()
6747 	drm_edid = drm_edid_read_ddc(connector, connector->ddc);  in intel_edp_init_connector()
6752 			drm_dbg_kms(&dev_priv->drm,  in intel_edp_init_connector()
6754 				    connector->base.id, connector->name);  in intel_edp_init_connector()
6761 			drm_edid = ERR_PTR(-EINVAL);  in intel_edp_init_connector()
6764 		drm_edid = ERR_PTR(-ENOENT);  in intel_edp_init_connector()
6767 	intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata,  in intel_edp_init_connector()
6776 	list_for_each_entry(fixed_mode, &intel_connector->panel.fixed_modes, head)  in intel_edp_init_connector()
6783 	mutex_unlock(&dev_priv->drm.mode_config.mutex);  in intel_edp_init_connector()
6786 		drm_info(&dev_priv->drm,  in intel_edp_init_connector()
6788 			 encoder->base.base.id, encoder->base.name);  in intel_edp_init_connector()
6815 	connector = &intel_connector->base;  in intel_dp_modeset_retry_work_fn()
6816 	drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s]\n", connector->base.id,  in intel_dp_modeset_retry_work_fn()
6817 		    connector->name);  in intel_dp_modeset_retry_work_fn()
6820 	mutex_lock(&connector->dev->mode_config.mutex);  in intel_dp_modeset_retry_work_fn()
6826 	mutex_unlock(&connector->dev->mode_config.mutex);  in intel_dp_modeset_retry_work_fn()
6835 	INIT_WORK(&connector->modeset_retry_work,  in intel_dp_init_modeset_retry_work()
6843 	struct drm_connector *connector = &intel_connector->base;  in intel_dp_init_connector()
6844 	struct intel_dp *intel_dp = &dig_port->dp;  in intel_dp_init_connector()
6845 	struct intel_encoder *intel_encoder = &dig_port->base;  in intel_dp_init_connector()
6846 	struct drm_device *dev = intel_encoder->base.dev;  in intel_dp_init_connector()
6848 	enum port port = intel_encoder->port;  in intel_dp_init_connector()
6854 	if (drm_WARN(dev, dig_port->max_lanes < 1,  in intel_dp_init_connector()
6856 		     dig_port->max_lanes, intel_encoder->base.base.id,  in intel_dp_init_connector()
6857 		     intel_encoder->base.name))  in intel_dp_init_connector()
6860 	intel_dp->reset_link_params = true;  in intel_dp_init_connector()
6861 	intel_dp->pps.pps_pipe = INVALID_PIPE;  in intel_dp_init_connector()
6862 	intel_dp->pps.active_pipe = INVALID_PIPE;  in intel_dp_init_connector()
6865 	intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);  in intel_dp_init_connector()
6866 	intel_dp->attached_connector = intel_connector;  in intel_dp_init_connector()
6868 	if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {  in intel_dp_init_connector()
6875 		intel_encoder->type = INTEL_OUTPUT_EDP;  in intel_dp_init_connector()
6890 		intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp);  in intel_dp_init_connector()
6893 	intel_connector->dp.dsc_decompression_aux = &intel_dp->aux;  in intel_dp_init_connector()
6895 	drm_dbg_kms(&dev_priv->drm,  in intel_dp_init_connector()
6898 		    intel_encoder->base.base.id, intel_encoder->base.name);  in intel_dp_init_connector()
6901 				    type, &intel_dp->aux.ddc);  in intel_dp_init_connector()
6905 		connector->interlace_allowed = true;  in intel_dp_init_connector()
6907 	intel_connector->polled = DRM_CONNECTOR_POLL_HPD;  in intel_dp_init_connector()
6908 	intel_connector->base.polled = intel_connector->polled;  in intel_dp_init_connector()
6913 		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;  in intel_dp_init_connector()
6915 		intel_connector->get_hw_state = intel_connector_get_hw_state;  in intel_dp_init_connector()
6916 	intel_connector->sync_state = intel_dp_connector_sync_state;  in intel_dp_init_connector()
6929 				  intel_connector->base.base.id);  in intel_dp_init_connector()
6936 			drm_dbg_kms(&dev_priv->drm,  in intel_dp_init_connector()
6940 	intel_dp->frl.is_trained = false;  in intel_dp_init_connector()
6941 	intel_dp->frl.trained_rate_gbps = 0;  in intel_dp_init_connector()
6961 	for_each_intel_encoder(&dev_priv->drm, encoder) {  in intel_dp_mst_suspend()
6964 		if (encoder->type != INTEL_OUTPUT_DDI)  in intel_dp_mst_suspend()
6972 		if (intel_dp->is_mst)  in intel_dp_mst_suspend()
6973 			drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);  in intel_dp_mst_suspend()
6984 	for_each_intel_encoder(&dev_priv->drm, encoder) {  in intel_dp_mst_resume()
6988 		if (encoder->type != INTEL_OUTPUT_DDI)  in intel_dp_mst_resume()
6996 		ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,  in intel_dp_mst_resume()
6999 			intel_dp->is_mst = false;  in intel_dp_mst_resume()
7000 			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,  in intel_dp_mst_resume()