Lines Matching +full:0 +full:x92000

12 #define DMC_SSP_BASE_ADDR_GEN9	0x00002FC0
14 #define _PIPEDMC_CONTROL_A		0x45250
15 #define _PIPEDMC_CONTROL_B		0x45254
19 #define  PIPEDMC_ENABLE			REG_BIT(0)
21 #define MTL_PIPEDMC_CONTROL		_MMIO(0x45250)
24 #define _ADLP_PIPEDMC_REG_MMIO_BASE_A	0x5f000
25 #define _TGL_PIPEDMC_REG_MMIO_BASE_A	0x92000
30 	 0x400 * ((dmc_id) - 1))
32 #define __DMC_REG_MMIO_BASE		0x8f000
43 #define _DMC_EVT_HTP_0			0x8f004
48 #define _DMC_EVT_CTL_0			0x8f034
56 #define DMC_EVT_CTL_TYPE_LEVEL_0	0
62 #define DMC_EVT_CTL_EVENT_ID_FALSE	0x01
63 #define DMC_EVT_CTL_EVENT_ID_VBLANK_A	0x32 /* main DMC */
65 #define DMC_EVT_CTL_EVENT_ID_CLK_MSEC	0xbf
67 #define DMC_HTP_ADDR_SKL	0x00500034
68 #define DMC_SSP_BASE		_MMIO(0x8F074)
69 #define DMC_HTP_SKL		_MMIO(0x8F004)
70 #define DMC_LAST_WRITE		_MMIO(0x8F034)
71 #define DMC_LAST_WRITE_VALUE	0xc003b400
72 #define DMC_MMIO_START_RANGE	0x80000
73 #define DMC_MMIO_END_RANGE     0x8FFFF
74 #define DMC_V1_MMIO_START_RANGE		0x80000
75 #define TGL_MAIN_MMIO_START		0x8F000
76 #define TGL_MAIN_MMIO_END		0x8FFFF
77 #define _TGL_PIPEA_MMIO_START		0x92000
78 #define _TGL_PIPEA_MMIO_END		0x93FFF
79 #define _TGL_PIPEB_MMIO_START		0x96000
80 #define _TGL_PIPEB_MMIO_END		0x97FFF
81 #define ADLP_PIPE_MMIO_START		0x5F000
82 #define ADLP_PIPE_MMIO_END		0x5FFFF
90 #define SKL_DMC_DC3_DC5_COUNT	_MMIO(0x80030)
91 #define SKL_DMC_DC5_DC6_COUNT	_MMIO(0x8002C)
92 #define BXT_DMC_DC3_DC5_COUNT	_MMIO(0x80038)
93 #define TGL_DMC_DEBUG_DC5_COUNT	_MMIO(0x101084)
94 #define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
95 #define DG1_DMC_DEBUG_DC5_COUNT	_MMIO(0x134154)
97 #define TGL_DMC_DEBUG3		_MMIO(0x101090)
98 #define DG1_DMC_DEBUG3		_MMIO(0x13415c)
100 #define DMC_WAKELOCK_CFG	_MMIO(0x8F1B0)
102 #define DMC_WAKELOCK1_CTL	_MMIO(0x8F140)