Lines Matching refs:page_mask
1550 u32 page_mask; member
1556 { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0xF },
1557 { .num_channels = 1, .type = INTEL_DRAM_DDR5, .page_mask = 0xF },
1558 { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1C },
1559 { .num_channels = 2, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x1C },
1560 { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x1F },
1561 { .num_channels = 2, .type = INTEL_DRAM_DDR5, .page_mask = 0x1E },
1562 { .num_channels = 4, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x38 },
1563 { .num_channels = 4, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x38 },
1568 { .num_channels = 1, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x1 },
1569 { .num_channels = 1, .type = INTEL_DRAM_DDR4, .page_mask = 0x1 },
1570 { .num_channels = 1, .type = INTEL_DRAM_DDR5, .page_mask = 0x1 },
1571 { .num_channels = 1, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x1 },
1572 { .num_channels = 2, .type = INTEL_DRAM_LPDDR4, .page_mask = 0x3 },
1573 { .num_channels = 2, .type = INTEL_DRAM_DDR4, .page_mask = 0x3 },
1574 { .num_channels = 2, .type = INTEL_DRAM_DDR5, .page_mask = 0x3 },
1575 { .num_channels = 2, .type = INTEL_DRAM_LPDDR5, .page_mask = 0x3 },
1598 for (config = 0; table[config].page_mask != 0; config++) in tgl_bw_buddy_init()
1603 if (table[config].page_mask == 0) { in tgl_bw_buddy_init()
1612 table[config].page_mask); in tgl_bw_buddy_init()