Lines Matching full:pipe
28 intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe) in intel_handle_vblank() argument
30 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); in intel_handle_vblank()
103 * bdw_update_pipe_irq - update DE pipe interrupt
105 * @pipe: pipe whose interrupt to update
110 enum pipe pipe, u32 interrupt_mask, in bdw_update_pipe_irq() argument
122 new_val = dev_priv->display.irq.de_irq_mask[pipe]; in bdw_update_pipe_irq()
126 if (new_val != dev_priv->display.irq.de_irq_mask[pipe]) { in bdw_update_pipe_irq()
127 dev_priv->display.irq.de_irq_mask[pipe] = new_val; in bdw_update_pipe_irq()
128 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe), in bdw_update_pipe_irq()
129 dev_priv->display.irq.de_irq_mask[pipe]); in bdw_update_pipe_irq()
130 intel_uncore_posting_read(&dev_priv->uncore, GEN8_DE_PIPE_IMR(pipe)); in bdw_update_pipe_irq()
135 enum pipe pipe, u32 bits) in bdw_enable_pipe_irq() argument
137 bdw_update_pipe_irq(i915, pipe, bits, bits); in bdw_enable_pipe_irq()
141 enum pipe pipe, u32 bits) in bdw_disable_pipe_irq() argument
143 bdw_update_pipe_irq(i915, pipe, bits, 0); in bdw_disable_pipe_irq()
183 enum pipe pipe) in i915_pipestat_enable_mask() argument
185 u32 status_mask = dev_priv->display.irq.pipestat_irq_mask[pipe]; in i915_pipestat_enable_mask()
194 * On pipe A we don't support the PSR interrupt yet, in i915_pipestat_enable_mask()
195 * on pipe B and C the same bit MBZ. in i915_pipestat_enable_mask()
201 * On pipe B and C we don't support the PSR interrupt yet, on pipe in i915_pipestat_enable_mask()
220 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n", in i915_pipestat_enable_mask()
221 pipe_name(pipe), enable_mask, status_mask); in i915_pipestat_enable_mask()
227 enum pipe pipe, u32 status_mask) in i915_enable_pipestat() argument
229 i915_reg_t reg = PIPESTAT(dev_priv, pipe); in i915_enable_pipestat()
233 "pipe %c: status_mask=0x%x\n", in i915_enable_pipestat()
234 pipe_name(pipe), status_mask); in i915_enable_pipestat()
239 if ((dev_priv->display.irq.pipestat_irq_mask[pipe] & status_mask) == status_mask) in i915_enable_pipestat()
242 dev_priv->display.irq.pipestat_irq_mask[pipe] |= status_mask; in i915_enable_pipestat()
243 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); in i915_enable_pipestat()
250 enum pipe pipe, u32 status_mask) in i915_disable_pipestat() argument
252 i915_reg_t reg = PIPESTAT(dev_priv, pipe); in i915_disable_pipestat()
256 "pipe %c: status_mask=0x%x\n", in i915_disable_pipestat()
257 pipe_name(pipe), status_mask); in i915_disable_pipestat()
262 if ((dev_priv->display.irq.pipestat_irq_mask[pipe] & status_mask) == 0) in i915_disable_pipestat()
265 dev_priv->display.irq.pipestat_irq_mask[pipe] &= ~status_mask; in i915_disable_pipestat()
266 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); in i915_disable_pipestat()
303 enum pipe pipe, in display_pipe_crc_irq_handler() argument
308 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); in display_pipe_crc_irq_handler()
338 enum pipe pipe, in display_pipe_crc_irq_handler() argument
345 enum pipe pipe) in flip_done_handler() argument
347 struct intel_crtc *crtc = intel_crtc_for_pipe(i915, pipe); in flip_done_handler()
361 enum pipe pipe) in hsw_pipe_crc_irq_handler() argument
363 display_pipe_crc_irq_handler(dev_priv, pipe, in hsw_pipe_crc_irq_handler()
364 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_HSW(pipe)), in hsw_pipe_crc_irq_handler()
369 enum pipe pipe) in ivb_pipe_crc_irq_handler() argument
371 display_pipe_crc_irq_handler(dev_priv, pipe, in ivb_pipe_crc_irq_handler()
372 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)), in ivb_pipe_crc_irq_handler()
373 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(pipe)), in ivb_pipe_crc_irq_handler()
374 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)), in ivb_pipe_crc_irq_handler()
375 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)), in ivb_pipe_crc_irq_handler()
376 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe))); in ivb_pipe_crc_irq_handler()
380 enum pipe pipe) in i9xx_pipe_crc_irq_handler() argument
386 PIPE_CRC_RES_RES1_I915(dev_priv, pipe)); in i9xx_pipe_crc_irq_handler()
392 PIPE_CRC_RES_RES2_G4X(dev_priv, pipe)); in i9xx_pipe_crc_irq_handler()
396 display_pipe_crc_irq_handler(dev_priv, pipe, in i9xx_pipe_crc_irq_handler()
397 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RED(dev_priv, pipe)), in i9xx_pipe_crc_irq_handler()
398 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_GREEN(dev_priv, pipe)), in i9xx_pipe_crc_irq_handler()
399 intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_BLUE(dev_priv, pipe)), in i9xx_pipe_crc_irq_handler()
405 enum pipe pipe; in i9xx_pipestat_irq_reset() local
407 for_each_pipe(dev_priv, pipe) { in i9xx_pipestat_irq_reset()
409 PIPESTAT(dev_priv, pipe), in i9xx_pipestat_irq_reset()
413 dev_priv->display.irq.pipestat_irq_mask[pipe] = 0; in i9xx_pipestat_irq_reset()
420 enum pipe pipe; in i9xx_pipestat_irq_ack() local
429 for_each_pipe(dev_priv, pipe) { in i9xx_pipestat_irq_ack()
444 switch (pipe) { in i9xx_pipestat_irq_ack()
457 status_mask |= dev_priv->display.irq.pipestat_irq_mask[pipe]; in i9xx_pipestat_irq_ack()
462 reg = PIPESTAT(dev_priv, pipe); in i9xx_pipestat_irq_ack()
463 pipe_stats[pipe] = intel_uncore_read(&dev_priv->uncore, reg) & status_mask; in i9xx_pipestat_irq_ack()
464 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); in i9xx_pipestat_irq_ack()
467 * Clear the PIPE*STAT regs before the IIR in i9xx_pipestat_irq_ack()
470 * edge in the ISR pipe event bit if we don't clear in i9xx_pipestat_irq_ack()
475 if (pipe_stats[pipe]) { in i9xx_pipestat_irq_ack()
476 intel_uncore_write(&dev_priv->uncore, reg, pipe_stats[pipe]); in i9xx_pipestat_irq_ack()
486 enum pipe pipe; in i8xx_pipestat_irq_handler() local
488 for_each_pipe(dev_priv, pipe) { in i8xx_pipestat_irq_handler()
489 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) in i8xx_pipestat_irq_handler()
490 intel_handle_vblank(dev_priv, pipe); in i8xx_pipestat_irq_handler()
492 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) in i8xx_pipestat_irq_handler()
493 i9xx_pipe_crc_irq_handler(dev_priv, pipe); in i8xx_pipestat_irq_handler()
495 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in i8xx_pipestat_irq_handler()
496 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in i8xx_pipestat_irq_handler()
506 enum pipe pipe; in i915_pipestat_irq_handler() local
508 for_each_pipe(dev_priv, pipe) { in i915_pipestat_irq_handler()
509 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) in i915_pipestat_irq_handler()
510 intel_handle_vblank(dev_priv, pipe); in i915_pipestat_irq_handler()
512 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) in i915_pipestat_irq_handler()
515 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) in i915_pipestat_irq_handler()
516 i9xx_pipe_crc_irq_handler(dev_priv, pipe); in i915_pipestat_irq_handler()
518 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in i915_pipestat_irq_handler()
519 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in i915_pipestat_irq_handler()
531 enum pipe pipe; in i965_pipestat_irq_handler() local
533 for_each_pipe(dev_priv, pipe) { in i965_pipestat_irq_handler()
534 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) in i965_pipestat_irq_handler()
535 intel_handle_vblank(dev_priv, pipe); in i965_pipestat_irq_handler()
537 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) in i965_pipestat_irq_handler()
540 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) in i965_pipestat_irq_handler()
541 i9xx_pipe_crc_irq_handler(dev_priv, pipe); in i965_pipestat_irq_handler()
543 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in i965_pipestat_irq_handler()
544 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in i965_pipestat_irq_handler()
557 enum pipe pipe; in valleyview_pipestat_irq_handler() local
559 for_each_pipe(dev_priv, pipe) { in valleyview_pipestat_irq_handler()
560 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS) in valleyview_pipestat_irq_handler()
561 intel_handle_vblank(dev_priv, pipe); in valleyview_pipestat_irq_handler()
563 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) in valleyview_pipestat_irq_handler()
564 flip_done_handler(dev_priv, pipe); in valleyview_pipestat_irq_handler()
566 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS) in valleyview_pipestat_irq_handler()
567 i9xx_pipe_crc_irq_handler(dev_priv, pipe); in valleyview_pipestat_irq_handler()
569 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) in valleyview_pipestat_irq_handler()
570 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in valleyview_pipestat_irq_handler()
580 enum pipe pipe; in ibx_irq_handler() local
608 for_each_pipe(dev_priv, pipe) in ibx_irq_handler()
609 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n", in ibx_irq_handler()
610 pipe_name(pipe), in ibx_irq_handler()
611 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe))); in ibx_irq_handler()
631 enum pipe pipe; in ivb_err_int_handler() local
636 for_each_pipe(dev_priv, pipe) { in ivb_err_int_handler()
637 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) in ivb_err_int_handler()
638 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in ivb_err_int_handler()
640 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) { in ivb_err_int_handler()
642 ivb_pipe_crc_irq_handler(dev_priv, pipe); in ivb_err_int_handler()
644 hsw_pipe_crc_irq_handler(dev_priv, pipe); in ivb_err_int_handler()
654 enum pipe pipe; in cpt_serr_int_handler() local
659 for_each_pipe(dev_priv, pipe) in cpt_serr_int_handler()
660 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe)) in cpt_serr_int_handler()
661 intel_pch_fifo_underrun_irq_handler(dev_priv, pipe); in cpt_serr_int_handler()
669 enum pipe pipe; in cpt_irq_handler() local
694 for_each_pipe(dev_priv, pipe) in cpt_irq_handler()
695 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n", in cpt_irq_handler()
696 pipe_name(pipe), in cpt_irq_handler()
697 intel_uncore_read(&dev_priv->uncore, FDI_RX_IIR(pipe))); in cpt_irq_handler()
707 enum pipe pipe; in ilk_display_irq_handler() local
722 for_each_pipe(dev_priv, pipe) { in ilk_display_irq_handler()
723 if (de_iir & DE_PIPE_VBLANK(pipe)) in ilk_display_irq_handler()
724 intel_handle_vblank(dev_priv, pipe); in ilk_display_irq_handler()
726 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) in ilk_display_irq_handler()
727 flip_done_handler(dev_priv, pipe); in ilk_display_irq_handler()
729 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe)) in ilk_display_irq_handler()
730 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in ilk_display_irq_handler()
732 if (de_iir & DE_PIPE_CRC_DONE(pipe)) in ilk_display_irq_handler()
733 i9xx_pipe_crc_irq_handler(dev_priv, pipe); in ilk_display_irq_handler()
756 enum pipe pipe; in ivb_display_irq_handler() local
785 for_each_pipe(dev_priv, pipe) { in ivb_display_irq_handler()
786 if (de_iir & DE_PIPE_VBLANK_IVB(pipe)) in ivb_display_irq_handler()
787 intel_handle_vblank(dev_priv, pipe); in ivb_display_irq_handler()
789 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) in ivb_display_irq_handler()
790 flip_done_handler(dev_priv, pipe); in ivb_display_irq_handler()
966 enum pipe pipe = INVALID_PIPE; in gen11_dsi_te_interrupt_handler() local
996 /* Get PIPE for handling VBLANK event */ in gen11_dsi_te_interrupt_handler()
1001 pipe = PIPE_A; in gen11_dsi_te_interrupt_handler()
1004 pipe = PIPE_B; in gen11_dsi_te_interrupt_handler()
1007 pipe = PIPE_C; in gen11_dsi_te_interrupt_handler()
1010 drm_err(&dev_priv->drm, "Invalid PIPE\n"); in gen11_dsi_te_interrupt_handler()
1014 intel_handle_vblank(dev_priv, pipe); in gen11_dsi_te_interrupt_handler()
1072 enum pipe pipe; in gen8_de_irq_handler() local
1150 for_each_pipe(dev_priv, pipe) { in gen8_de_irq_handler()
1153 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) in gen8_de_irq_handler()
1156 iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe)); in gen8_de_irq_handler()
1159 "The master control interrupt lied (DE PIPE)!\n"); in gen8_de_irq_handler()
1163 intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe), iir); in gen8_de_irq_handler()
1166 intel_handle_vblank(dev_priv, pipe); in gen8_de_irq_handler()
1169 flip_done_handler(dev_priv, pipe); in gen8_de_irq_handler()
1173 intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_0); in gen8_de_irq_handler()
1176 intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_1); in gen8_de_irq_handler()
1179 intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_2); in gen8_de_irq_handler()
1183 hsw_pipe_crc_irq_handler(dev_priv, pipe); in gen8_de_irq_handler()
1186 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe); in gen8_de_irq_handler()
1191 "Fault errors on pipe %c: 0x%08x\n", in gen8_de_irq_handler()
1192 pipe_name(pipe), in gen8_de_irq_handler()
1269 * we use as a pipe index
1274 enum pipe pipe = to_intel_crtc(crtc)->pipe; in i8xx_enable_vblank() local
1278 i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); in i8xx_enable_vblank()
1303 enum pipe pipe = to_intel_crtc(crtc)->pipe; in i965_enable_vblank() local
1307 i915_enable_pipestat(dev_priv, pipe, in i965_enable_vblank()
1317 enum pipe pipe = to_intel_crtc(crtc)->pipe; in ilk_enable_vblank() local
1320 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); in ilk_enable_vblank()
1363 enum pipe pipe = crtc->pipe; in bdw_enable_vblank() local
1370 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); in bdw_enable_vblank()
1383 * we use as a pipe index
1388 enum pipe pipe = to_intel_crtc(crtc)->pipe; in i8xx_disable_vblank() local
1392 i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS); in i8xx_disable_vblank()
1409 enum pipe pipe = to_intel_crtc(crtc)->pipe; in i965_disable_vblank() local
1413 i915_disable_pipestat(dev_priv, pipe, in i965_disable_vblank()
1421 enum pipe pipe = to_intel_crtc(crtc)->pipe; in ilk_disable_vblank() local
1424 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe); in ilk_disable_vblank()
1435 enum pipe pipe = crtc->pipe; in bdw_disable_vblank() local
1442 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK); in bdw_disable_vblank()
1470 enum pipe pipe; in vlv_display_irq_postinstall() local
1475 for_each_pipe(dev_priv, pipe) in vlv_display_irq_postinstall()
1476 i915_enable_pipestat(dev_priv, pipe, pipestat_mask); in vlv_display_irq_postinstall()
1498 enum pipe pipe; in gen8_display_irq_reset() local
1506 for_each_pipe(dev_priv, pipe) in gen8_display_irq_reset()
1508 POWER_DOMAIN_PIPE(pipe))) in gen8_display_irq_reset()
1509 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); in gen8_display_irq_reset()
1518 enum pipe pipe; in gen11_display_irq_reset() local
1549 for_each_pipe(dev_priv, pipe) in gen11_display_irq_reset()
1551 POWER_DOMAIN_PIPE(pipe))) in gen11_display_irq_reset()
1552 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); in gen11_display_irq_reset()
1573 enum pipe pipe; in gen8_irq_power_well_post_enable() local
1582 for_each_pipe_masked(dev_priv, pipe, pipe_mask) in gen8_irq_power_well_post_enable()
1583 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe, in gen8_irq_power_well_post_enable()
1584 dev_priv->display.irq.de_irq_mask[pipe], in gen8_irq_power_well_post_enable()
1585 ~dev_priv->display.irq.de_irq_mask[pipe] | extra_ier); in gen8_irq_power_well_post_enable()
1594 enum pipe pipe; in gen8_irq_power_well_pre_disable() local
1603 for_each_pipe_masked(dev_priv, pipe, pipe_mask) in gen8_irq_power_well_pre_disable()
1604 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe); in gen8_irq_power_well_pre_disable()
1726 enum pipe pipe; in gen8_de_irq_postinstall() local
1787 for_each_pipe(dev_priv, pipe) { in gen8_de_irq_postinstall()
1788 dev_priv->display.irq.de_irq_mask[pipe] = ~de_pipe_masked; in gen8_de_irq_postinstall()
1791 POWER_DOMAIN_PIPE(pipe))) in gen8_de_irq_postinstall()
1792 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe, in gen8_de_irq_postinstall()
1793 dev_priv->display.irq.de_irq_mask[pipe], in gen8_de_irq_postinstall()