418 			   u32 iir, u32 pipe_stats[I915_MAX_PIPES])  in i9xx_pipestat_irq_ack()  argument
456 		if (iir & iir_bit)  in i9xx_pipestat_irq_ack()
467 		 * Clear the PIPE*STAT regs before the IIR  in i9xx_pipestat_irq_ack()
472 		 * triggered IIR on i965/g4x wouldn't notice that  in i9xx_pipestat_irq_ack()
484 			       u16 iir, u32 pipe_stats[I915_MAX_PIPES])  in i8xx_pipestat_irq_handler()  argument
501 			       u32 iir, u32 pipe_stats[I915_MAX_PIPES])  in i915_pipestat_irq_handler()  argument
522 	if (blc_event || (iir & I915_ASLE_INTERRUPT))  in i915_pipestat_irq_handler()
527 			       u32 iir, u32 pipe_stats[I915_MAX_PIPES])  in i965_pipestat_irq_handler()  argument
547 	if (blc_event || (iir & I915_ASLE_INTERRUPT))  in i965_pipestat_irq_handler()
609 			drm_dbg(&dev_priv->drm, "  pipe %c FDI IIR: 0x%08x\n",  in ibx_irq_handler()
695 			drm_dbg(&dev_priv->drm, "  pipe %c FDI IIR: 0x%08x\n",  in cpt_irq_handler()
905 gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)  in gen8_de_misc_irq_handler()  argument
911 		if (iir & (XELPDP_PMDEMAND_RSP |  in gen8_de_misc_irq_handler()
913 			if (iir & XELPDP_PMDEMAND_RSPTOUT_ERR)  in gen8_de_misc_irq_handler()
921 		if (iir & XELPDP_RM_TIMEOUT) {  in gen8_de_misc_irq_handler()
927 	} else if (iir & GEN8_DE_MISC_GSE) {  in gen8_de_misc_irq_handler()
932 	if (iir & GEN8_DE_EDP_PSR) {  in gen8_de_misc_irq_handler()
960 		drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt: 0x%08x\n", iir);  in gen8_de_misc_irq_handler()
1016 	/* clear TE in dsi IIR */  in gen11_dsi_te_interrupt_handler()
1050 	 * PICA IER must be disabled/re-enabled around clearing PICA IIR and  in gen8_read_and_ack_pch_irqs()
1052 	 * their flags both in the PICA and SDE IIR.  in gen8_read_and_ack_pch_irqs()
1071 	u32 iir;  in gen8_de_irq_handler()  local
1077 		iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_MISC_IIR);  in gen8_de_irq_handler()
1078 		if (iir) {  in gen8_de_irq_handler()
1079 			intel_uncore_write(&dev_priv->uncore, GEN8_DE_MISC_IIR, iir);  in gen8_de_irq_handler()
1080 			gen8_de_misc_irq_handler(dev_priv, iir);  in gen8_de_irq_handler()
1088 		iir = intel_uncore_read(&dev_priv->uncore, GEN11_DE_HPD_IIR);  in gen8_de_irq_handler()
1089 		if (iir) {  in gen8_de_irq_handler()
1090 			intel_uncore_write(&dev_priv->uncore, GEN11_DE_HPD_IIR, iir);  in gen8_de_irq_handler()
1091 			gen11_hpd_irq_handler(dev_priv, iir);  in gen8_de_irq_handler()
1099 		iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PORT_IIR);  in gen8_de_irq_handler()
1100 		if (iir) {  in gen8_de_irq_handler()
1103 			intel_uncore_write(&dev_priv->uncore, GEN8_DE_PORT_IIR, iir);  in gen8_de_irq_handler()
1105 			if (iir & gen8_de_port_aux_mask(dev_priv)) {  in gen8_de_irq_handler()
1111 				u32 hotplug_trigger = iir & BXT_DE_PORT_HOTPLUG_MASK;  in gen8_de_irq_handler()
1118 				u32 hotplug_trigger = iir & BDW_DE_PORT_HOTPLUG_MASK;  in gen8_de_irq_handler()
1127 			    (iir & BXT_DE_PORT_GMBUS)) {  in gen8_de_irq_handler()
1133 				u32 te_trigger = iir & (DSI0_TE | DSI1_TE);  in gen8_de_irq_handler()
1156 		iir = intel_uncore_read(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe));  in gen8_de_irq_handler()
1157 		if (!iir) {  in gen8_de_irq_handler()
1163 		intel_uncore_write(&dev_priv->uncore, GEN8_DE_PIPE_IIR(pipe), iir);  in gen8_de_irq_handler()
1165 		if (iir & GEN8_PIPE_VBLANK)  in gen8_de_irq_handler()
1168 		if (iir & gen8_de_pipe_flip_done_mask(dev_priv))  in gen8_de_irq_handler()
1172 			if (iir & GEN12_DSB_INT(INTEL_DSB_0))  in gen8_de_irq_handler()
1175 			if (iir & GEN12_DSB_INT(INTEL_DSB_1))  in gen8_de_irq_handler()
1178 			if (iir & GEN12_DSB_INT(INTEL_DSB_2))  in gen8_de_irq_handler()
1182 		if (iir & GEN8_PIPE_CDCLK_CRC_DONE)  in gen8_de_irq_handler()
1185 		if (iir & gen8_de_pipe_underrun_mask(dev_priv))  in gen8_de_irq_handler()
1188 		fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);  in gen8_de_irq_handler()
1205 		gen8_read_and_ack_pch_irqs(dev_priv, &iir, &pica_iir);  in gen8_de_irq_handler()
1206 		if (iir) {  in gen8_de_irq_handler()
1211 				icp_irq_handler(dev_priv, iir);  in gen8_de_irq_handler()
1213 				spt_irq_handler(dev_priv, iir);  in gen8_de_irq_handler()
1215 				cpt_irq_handler(dev_priv, iir);  in gen8_de_irq_handler()
1230 	u32 iir;  in gen11_gu_misc_irq_ack()  local
1235 	iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);  in gen11_gu_misc_irq_ack()
1236 	if (likely(iir))  in gen11_gu_misc_irq_ack()
1237 		raw_reg_write(regs, GEN11_GU_MISC_IIR, iir);  in gen11_gu_misc_irq_ack()
1239 	return iir;  in gen11_gu_misc_irq_ack()
1242 void gen11_gu_misc_irq_handler(struct drm_i915_private *i915, const u32 iir)  in gen11_gu_misc_irq_handler()  argument
1246 	if (iir & GEN11_GU_MISC_GSE)  in gen11_gu_misc_irq_handler()