119 #define HAS_4TILE(i915)			(IS_DG2(i915) || DISPLAY_VER(i915) >= 14)  argument
120 #define HAS_ASYNC_FLIPS(i915)		(DISPLAY_VER(i915) >= 5)  argument
121 #define HAS_CDCLK_CRAWL(i915)		(DISPLAY_INFO(i915)->has_cdclk_crawl)  argument
122 #define HAS_CDCLK_SQUASH(i915)		(DISPLAY_INFO(i915)->has_cdclk_squash)  argument
123 #define HAS_CUR_FBC(i915)		(!HAS_GMCH(i915) && IS_DISPLAY_VER(i915, 7, 13))  argument
124 #define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || IS_ALDERLAKE_S(i915))  argument
125 #define HAS_DDI(i915)			(DISPLAY_INFO(i915)->has_ddi)  argument
126 #define HAS_DISPLAY(i915)		(DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0)  argument
127 #define HAS_DMC(i915)			(DISPLAY_RUNTIME_INFO(i915)->has_dmc)  argument
128 #define HAS_DOUBLE_BUFFERED_M_N(i915)	(DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915))  argument
129 #define HAS_DP_MST(i915)		(DISPLAY_INFO(i915)->has_dp_mst)  argument
130 #define HAS_DP20(i915)			(IS_DG2(i915) || DISPLAY_VER(i915) >= 14)  argument
131 #define HAS_DPT(i915)			(DISPLAY_VER(i915) >= 13)  argument
132 #define HAS_DSB(i915)			(DISPLAY_INFO(i915)->has_dsb)  argument
135 #define HAS_FBC(i915)			(DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0)  argument
136 #define HAS_FPGA_DBG_UNCLAIMED(i915)	(DISPLAY_INFO(i915)->has_fpga_dbg)  argument
137 #define HAS_FW_BLC(i915)		(DISPLAY_VER(i915) >= 3)  argument
138 #define HAS_GMBUS_IRQ(i915)		(DISPLAY_VER(i915) >= 4)  argument
139 #define HAS_GMBUS_BURST_READ(i915)	(DISPLAY_VER(i915) >= 10 || IS_KABYLAKE(i915))  argument
140 #define HAS_GMCH(i915)			(DISPLAY_INFO(i915)->has_gmch)  argument
141 #define HAS_HW_SAGV_WM(i915)		(DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))  argument
142 #define HAS_IPC(i915)			(DISPLAY_INFO(i915)->has_ipc)  argument
143 #define HAS_IPS(i915)			(IS_HASWELL_ULT(i915) || IS_BROADWELL(i915))  argument
144 #define HAS_LRR(i915)			(DISPLAY_VER(i915) >= 12)  argument
145 #define HAS_LSPCON(i915)		(IS_DISPLAY_VER(i915, 9, 10))  argument
146 #define HAS_MBUS_JOINING(i915)		(IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14)  argument
147 #define HAS_MSO(i915)			(DISPLAY_VER(i915) >= 12)  argument
148 #define HAS_OVERLAY(i915)		(DISPLAY_INFO(i915)->has_overlay)  argument
149 #define HAS_PSR(i915)			(DISPLAY_INFO(i915)->has_psr)  argument
150 #define HAS_PSR_HW_TRACKING(i915)	(DISPLAY_INFO(i915)->has_psr_hw_tracking)  argument
151 #define HAS_PSR2_SEL_FETCH(i915)	(DISPLAY_VER(i915) >= 12)  argument
152 #define HAS_SAGV(i915)			(DISPLAY_VER(i915) >= 9 && !IS_LP(i915))  argument
153 #define HAS_TRANSCODER(i915, trans)	((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \  argument
155 #define HAS_VRR(i915)			(DISPLAY_VER(i915) >= 11)  argument
156 #define HAS_AS_SDP(i915)		(DISPLAY_VER(i915) >= 13)  argument
157 #define HAS_CMRR(i915)			(DISPLAY_VER(i915) >= 20)  argument
158 #define INTEL_NUM_PIPES(i915)		(hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask))  argument
159 #define I915_HAS_HOTPLUG(i915)		(DISPLAY_INFO(i915)->has_hotplug)  argument
160 #define OVERLAY_NEEDS_PHYSICAL(i915)	(DISPLAY_INFO(i915)->overlay_needs_physical)  argument
161 #define SUPPORTS_TV(i915)		(DISPLAY_INFO(i915)->supports_tv)  argument
188 #define DISPLAY_INFO(i915)		(__to_intel_display(i915)->info.__device_info)  argument
189 #define DISPLAY_RUNTIME_INFO(i915)	(&__to_intel_display(i915)->info.__runtime_info)  argument
191 #define DISPLAY_VER(i915)	(DISPLAY_RUNTIME_INFO(i915)->ip.ver)  argument
192 #define DISPLAY_VER_FULL(i915)	IP_VER(DISPLAY_RUNTIME_INFO(i915)->ip.ver, \  argument
194 #define IS_DISPLAY_VER(i915, from, until) \  argument