Lines Matching +full:1 +full:- +full:bit
1 // SPDX-License-Identifier: MIT
22 __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for display info");
69 /* ICL DSI 0 and 1 */
209 .has_overlay = 1, \
210 .cursor_needs_physical = 1, \
211 .overlay_needs_physical = 1, \
212 .has_gmch = 1, \
218 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
220 BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
223 .has_overlay = 1, \
224 .overlay_needs_physical = 1, \
225 .has_gmch = 1, \
231 .__runtime_defaults.pipe_mask = BIT(PIPE_A), \
232 .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A)
239 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C), /* DVO A/B/C */
248 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
257 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
258 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
267 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
268 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
273 .has_gmch = 1, \
274 .has_overlay = 1, \
279 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
281 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
282 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) /* SDVO B/C */
289 .cursor_needs_physical = 1,
290 .overlay_needs_physical = 1,
299 .cursor_needs_physical = 1,
300 .overlay_needs_physical = 1,
301 .supports_tv = 1,
303 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
312 .has_hotplug = 1,
313 .cursor_needs_physical = 1,
314 .overlay_needs_physical = 1,
323 .has_hotplug = 1,
324 .cursor_needs_physical = 1,
325 .overlay_needs_physical = 1,
326 .supports_tv = 1,
328 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
337 .has_hotplug = 1,
346 .has_hotplug = 1,
351 .has_hotplug = 1, \
352 .has_gmch = 1, \
358 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
360 BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
366 .has_overlay = 1,
368 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */
376 .has_overlay = 1,
377 .supports_tv = 1,
379 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */
380 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
389 ….__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D…
397 .supports_tv = 1,
399 ….__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D…
400 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
405 .has_hotplug = 1, \
411 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
413 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
414 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) /* DP A, SDV…
428 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
435 .has_hotplug = 1,
441 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
443 BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
444 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SD…
445 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
452 .has_hotplug = 1,
458 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
460 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
461 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SD…
462 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
469 .has_gmch = 1,
470 .has_hotplug = 1,
477 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
479 BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
480 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* HDMI/DP B/C */
505 .has_ddi = 1,
506 .has_dp_mst = 1,
507 .has_fpga_dbg = 1,
508 .has_hotplug = 1,
509 .has_psr = 1,
510 .has_psr_hw_tracking = 1,
516 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
518 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
519 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
520 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E…
521 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
549 .has_ddi = 1,
550 .has_dp_mst = 1,
551 .has_fpga_dbg = 1,
552 .has_hotplug = 1,
553 .has_psr = 1,
554 .has_psr_hw_tracking = 1,
560 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
562 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
563 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
564 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E…
565 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
572 .has_hotplug = 1,
573 .has_gmch = 1,
580 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
582 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
583 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* HDMI/DP B/C/D */
588 .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */
589 .dbuf.slice_mask = BIT(DBUF_S1),
590 .has_ddi = 1,
591 .has_dp_mst = 1,
592 .has_fpga_dbg = 1,
593 .has_hotplug = 1,
594 .has_ipc = 1,
595 .has_psr = 1,
596 .has_psr_hw_tracking = 1,
602 .__runtime_defaults.has_dmc = 1,
603 .__runtime_defaults.has_hdcp = 1,
604 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
606 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
607 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
608 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E…
609 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
658 [1] = STEP_B0,
718 .dbuf.slice_mask = BIT(DBUF_S1), \
719 .has_dp_mst = 1, \
720 .has_ddi = 1, \
721 .has_fpga_dbg = 1, \
722 .has_hotplug = 1, \
723 .has_ipc = 1, \
724 .has_psr = 1, \
725 .has_psr_hw_tracking = 1, \
730 .__runtime_defaults.has_dmc = 1, \
731 .__runtime_defaults.has_hdcp = 1, \
732 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \
733 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
735 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
736 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
737 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
738 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C)
751 .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
766 .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
775 .abox_mask = BIT(0), \
777 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
778 .has_ddi = 1, \
779 .has_dp_mst = 1, \
780 .has_fpga_dbg = 1, \
781 .has_hotplug = 1, \
782 .has_ipc = 1, \
783 .has_psr = 1, \
784 .has_psr_hw_tracking = 1, \
805 .__runtime_defaults.has_dmc = 1, \
806 .__runtime_defaults.has_dsc = 1, \
807 .__runtime_defaults.has_hdcp = 1, \
808 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
810 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
811 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
812 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
813 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A)
833 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E…
841 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D),
846 [1] = STEP_B0,
862 .abox_mask = GENMASK(2, 1), \
864 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
865 .has_ddi = 1, \
866 .has_dp_mst = 1, \
867 .has_dsb = 1, \
868 .has_fpga_dbg = 1, \
869 .has_hotplug = 1, \
870 .has_ipc = 1, \
871 .has_psr = 1, \
872 .has_psr_hw_tracking = 1, \
893 .__runtime_defaults.has_dmc = 1, \
894 .__runtime_defaults.has_dsc = 1, \
895 .__runtime_defaults.has_hdcp = 1, \
897 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
899 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
900 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
901 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
902 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A)
911 [1] = STEP_D0,
916 [1] = STEP_C0,
935 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
936 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4) | BIT(PORT_TC5) | BIT(PORT_TC6),
943 [1] = STEP_B0,
951 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
952 BIT(PORT_TC1) | BIT(PORT_TC2),
959 [1] = STEP_B0,
967 .abox_mask = BIT(0),
968 .has_hti = 1,
971 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
973 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
974 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
975 BIT(PORT_TC1) | BIT(PORT_TC2),
1001 { INTEL_DISPLAY_ALDERLAKE_S_RAPTORLAKE_S, "RPL-S", adls_rpls_ids,
1007 .has_hti = 1,
1010 .__runtime_defaults.port_mask = BIT(PORT_A) |
1011 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
1017 .abox_mask = GENMASK(1, 0), \
1024 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
1025 BIT(DBUF_S4), \
1026 .has_ddi = 1, \
1027 .has_dp_mst = 1, \
1028 .has_dsb = 1, \
1029 .has_fpga_dbg = 1, \
1030 .has_hotplug = 1, \
1031 .has_ipc = 1, \
1032 .has_psr = 1, \
1052 .__runtime_defaults.has_dmc = 1, \
1053 .__runtime_defaults.has_dsc = 1, \
1054 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \
1055 .__runtime_defaults.has_hdcp = 1, \
1057 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
1061 .has_cdclk_crawl = 1,
1065 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
1066 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
1067 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
1068 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
1069 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
1105 { INTEL_DISPLAY_ALDERLAKE_P_ALDERLAKE_N, "ADL-N", adlp_adln_ids,
1107 { INTEL_DISPLAY_ALDERLAKE_P_RAPTORLAKE_P, "RPL-P", adlp_rplp_ids,
1109 { INTEL_DISPLAY_ALDERLAKE_P_RAPTORLAKE_U, "RPL-U", adlp_rplu_ids,
1119 .has_cdclk_squash = 1,
1122 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
1123 BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
1124 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D_XELPD) |
1125 BIT(PORT_TC1),
1176 .abox_mask = GENMASK(1, 0), \
1183 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
1184 BIT(DBUF_S4), \
1185 .has_cdclk_crawl = 1, \
1186 .has_cdclk_squash = 1, \
1187 .has_ddi = 1, \
1188 .has_dp_mst = 1, \
1189 .has_dsb = 1, \
1190 .has_fpga_dbg = 1, \
1191 .has_hotplug = 1, \
1192 .has_ipc = 1, \
1193 .has_psr = 1, \
1209 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
1210 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
1211 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B), \
1212 .__runtime_defaults.has_dmc = 1, \
1213 .__runtime_defaults.has_dsc = 1, \
1214 .__runtime_defaults.has_hdcp = 1, \
1216 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
1217 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | \
1218 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4)
1228 BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) |
1229 BIT(INTEL_FBC_C) | BIT(INTEL_FBC_D),
1234 .__runtime_defaults.port_mask = BIT(PORT_A) |
1235 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
1332 { 14, 1, &xe2_hpd_display },
1339 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); in probe_gmdid_display()
1347 drm_err(&i915->drm, "Cannot map MMIO BAR to read display GMD_ID\n"); in probe_gmdid_display()
1355 drm_dbg_kms(&i915->drm, "Device doesn't have display\n"); in probe_gmdid_display()
1371 drm_err(&i915->drm, "Unrecognized display IP version %d.%02d; disabling display.\n", in probe_gmdid_display()
1381 if (intel_display_ids[i].devid == pdev->device) in find_platform_desc()
1394 for (sp = desc->subplatforms; sp && sp->subplatform; sp++) in find_subplatform_desc()
1395 for (id = sp->pciidlist; *id; id++) in find_subplatform_desc()
1396 if (*id == pdev->device) in find_subplatform_desc()
1406 struct pci_dev *pdev = to_pci_dev(display->drm->dev); in get_pre_gmdid_step()
1407 const enum intel_step *map = main->map; in get_pre_gmdid_step()
1408 int size = main->size; in get_pre_gmdid_step()
1409 int revision = pdev->revision; in get_pre_gmdid_step()
1413 if (sub && sub->map && sub->size) { in get_pre_gmdid_step()
1414 map = sub->map; in get_pre_gmdid_step()
1415 size = sub->size; in get_pre_gmdid_step()
1425 drm_warn(display->drm, "Unknown revision 0x%02x\n", revision); in get_pre_gmdid_step()
1439 drm_dbg_kms(display->drm, "Using display stepping for revision 0x%02x\n", in get_pre_gmdid_step()
1443 drm_dbg_kms(display->drm, "Using future display stepping\n"); in get_pre_gmdid_step()
1448 drm_WARN_ON(display->drm, step == STEP_NONE); in get_pre_gmdid_step()
1455 struct intel_display *display = &i915->display; in intel_display_device_probe()
1456 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); in intel_display_device_probe()
1464 i915->display.drm = &i915->drm; in intel_display_device_probe()
1466 intel_display_params_copy(&i915->display.params); in intel_display_device_probe()
1469 drm_dbg_kms(&i915->drm, "Device doesn't have display\n"); in intel_display_device_probe()
1475 drm_dbg_kms(&i915->drm, "Unknown device ID %04x; disabling display.\n", in intel_display_device_probe()
1476 pdev->device); in intel_display_device_probe()
1480 info = desc->info; in intel_display_device_probe()
1489 &DISPLAY_INFO(i915)->__runtime_defaults, in intel_display_device_probe()
1492 drm_WARN_ON(&i915->drm, !desc->platform || !desc->name); in intel_display_device_probe()
1493 DISPLAY_RUNTIME_INFO(i915)->platform = desc->platform; in intel_display_device_probe()
1497 drm_WARN_ON(&i915->drm, !subdesc->subplatform || !subdesc->name); in intel_display_device_probe()
1498 DISPLAY_RUNTIME_INFO(i915)->subplatform = subdesc->subplatform; in intel_display_device_probe()
1502 DISPLAY_RUNTIME_INFO(i915)->ip = ip_ver; in intel_display_device_probe()
1505 drm_dbg_kms(display->drm, "Using future display stepping\n"); in intel_display_device_probe()
1509 step = get_pre_gmdid_step(display, &desc->step_info, in intel_display_device_probe()
1510 subdesc ? &subdesc->step_info : NULL); in intel_display_device_probe()
1513 DISPLAY_RUNTIME_INFO(i915)->step = step; in intel_display_device_probe()
1515 drm_info(&i915->drm, "Found %s%s%s (device ID %04x) display version %u.%02u stepping %s\n", in intel_display_device_probe()
1516 desc->name, subdesc ? "/" : "", subdesc ? subdesc->name : "", in intel_display_device_probe()
1517 pdev->device, DISPLAY_RUNTIME_INFO(i915)->ip.ver, in intel_display_device_probe()
1518 DISPLAY_RUNTIME_INFO(i915)->ip.rel, in intel_display_device_probe()
1529 intel_display_params_free(&i915->display.params); in intel_display_device_remove()
1537 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->pipe_mask) < I915_MAX_PIPES); in __intel_display_device_info_runtime_init()
1538 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->cpu_transcoder_mask) < I915_MAX_TRANSCODERS); in __intel_display_device_info_runtime_init()
1539 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->port_mask) < I915_MAX_PORTS); in __intel_display_device_info_runtime_init()
1543 display_runtime->port_mask &= ~BIT(PORT_D); in __intel_display_device_info_runtime_init()
1546 display_runtime->port_mask |= BIT(PORT_F); in __intel_display_device_info_runtime_init()
1548 /* Wa_14011765242: adl-s A0,A1 */ in __intel_display_device_info_runtime_init()
1551 display_runtime->num_scalers[pipe] = 0; in __intel_display_device_info_runtime_init()
1554 display_runtime->num_scalers[pipe] = 2; in __intel_display_device_info_runtime_init()
1556 display_runtime->num_scalers[PIPE_A] = 2; in __intel_display_device_info_runtime_init()
1557 display_runtime->num_scalers[PIPE_B] = 2; in __intel_display_device_info_runtime_init()
1558 display_runtime->num_scalers[PIPE_C] = 1; in __intel_display_device_info_runtime_init()
1563 display_runtime->num_sprites[pipe] = 4; in __intel_display_device_info_runtime_init()
1566 display_runtime->num_sprites[pipe] = 6; in __intel_display_device_info_runtime_init()
1569 display_runtime->num_sprites[pipe] = 3; in __intel_display_device_info_runtime_init()
1580 display_runtime->num_sprites[PIPE_A] = 2; in __intel_display_device_info_runtime_init()
1581 display_runtime->num_sprites[PIPE_B] = 2; in __intel_display_device_info_runtime_init()
1582 display_runtime->num_sprites[PIPE_C] = 1; in __intel_display_device_info_runtime_init()
1585 display_runtime->num_sprites[pipe] = 2; in __intel_display_device_info_runtime_init()
1588 display_runtime->num_sprites[pipe] = 1; in __intel_display_device_info_runtime_init()
1593 drm_info(&i915->drm, "Display not present, disabling\n"); in __intel_display_device_info_runtime_init()
1602 * SFUSE_STRAP is supposed to have a bit signalling the display in __intel_display_device_info_runtime_init()
1614 drm_info(&i915->drm, in __intel_display_device_info_runtime_init()
1618 drm_info(&i915->drm, "PipeC fused off\n"); in __intel_display_device_info_runtime_init()
1619 display_runtime->pipe_mask &= ~BIT(PIPE_C); in __intel_display_device_info_runtime_init()
1620 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); in __intel_display_device_info_runtime_init()
1626 display_runtime->pipe_mask &= ~BIT(PIPE_A); in __intel_display_device_info_runtime_init()
1627 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A); in __intel_display_device_info_runtime_init()
1628 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_A); in __intel_display_device_info_runtime_init()
1631 display_runtime->pipe_mask &= ~BIT(PIPE_B); in __intel_display_device_info_runtime_init()
1632 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B); in __intel_display_device_info_runtime_init()
1633 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_B); in __intel_display_device_info_runtime_init()
1636 display_runtime->pipe_mask &= ~BIT(PIPE_C); in __intel_display_device_info_runtime_init()
1637 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C); in __intel_display_device_info_runtime_init()
1638 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_C); in __intel_display_device_info_runtime_init()
1643 display_runtime->pipe_mask &= ~BIT(PIPE_D); in __intel_display_device_info_runtime_init()
1644 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D); in __intel_display_device_info_runtime_init()
1645 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_D); in __intel_display_device_info_runtime_init()
1648 if (!display_runtime->pipe_mask) in __intel_display_device_info_runtime_init()
1652 display_runtime->has_hdcp = 0; in __intel_display_device_info_runtime_init()
1655 display_runtime->fbc_mask = 0; in __intel_display_device_info_runtime_init()
1658 display_runtime->has_dmc = 0; in __intel_display_device_info_runtime_init()
1662 display_runtime->has_dsc = 0; in __intel_display_device_info_runtime_init()
1670 display_runtime->has_dsc = 0; in __intel_display_device_info_runtime_init()
1675 if (display_runtime->num_scalers[pipe]) in __intel_display_device_info_runtime_init()
1676 display_runtime->num_scalers[pipe] = 1; in __intel_display_device_info_runtime_init()
1680 display_runtime->rawclk_freq = intel_read_rawclk(i915); in __intel_display_device_info_runtime_init()
1681 drm_dbg_kms(&i915->drm, "rawclk rate: %d kHz\n", display_runtime->rawclk_freq); in __intel_display_device_info_runtime_init()
1696 i915->drm.driver_features &= ~(DRIVER_MODESET | DRIVER_ATOMIC); in intel_display_device_info_runtime_init()
1697 i915->display.info.__device_info = &no_display; in intel_display_device_info_runtime_init()
1700 /* Disable nuclear pageflip by default on pre-g4x */ in intel_display_device_info_runtime_init()
1701 if (!i915->display.params.nuclear_pageflip && in intel_display_device_info_runtime_init()
1703 i915->drm.driver_features &= ~DRIVER_ATOMIC; in intel_display_device_info_runtime_init()
1710 if (runtime->ip.rel) in intel_display_device_info_print()
1712 runtime->ip.ver, in intel_display_device_info_print()
1713 runtime->ip.rel); in intel_display_device_info_print()
1716 runtime->ip.ver); in intel_display_device_info_print()
1718 drm_printf(p, "display stepping: %s\n", intel_step_name(runtime->step)); in intel_display_device_info_print()
1720 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name)) in intel_display_device_info_print()
1724 drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp)); in intel_display_device_info_print()
1725 drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc)); in intel_display_device_info_print()
1726 drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc)); in intel_display_device_info_print()
1728 drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq); in intel_display_device_info_print()
1742 struct intel_display *display = &i915->display; in intel_display_device_enabled()
1745 drm_WARN_ON(display->drm, !HAS_DISPLAY(display)); in intel_display_device_enabled()
1747 return !display->params.disable_display && in intel_display_device_enabled()