2  * Copyright © 2006-2007 Intel Corporation
27 #include <linux/dma-resv.h>
161 	drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=  in vlv_get_cck_clock()
175 	if (dev_priv->hpll_freq == 0)  in vlv_get_cck_clock_hpll()
176 		dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);  in vlv_get_cck_clock_hpll()
178 	hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);  in vlv_get_cck_clock_hpll()
190 	dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",  in intel_update_czclk()
193 	drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",  in intel_update_czclk()
194 		dev_priv->czclk_freq);  in intel_update_czclk()
199 	return (crtc_state->active_planes &  in is_hdr_mode()
235 	return crtc_state->master_transcoder != INVALID_TRANSCODER;  in is_trans_port_sync_slave()
241 	return crtc_state->sync_mode_slaves_mask != 0;  in is_trans_port_sync_master()
253 	return ffs(crtc_state->joiner_pipes) - 1;  in joiner_primary_pipe()
258 	if (crtc_state->joiner_pipes)  in intel_crtc_joiner_secondary_pipes()
259 		return crtc_state->joiner_pipes & ~BIT(joiner_primary_pipe(crtc_state));  in intel_crtc_joiner_secondary_pipes()
266 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_is_joiner_secondary()
268 	return crtc_state->joiner_pipes &&  in intel_crtc_is_joiner_secondary()
269 		crtc->pipe != joiner_primary_pipe(crtc_state);  in intel_crtc_is_joiner_secondary()
274 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_is_joiner_primary()
276 	return crtc_state->joiner_pipes &&  in intel_crtc_is_joiner_primary()
277 		crtc->pipe == joiner_primary_pipe(crtc_state);  in intel_crtc_is_joiner_primary()
282 	return hweight8(crtc_state->joiner_pipes);  in intel_joiner_num_pipes()
287 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_joined_pipe_mask()
289 	return BIT(crtc->pipe) | crtc_state->joiner_pipes;  in intel_crtc_joined_pipe_mask()
294 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);  in intel_primary_crtc()
299 		return to_intel_crtc(crtc_state->uapi.crtc);  in intel_primary_crtc()
305 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);  in intel_wait_for_pipe_off()
306 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_wait_for_pipe_off()
309 		enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;  in intel_wait_for_pipe_off()
314 			drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");  in intel_wait_for_pipe_off()
351 	struct drm_i915_private *i915 = to_i915(plane->base.dev);  in assert_plane()
355 	cur_state = plane->get_hw_state(plane, &pipe);  in assert_plane()
359 			plane->base.name, str_on_off(state),  in assert_plane()
368 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in assert_planes_disabled()
371 	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)  in assert_planes_disabled()
382 	switch (dig_port->base.port) {  in vlv_wait_port_ready()
384 		MISSING_CASE(dig_port->base.port);  in vlv_wait_port_ready()
402 		drm_WARN(&dev_priv->drm, 1,  in vlv_wait_port_ready()
404 			 dig_port->base.base.base.id, dig_port->base.base.name,  in vlv_wait_port_ready()
411 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);  in intel_enable_transcoder()
412 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_enable_transcoder()
413 	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;  in intel_enable_transcoder()
414 	enum pipe pipe = crtc->pipe;  in intel_enable_transcoder()
417 	drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));  in intel_enable_transcoder()
432 		if (new_crtc_state->has_pch_encoder) {  in intel_enable_transcoder()
442 	/* Wa_22012358565:adl-p */  in intel_enable_transcoder()
462 		drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));  in intel_enable_transcoder()
468 	    new_crtc_state->dsc.compression_enable) {  in intel_enable_transcoder()
491 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);  in intel_disable_transcoder()
492 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_disable_transcoder()
493 	enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;  in intel_disable_transcoder()
494 	enum pipe pipe = crtc->pipe;  in intel_disable_transcoder()
497 	drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));  in intel_disable_transcoder()
513 	if (old_crtc_state->double_wide)  in intel_disable_transcoder()
522 	    old_crtc_state->dsc.compression_enable)  in intel_disable_transcoder()
540 	for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)  in intel_rotation_info_size()
541 		size += rot_info->plane[i].dst_stride * rot_info->plane[i].width;  in intel_rotation_info_size()
551 	for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {  in intel_remapped_info_size()
554 		if (rem_info->plane[i].linear)  in intel_remapped_info_size()
555 			plane_size = rem_info->plane[i].size;  in intel_remapped_info_size()
557 			plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height;  in intel_remapped_info_size()
562 		if (rem_info->plane_alignment)  in intel_remapped_info_size()
563 			size = ALIGN(size, rem_info->plane_alignment);  in intel_remapped_info_size()
573 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);  in intel_plane_uses_fence()
574 	struct drm_i915_private *dev_priv = to_i915(plane->base.dev);  in intel_plane_uses_fence()
577 		(plane->fbc && !plane_state->no_fbc_reason &&  in intel_plane_uses_fence()
578 		 plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL);  in intel_plane_uses_fence()
584  * offset is only used with linear buffers on pre-hsw and tiled buffers
591 	const struct drm_framebuffer *fb = state->hw.fb;  in intel_fb_xy_to_linear()
592 	unsigned int cpp = fb->format->cpp[color_plane];  in intel_fb_xy_to_linear()
593 	unsigned int pitch = state->view.color_plane[color_plane].mapping_stride;  in intel_fb_xy_to_linear()
599  * Add the x/y offsets derived from fb->offsets[] to the user
608 	*x += state->view.color_plane[color_plane].x;  in intel_add_fb_offsets()
609 	*y += state->view.color_plane[color_plane].y;  in intel_add_fb_offsets()
630 	plane = to_intel_plane(crtc->base.primary);  in intel_plane_fb_max_stride()
632 	return plane->max_stride(plane, pixel_format, modifier,  in intel_plane_fb_max_stride()
640 	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);  in intel_set_plane_visible()
642 	plane_state->uapi.visible = visible;  in intel_set_plane_visible()
645 		crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);  in intel_set_plane_visible()
647 		crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);  in intel_set_plane_visible()
652 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in intel_plane_fixup_bitmasks()
660 	crtc_state->enabled_planes = 0;  in intel_plane_fixup_bitmasks()
661 	crtc_state->active_planes = 0;  in intel_plane_fixup_bitmasks()
663 	drm_for_each_plane_mask(plane, &dev_priv->drm,  in intel_plane_fixup_bitmasks()
664 				crtc_state->uapi.plane_mask) {  in intel_plane_fixup_bitmasks()
665 		crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);  in intel_plane_fixup_bitmasks()
666 		crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);  in intel_plane_fixup_bitmasks()
673 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_plane_disable_noatomic()
675 		to_intel_crtc_state(crtc->base.state);  in intel_plane_disable_noatomic()
677 		to_intel_plane_state(plane->base.state);  in intel_plane_disable_noatomic()
679 	drm_dbg_kms(&dev_priv->drm,  in intel_plane_disable_noatomic()
681 		    plane->base.base.id, plane->base.name,  in intel_plane_disable_noatomic()
682 		    crtc->base.base.id, crtc->base.name);  in intel_plane_disable_noatomic()
686 	crtc_state->data_rate[plane->id] = 0;  in intel_plane_disable_noatomic()
687 	crtc_state->data_rate_y[plane->id] = 0;  in intel_plane_disable_noatomic()
688 	crtc_state->rel_data_rate[plane->id] = 0;  in intel_plane_disable_noatomic()
689 	crtc_state->rel_data_rate_y[plane->id] = 0;  in intel_plane_disable_noatomic()
690 	crtc_state->min_cdclk[plane->id] = 0;  in intel_plane_disable_noatomic()
692 	if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&  in intel_plane_disable_noatomic()
694 		crtc_state->ips_enabled = false;  in intel_plane_disable_noatomic()
700 	 * are blocked if the memory self-refresh mode is active at that  in intel_plane_disable_noatomic()
702 	 * first the self-refresh mode. The self-refresh enable bit in turn  in intel_plane_disable_noatomic()
705 	 * wait-for-vblank between disabling the plane and the pipe.  in intel_plane_disable_noatomic()
715 	if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)  in intel_plane_disable_noatomic()
716 		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);  in intel_plane_disable_noatomic()
728 					  plane_state->view.color_plane[0].offset, 0);  in intel_plane_fence_y_offset()
735 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in icl_set_pipe_chicken()
736 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in icl_set_pipe_chicken()
737 	enum pipe pipe = crtc->pipe;  in icl_set_pipe_chicken()
745 	 * and rounding for per-pixel values 00 and 0xff  in icl_set_pipe_chicken()
777 	drm_for_each_crtc(crtc, &dev_priv->drm) {  in intel_has_pending_fb_unpin()
779 		spin_lock(&crtc->commit_lock);  in intel_has_pending_fb_unpin()
780 		commit = list_first_entry_or_null(&crtc->commit_list,  in intel_has_pending_fb_unpin()
783 			try_wait_for_completion(&commit->cleanup_done) : true;  in intel_has_pending_fb_unpin()
784 		spin_unlock(&crtc->commit_lock);  in intel_has_pending_fb_unpin()
814 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in intel_get_crtc_new_encoder()
815 		if (connector_state->crtc != &primary_crtc->base)  in intel_get_crtc_new_encoder()
818 		encoder = to_intel_encoder(connector_state->best_encoder);  in intel_get_crtc_new_encoder()
822 	drm_WARN(state->base.dev, num_encoders != 1,  in intel_get_crtc_new_encoder()
824 		 num_encoders, pipe_name(primary_crtc->pipe));  in intel_get_crtc_new_encoder()
831 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in ilk_pfit_enable()
832 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_pfit_enable()
833 	const struct drm_rect *dst = &crtc_state->pch_pfit.dst;  in ilk_pfit_enable()
834 	enum pipe pipe = crtc->pipe;  in ilk_pfit_enable()
837 	int x = dst->x1;  in ilk_pfit_enable()
838 	int y = dst->y1;  in ilk_pfit_enable()
840 	if (!crtc_state->pch_pfit.enabled)  in ilk_pfit_enable()
843 	/* Force use of hard-coded filter coefficients  in ilk_pfit_enable()
844 	 * as some pre-programmed values are broken,  in ilk_pfit_enable()
861 	if (crtc->overlay)  in intel_crtc_dpms_overlay_disable()
862 		(void) intel_overlay_switch_off(crtc->overlay);  in intel_crtc_dpms_overlay_disable()
871 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in needs_nv12_wa()
873 	if (!crtc_state->nv12_planes)  in needs_nv12_wa()
885 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in needs_scalerclk_wa()
888 	if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11)  in needs_scalerclk_wa()
896 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in needs_cursorclk_wa()
900 	    crtc_state->active_planes & BIT(PLANE_CURSOR) &&  in needs_cursorclk_wa()
928 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);  in needs_async_flip_vtd_wa()
930 	return crtc_state->uapi.async_flip && i915_vtd_active(i915) &&  in needs_async_flip_vtd_wa()
943 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_audio_enable()
945 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_audio_enable()
947 		if (conn_state->crtc != &crtc->base)  in intel_encoders_audio_enable()
950 		if (encoder->audio_enable)  in intel_encoders_audio_enable()
951 			encoder->audio_enable(encoder, crtc_state, conn_state);  in intel_encoders_audio_enable()
964 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {  in intel_encoders_audio_disable()
966 			to_intel_encoder(old_conn_state->best_encoder);  in intel_encoders_audio_disable()
968 		if (old_conn_state->crtc != &crtc->base)  in intel_encoders_audio_disable()
971 		if (encoder->audio_disable)  in intel_encoders_audio_disable()
972 			encoder->audio_disable(encoder, old_crtc_state, old_conn_state);  in intel_encoders_audio_disable()
977 	((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \
978 	 (new_crtc_state)->feature)
980 	((old_crtc_state)->feature && \
981 	 (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)))
986 	if (!new_crtc_state->hw.active)  in planes_enabling()
995 	if (!old_crtc_state->hw.active)  in planes_disabling()
1004 	return old_crtc_state->vrr.flipline != new_crtc_state->vrr.flipline ||  in vrr_params_changed()
1005 		old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin ||  in vrr_params_changed()
1006 		old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax ||  in vrr_params_changed()
1007 		old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband ||  in vrr_params_changed()
1008 		old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full;  in vrr_params_changed()
1014 	return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||  in cmrr_params_changed()
1015 		old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;  in cmrr_params_changed()
1026 	if (!new_crtc_state->hw.active)  in intel_crtc_vrr_enabling()
1030 		(new_crtc_state->vrr.enable &&  in intel_crtc_vrr_enabling()
1031 		 (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||  in intel_crtc_vrr_enabling()
1043 	if (!old_crtc_state->hw.active)  in intel_crtc_vrr_disabling()
1047 		(old_crtc_state->vrr.enable &&  in intel_crtc_vrr_disabling()
1048 		 (new_crtc_state->update_m_n || new_crtc_state->update_lrr ||  in intel_crtc_vrr_disabling()
1055 	if (!new_crtc_state->hw.active)  in audio_enabling()
1059 		(new_crtc_state->has_audio &&  in audio_enabling()
1060 		 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0);  in audio_enabling()
1066 	if (!old_crtc_state->hw.active)  in audio_disabling()
1070 		(old_crtc_state->has_audio &&  in audio_disabling()
1071 		 memcmp(old_crtc_state->eld, new_crtc_state->eld, MAX_ELD_BYTES) != 0);  in audio_disabling()
1080 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_post_plane_update()
1085 	enum pipe pipe = crtc->pipe;  in intel_post_plane_update()
1089 	intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);  in intel_post_plane_update()
1091 	if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)  in intel_post_plane_update()
1124 	u8 update_planes = crtc_state->update_planes;  in intel_crtc_enable_flip_done()
1130 		if (plane->pipe == crtc->pipe &&  in intel_crtc_enable_flip_done()
1131 		    update_planes & BIT(plane->id))  in intel_crtc_enable_flip_done()
1132 			plane->enable_flip_done(plane);  in intel_crtc_enable_flip_done()
1141 	u8 update_planes = crtc_state->update_planes;  in intel_crtc_disable_flip_done()
1147 		if (plane->pipe == crtc->pipe &&  in intel_crtc_disable_flip_done()
1148 		    update_planes & BIT(plane->id))  in intel_crtc_disable_flip_done()
1149 			plane->disable_flip_done(plane);  in intel_crtc_disable_flip_done()
1160 	u8 disable_async_flip_planes = old_crtc_state->async_flip_planes &  in intel_crtc_async_flip_disable_wa()
1161 				       ~new_crtc_state->async_flip_planes;  in intel_crtc_async_flip_disable_wa()
1168 		if (plane->need_async_flip_toggle_wa &&  in intel_crtc_async_flip_disable_wa()
1169 		    plane->pipe == crtc->pipe &&  in intel_crtc_async_flip_disable_wa()
1170 		    disable_async_flip_planes & BIT(plane->id)) {  in intel_crtc_async_flip_disable_wa()
1188 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_pre_plane_update()
1193 	enum pipe pipe = crtc->pipe;  in intel_pre_plane_update()
1234 	 * are blocked if the memory self-refresh mode is active at that  in intel_pre_plane_update()
1236 	 * first the self-refresh mode. The self-refresh enable bit in turn  in intel_pre_plane_update()
1239 	 * wait-for-vblank between disabling the plane and the pipe.  in intel_pre_plane_update()
1241 	if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&  in intel_pre_plane_update()
1242 	    new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))  in intel_pre_plane_update()
1247 	 * one frame before enabling scaling.  LP watermarks can be re-enabled  in intel_pre_plane_update()
1252 	if (old_crtc_state->hw.active &&  in intel_pre_plane_update()
1253 	    new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))  in intel_pre_plane_update()
1258 	 * pre-vblank watermark programming here.  in intel_pre_plane_update()
1263 		 * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these  in intel_pre_plane_update()
1264 		 * will be the intermediate values that are safe for both pre- and  in intel_pre_plane_update()
1265 		 * post- vblank; when vblank happens, the 'active' values will be set  in intel_pre_plane_update()
1276 			if (new_crtc_state->update_wm_pre)  in intel_pre_plane_update()
1295 	if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes)  in intel_pre_plane_update()
1302 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_crtc_disable_planes()
1305 	unsigned int update_mask = new_crtc_state->update_planes;  in intel_crtc_disable_planes()
1314 		if (crtc->pipe != plane->pipe ||  in intel_crtc_disable_planes()
1315 		    !(update_mask & BIT(plane->id)))  in intel_crtc_disable_planes()
1320 		if (old_plane_state->uapi.visible)  in intel_crtc_disable_planes()
1321 			fb_bits |= plane->frontbuffer_bit;  in intel_crtc_disable_planes()
1329 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_encoders_update_prepare()
1335 	 * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.  in intel_encoders_update_prepare()
1336 	 * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.  in intel_encoders_update_prepare()
1338 	if (i915->display.dpll.mgr) {  in intel_encoders_update_prepare()
1343 			new_crtc_state->shared_dpll = old_crtc_state->shared_dpll;  in intel_encoders_update_prepare()
1344 			new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;  in intel_encoders_update_prepare()
1358 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_pre_pll_enable()
1360 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_pre_pll_enable()
1362 		if (conn_state->crtc != &crtc->base)  in intel_encoders_pre_pll_enable()
1365 		if (encoder->pre_pll_enable)  in intel_encoders_pre_pll_enable()
1366 			encoder->pre_pll_enable(state, encoder,  in intel_encoders_pre_pll_enable()
1380 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_pre_enable()
1382 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_pre_enable()
1384 		if (conn_state->crtc != &crtc->base)  in intel_encoders_pre_enable()
1387 		if (encoder->pre_enable)  in intel_encoders_pre_enable()
1388 			encoder->pre_enable(state, encoder,  in intel_encoders_pre_enable()
1402 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_enable()
1404 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_enable()
1406 		if (conn_state->crtc != &crtc->base)  in intel_encoders_enable()
1409 		if (encoder->enable)  in intel_encoders_enable()
1410 			encoder->enable(state, encoder,  in intel_encoders_enable()
1425 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {  in intel_encoders_disable()
1427 			to_intel_encoder(old_conn_state->best_encoder);  in intel_encoders_disable()
1429 		if (old_conn_state->crtc != &crtc->base)  in intel_encoders_disable()
1433 		if (encoder->disable)  in intel_encoders_disable()
1434 			encoder->disable(state, encoder,  in intel_encoders_disable()
1448 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {  in intel_encoders_post_disable()
1450 			to_intel_encoder(old_conn_state->best_encoder);  in intel_encoders_post_disable()
1452 		if (old_conn_state->crtc != &crtc->base)  in intel_encoders_post_disable()
1455 		if (encoder->post_disable)  in intel_encoders_post_disable()
1456 			encoder->post_disable(state, encoder,  in intel_encoders_post_disable()
1470 	for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {  in intel_encoders_post_pll_disable()
1472 			to_intel_encoder(old_conn_state->best_encoder);  in intel_encoders_post_pll_disable()
1474 		if (old_conn_state->crtc != &crtc->base)  in intel_encoders_post_pll_disable()
1477 		if (encoder->post_pll_disable)  in intel_encoders_post_pll_disable()
1478 			encoder->post_pll_disable(state, encoder,  in intel_encoders_post_pll_disable()
1492 	for_each_new_connector_in_state(&state->base, conn, conn_state, i) {  in intel_encoders_update_pipe()
1494 			to_intel_encoder(conn_state->best_encoder);  in intel_encoders_update_pipe()
1496 		if (conn_state->crtc != &crtc->base)  in intel_encoders_update_pipe()
1499 		if (encoder->update_pipe)  in intel_encoders_update_pipe()
1500 			encoder->update_pipe(state, encoder,  in intel_encoders_update_pipe()
1507 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_disable_primary_plane()
1508 	struct intel_plane *plane = to_intel_plane(crtc->base.primary);  in intel_disable_primary_plane()
1510 	plane->disable_arm(plane, crtc_state);  in intel_disable_primary_plane()
1515 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in ilk_configure_cpu_transcoder()
1516 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in ilk_configure_cpu_transcoder()
1518 	if (crtc_state->has_pch_encoder) {  in ilk_configure_cpu_transcoder()
1520 					       &crtc_state->fdi_m_n);  in ilk_configure_cpu_transcoder()
1523 					       &crtc_state->dp_m_n);  in ilk_configure_cpu_transcoder()
1525 					       &crtc_state->dp_m2_n2);  in ilk_configure_cpu_transcoder()
1538 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_crtc_enable()
1539 	enum pipe pipe = crtc->pipe;  in ilk_crtc_enable()
1541 	if (drm_WARN_ON(&dev_priv->drm, crtc->active))  in ilk_crtc_enable()
1561 	crtc->active = true;  in ilk_crtc_enable()
1565 	if (new_crtc_state->has_pch_encoder) {  in ilk_crtc_enable()
1587 	if (new_crtc_state->has_pch_encoder)  in ilk_crtc_enable()
1603 	if (new_crtc_state->has_pch_encoder) {  in ilk_crtc_enable()
1614 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);  in glk_need_scaler_clock_gating_wa()
1616 	return DISPLAY_VER(i915) == 10 && crtc_state->pch_pfit.enabled;  in glk_need_scaler_clock_gating_wa()
1621 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in glk_pipe_scaler_clock_gating_wa()
1624 	intel_de_rmw(i915, CLKGATE_DIS_PSL(crtc->pipe),  in glk_pipe_scaler_clock_gating_wa()
1630 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_set_linetime_wm()
1631 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_set_linetime_wm()
1633 	intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),  in hsw_set_linetime_wm()
1634 		       HSW_LINETIME(crtc_state->linetime) |  in hsw_set_linetime_wm()
1635 		       HSW_IPS_LINETIME(crtc_state->ips_linetime));  in hsw_set_linetime_wm()
1640 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_set_frame_start_delay()
1641 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in hsw_set_frame_start_delay()
1643 	intel_de_rmw(i915, hsw_chicken_trans_reg(i915, crtc_state->cpu_transcoder),  in hsw_set_frame_start_delay()
1645 		     HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1));  in hsw_set_frame_start_delay()
1650 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_configure_cpu_transcoder()
1651 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_configure_cpu_transcoder()
1652 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in hsw_configure_cpu_transcoder()
1654 	if (crtc_state->has_pch_encoder) {  in hsw_configure_cpu_transcoder()
1656 					       &crtc_state->fdi_m_n);  in hsw_configure_cpu_transcoder()
1659 					       &crtc_state->dp_m_n);  in hsw_configure_cpu_transcoder()
1661 					       &crtc_state->dp_m2_n2);  in hsw_configure_cpu_transcoder()
1670 			       crtc_state->pixel_multiplier - 1);  in hsw_configure_cpu_transcoder()
1682 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_crtc_enable()
1683 	enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;  in hsw_crtc_enable()
1686 	if (drm_WARN_ON(&dev_priv->drm, crtc->active))  in hsw_crtc_enable()
1689 	for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,  in hsw_crtc_enable()
1691 		intel_dmc_enable_pipe(dev_priv, pipe_crtc->pipe);  in hsw_crtc_enable()
1695 	for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,  in hsw_crtc_enable()
1700 		if (pipe_crtc_state->shared_dpll)  in hsw_crtc_enable()
1706 	for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,  in hsw_crtc_enable()
1725 	for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,  in hsw_crtc_enable()
1730 		pipe_crtc->active = true;  in hsw_crtc_enable()
1761 	for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,  in hsw_crtc_enable()
1776 		hsw_workaround_pipe = pipe_crtc_state->hsw_workaround_pipe;  in hsw_crtc_enable()
1789 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);  in ilk_pfit_disable()
1790 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_pfit_disable()
1791 	enum pipe pipe = crtc->pipe;  in ilk_pfit_disable()
1795 	if (!old_crtc_state->pch_pfit.enabled)  in ilk_pfit_disable()
1808 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_crtc_disable()
1809 	enum pipe pipe = crtc->pipe;  in ilk_crtc_disable()
1827 	if (old_crtc_state->has_pch_encoder)  in ilk_crtc_disable()
1832 	if (old_crtc_state->has_pch_encoder)  in ilk_crtc_disable()
1846 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in hsw_crtc_disable()
1851 	 * Need care with mst->ddi interactions.  in hsw_crtc_disable()
1856 	for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc,  in hsw_crtc_disable()
1866 	for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc,  in hsw_crtc_disable()
1868 		intel_dmc_disable_pipe(i915, pipe_crtc->pipe);  in hsw_crtc_disable()
1873 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in i9xx_pfit_enable()
1874 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_pfit_enable()
1876 	if (!crtc_state->gmch_pfit.control)  in i9xx_pfit_enable()
1883 	drm_WARN_ON(&dev_priv->drm,  in i9xx_pfit_enable()
1885 	assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);  in i9xx_pfit_enable()
1888 		       crtc_state->gmch_pfit.pgm_ratios);  in i9xx_pfit_enable()
1890 		       crtc_state->gmch_pfit.control);  in i9xx_pfit_enable()
1894 	intel_de_write(dev_priv, BCLRPAT(dev_priv, crtc->pipe), 0);  in i9xx_pfit_enable()
1924 	 * subsystem Legacy or non-legacy, and only support native DP/HDMI  in intel_phy_is_tc()
1953 		return PHY_D + port - PORT_D_XELPD;  in intel_port_to_phy()
1955 		return PHY_F + port - PORT_TC1;  in intel_port_to_phy()
1957 		return PHY_B + port - PORT_TC1;  in intel_port_to_phy()
1959 		return PHY_C + port - PORT_TC1;  in intel_port_to_phy()
1964 	return PHY_A + port - PORT_A;  in intel_port_to_phy()
1974 		return TC_PORT_1 + port - PORT_TC1;  in intel_port_to_tc()
1976 		return TC_PORT_1 + port - PORT_C;  in intel_port_to_tc()
1981 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_encoder_to_phy()
1983 	return intel_port_to_phy(i915, encoder->port);  in intel_encoder_to_phy()
1988 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_encoder_is_combo()
1995 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_encoder_is_snps()
2002 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_encoder_is_tc()
2009 	struct drm_i915_private *i915 = to_i915(encoder->base.dev);  in intel_encoder_to_tc()
2011 	return intel_port_to_tc(i915, encoder->port);  in intel_encoder_to_tc()
2017 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);  in intel_aux_power_domain()
2020 		return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch);  in intel_aux_power_domain()
2022 	return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch);  in intel_aux_power_domain()
2028 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in get_crtc_power_domains()
2029 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in get_crtc_power_domains()
2030 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in get_crtc_power_domains()
2032 	enum pipe pipe = crtc->pipe;  in get_crtc_power_domains()
2034 	bitmap_zero(mask->bits, POWER_DOMAIN_NUM);  in get_crtc_power_domains()
2036 	if (!crtc_state->hw.active)  in get_crtc_power_domains()
2039 	set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);  in get_crtc_power_domains()
2040 	set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);  in get_crtc_power_domains()
2041 	if (crtc_state->pch_pfit.enabled ||  in get_crtc_power_domains()
2042 	    crtc_state->pch_pfit.force_thru)  in get_crtc_power_domains()
2043 		set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);  in get_crtc_power_domains()
2045 	drm_for_each_encoder_mask(encoder, &dev_priv->drm,  in get_crtc_power_domains()
2046 				  crtc_state->uapi.encoder_mask) {  in get_crtc_power_domains()
2049 		set_bit(intel_encoder->power_domain, mask->bits);  in get_crtc_power_domains()
2052 	if (HAS_DDI(dev_priv) && crtc_state->has_audio)  in get_crtc_power_domains()
2053 		set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);  in get_crtc_power_domains()
2055 	if (crtc_state->shared_dpll)  in get_crtc_power_domains()
2056 		set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);  in get_crtc_power_domains()
2058 	if (crtc_state->dsc.compression_enable)  in get_crtc_power_domains()
2059 		set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);  in get_crtc_power_domains()
2065 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_modeset_get_crtc_power_domains()
2066 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_modeset_get_crtc_power_domains()
2074 		      crtc->enabled_power_domains.mask.bits,  in intel_modeset_get_crtc_power_domains()
2076 	bitmap_andnot(old_domains->bits,  in intel_modeset_get_crtc_power_domains()
2077 		      crtc->enabled_power_domains.mask.bits,  in intel_modeset_get_crtc_power_domains()
2083 					       &crtc->enabled_power_domains,  in intel_modeset_get_crtc_power_domains()
2090 	intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),  in intel_modeset_put_crtc_power_domains()
2091 					    &crtc->enabled_power_domains,  in intel_modeset_put_crtc_power_domains()
2097 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in i9xx_configure_cpu_transcoder()
2098 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in i9xx_configure_cpu_transcoder()
2102 					       &crtc_state->dp_m_n);  in i9xx_configure_cpu_transcoder()
2104 					       &crtc_state->dp_m2_n2);  in i9xx_configure_cpu_transcoder()
2117 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in valleyview_crtc_enable()
2118 	enum pipe pipe = crtc->pipe;  in valleyview_crtc_enable()
2120 	if (drm_WARN_ON(&dev_priv->drm, crtc->active))  in valleyview_crtc_enable()
2135 	crtc->active = true;  in valleyview_crtc_enable()
2169 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_crtc_enable()
2170 	enum pipe pipe = crtc->pipe;  in i9xx_crtc_enable()
2172 	if (drm_WARN_ON(&dev_priv->drm, crtc->active))  in i9xx_crtc_enable()
2179 	crtc->active = true;  in i9xx_crtc_enable()
2211 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);  in i9xx_pfit_disable()
2212 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_pfit_disable()
2214 	if (!old_crtc_state->gmch_pfit.control)  in i9xx_pfit_disable()
2217 	assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);  in i9xx_pfit_disable()
2219 	drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",  in i9xx_pfit_disable()
2229 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_crtc_disable()
2230 	enum pipe pipe = crtc->pipe;  in i9xx_crtc_disable()
2263 	if (!dev_priv->display.funcs.wm->initial_watermarks)  in i9xx_crtc_disable()
2281 	const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_crtc_supports_double_wide()
2285 		(crtc->pipe == PIPE_A || IS_I915G(dev_priv));  in intel_crtc_supports_double_wide()
2290 	u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;  in ilk_pipe_pixel_rate()
2294 	 * We only use IF-ID interlacing. If we ever use  in ilk_pipe_pixel_rate()
2295 	 * PF-ID we'll need to adjust the pixel_rate here.  in ilk_pipe_pixel_rate()
2298 	if (!crtc_state->pch_pfit.enabled)  in ilk_pipe_pixel_rate()
2302 		      drm_rect_width(&crtc_state->pipe_src) << 16,  in ilk_pipe_pixel_rate()
2303 		      drm_rect_height(&crtc_state->pipe_src) << 16);  in ilk_pipe_pixel_rate()
2305 	return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,  in ilk_pipe_pixel_rate()
2309 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,  in intel_mode_from_crtc_timings()  argument
2312 	mode->hdisplay = timings->crtc_hdisplay;  in intel_mode_from_crtc_timings()
2313 	mode->htotal = timings->crtc_htotal;  in intel_mode_from_crtc_timings()
2314 	mode->hsync_start = timings->crtc_hsync_start;  in intel_mode_from_crtc_timings()
2315 	mode->hsync_end = timings->crtc_hsync_end;  in intel_mode_from_crtc_timings()
2317 	mode->vdisplay = timings->crtc_vdisplay;  in intel_mode_from_crtc_timings()
2318 	mode->vtotal = timings->crtc_vtotal;  in intel_mode_from_crtc_timings()
2319 	mode->vsync_start = timings->crtc_vsync_start;  in intel_mode_from_crtc_timings()
2320 	mode->vsync_end = timings->crtc_vsync_end;  in intel_mode_from_crtc_timings()
2322 	mode->flags = timings->flags;  in intel_mode_from_crtc_timings()
2323 	mode->type = DRM_MODE_TYPE_DRIVER;  in intel_mode_from_crtc_timings()
2325 	mode->clock = timings->crtc_clock;  in intel_mode_from_crtc_timings()
2327 	drm_mode_set_name(mode);  in intel_mode_from_crtc_timings()
2332 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in intel_crtc_compute_pixel_rate()
2336 		crtc_state->pixel_rate =  in intel_crtc_compute_pixel_rate()
2337 			crtc_state->hw.pipe_mode.crtc_clock;  in intel_crtc_compute_pixel_rate()
2339 		crtc_state->pixel_rate =  in intel_crtc_compute_pixel_rate()
2344 					struct drm_display_mode *mode)  in intel_joiner_adjust_timings()  argument
2351 	mode->crtc_clock /= num_pipes;  in intel_joiner_adjust_timings()
2352 	mode->crtc_hdisplay /= num_pipes;  in intel_joiner_adjust_timings()
2353 	mode->crtc_hblank_start /= num_pipes;  in intel_joiner_adjust_timings()
2354 	mode->crtc_hblank_end /= num_pipes;  in intel_joiner_adjust_timings()
2355 	mode->crtc_hsync_start /= num_pipes;  in intel_joiner_adjust_timings()
2356 	mode->crtc_hsync_end /= num_pipes;  in intel_joiner_adjust_timings()
2357 	mode->crtc_htotal /= num_pipes;  in intel_joiner_adjust_timings()
2361 					  struct drm_display_mode *mode)  in intel_splitter_adjust_timings()  argument
2363 	int overlap = crtc_state->splitter.pixel_overlap;  in intel_splitter_adjust_timings()
2364 	int n = crtc_state->splitter.link_count;  in intel_splitter_adjust_timings()
2366 	if (!crtc_state->splitter.enable)  in intel_splitter_adjust_timings()
2371 	 * timings, but full mode for everything else.  in intel_splitter_adjust_timings()
2373 	 * h_full = (h_segment - pixel_overlap) * link_count  in intel_splitter_adjust_timings()
2375 	mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n;  in intel_splitter_adjust_timings()
2376 	mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n;  in intel_splitter_adjust_timings()
2377 	mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n;  in intel_splitter_adjust_timings()
2378 	mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n;  in intel_splitter_adjust_timings()
2379 	mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n;  in intel_splitter_adjust_timings()
2380 	mode->crtc_htotal = (mode->crtc_htotal - overlap) * n;  in intel_splitter_adjust_timings()
2381 	mode->crtc_clock *= n;  in intel_splitter_adjust_timings()
2386 	struct drm_display_mode *mode = &crtc_state->hw.mode;  in intel_crtc_readout_derived_state()  local
2387 	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;  in intel_crtc_readout_derived_state()
2388 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_crtc_readout_derived_state()
2396 	/* Expand MSO per-segment transcoder timings to full */  in intel_crtc_readout_derived_state()
2406 	/* Populate the "user" mode with full numbers */  in intel_crtc_readout_derived_state()
2407 	drm_mode_copy(mode, pipe_mode);  in intel_crtc_readout_derived_state()
2408 	intel_mode_from_crtc_timings(mode, mode);  in intel_crtc_readout_derived_state()
2409 	mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) *  in intel_crtc_readout_derived_state()
2411 	mode->vdisplay = drm_rect_height(&crtc_state->pipe_src);  in intel_crtc_readout_derived_state()
2413 	/* Derive per-pipe timings in case joiner is used */  in intel_crtc_readout_derived_state()
2423 	encoder->get_config(encoder, crtc_state);  in intel_encoder_get_config()
2436 	width = drm_rect_width(&crtc_state->pipe_src);  in intel_joiner_compute_pipe_src()
2437 	height = drm_rect_height(&crtc_state->pipe_src);  in intel_joiner_compute_pipe_src()
2439 	drm_rect_init(&crtc_state->pipe_src, 0, 0,  in intel_joiner_compute_pipe_src()
2445 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_compute_pipe_src()
2446 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in intel_crtc_compute_pipe_src()
2452 	 * - DVO ganged mode  in intel_crtc_compute_pipe_src()
2453 	 * - LVDS dual channel mode  in intel_crtc_compute_pipe_src()
2454 	 * - Double wide pipe  in intel_crtc_compute_pipe_src()
2456 	if (drm_rect_width(&crtc_state->pipe_src) & 1) {  in intel_crtc_compute_pipe_src()
2457 		if (crtc_state->double_wide) {  in intel_crtc_compute_pipe_src()
2458 			drm_dbg_kms(&i915->drm,  in intel_crtc_compute_pipe_src()
2460 				    crtc->base.base.id, crtc->base.name);  in intel_crtc_compute_pipe_src()
2461 			return -EINVAL;  in intel_crtc_compute_pipe_src()
2466 			drm_dbg_kms(&i915->drm,  in intel_crtc_compute_pipe_src()
2468 				    crtc->base.base.id, crtc->base.name);  in intel_crtc_compute_pipe_src()
2469 			return -EINVAL;  in intel_crtc_compute_pipe_src()
2478 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_compute_pipe_mode()
2479 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in intel_crtc_compute_pipe_mode()
2480 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_crtc_compute_pipe_mode()
2481 	struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;  in intel_crtc_compute_pipe_mode()
2482 	int clock_limit = i915->display.cdclk.max_dotclk_freq;  in intel_crtc_compute_pipe_mode()
2490 	/* Expand MSO per-segment transcoder timings to full */  in intel_crtc_compute_pipe_mode()
2493 	/* Derive per-pipe timings in case joiner is used */  in intel_crtc_compute_pipe_mode()
2498 		clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10;  in intel_crtc_compute_pipe_mode()
2501 		 * Enable double wide mode when the dot clock  in intel_crtc_compute_pipe_mode()
2505 		    pipe_mode->crtc_clock > clock_limit) {  in intel_crtc_compute_pipe_mode()
2506 			clock_limit = i915->display.cdclk.max_dotclk_freq;  in intel_crtc_compute_pipe_mode()
2507 			crtc_state->double_wide = true;  in intel_crtc_compute_pipe_mode()
2511 	if (pipe_mode->crtc_clock > clock_limit) {  in intel_crtc_compute_pipe_mode()
2512 		drm_dbg_kms(&i915->drm,  in intel_crtc_compute_pipe_mode()
2514 			    crtc->base.base.id, crtc->base.name,  in intel_crtc_compute_pipe_mode()
2515 			    pipe_mode->crtc_clock, clock_limit,  in intel_crtc_compute_pipe_mode()
2516 			    str_yes_no(crtc_state->double_wide));  in intel_crtc_compute_pipe_mode()
2517 		return -EINVAL;  in intel_crtc_compute_pipe_mode()
2544 	if (crtc_state->has_pch_encoder)  in intel_crtc_compute_config()
2590 	m_n->tu = 64;  in intel_link_compute_m_n()
2591 	compute_m_n(&m_n->data_m, &m_n->data_n,  in intel_link_compute_m_n()
2595 	compute_m_n(&m_n->link_m, &m_n->link_n,  in intel_link_compute_m_n()
2613 		if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) {  in intel_panel_sanitize_ssc()
2614 			drm_dbg_kms(&dev_priv->drm,  in intel_panel_sanitize_ssc()
2617 				    str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc));  in intel_panel_sanitize_ssc()
2618 			dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc;  in intel_panel_sanitize_ssc()
2627 	m_n->tu = 1;  in intel_zero_m_n()
2635 	intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);  in intel_set_m_n()
2636 	intel_de_write(i915, data_n_reg, m_n->data_n);  in intel_set_m_n()
2637 	intel_de_write(i915, link_m_reg, m_n->link_m);  in intel_set_m_n()
2642 	intel_de_write(i915, link_n_reg, m_n->link_n);  in intel_set_m_n()
2658 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_cpu_transcoder_set_m1_n1()
2659 	enum pipe pipe = crtc->pipe;  in intel_cpu_transcoder_set_m1_n1()
2677 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_cpu_transcoder_set_m2_n2()
2691 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_set_transcoder_timings()
2692 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_set_transcoder_timings()
2693 	enum pipe pipe = crtc->pipe;  in intel_set_transcoder_timings()
2694 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_set_transcoder_timings()
2695 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_set_transcoder_timings()
2699 	/* We need to be careful not to changed the adjusted mode, for otherwise  in intel_set_transcoder_timings()
2701 	crtc_vdisplay = adjusted_mode->crtc_vdisplay;  in intel_set_transcoder_timings()
2702 	crtc_vtotal = adjusted_mode->crtc_vtotal;  in intel_set_transcoder_timings()
2703 	crtc_vblank_start = adjusted_mode->crtc_vblank_start;  in intel_set_transcoder_timings()
2704 	crtc_vblank_end = adjusted_mode->crtc_vblank_end;  in intel_set_transcoder_timings()
2706 	if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {  in intel_set_transcoder_timings()
2708 		crtc_vtotal -= 1;  in intel_set_transcoder_timings()
2709 		crtc_vblank_end -= 1;  in intel_set_transcoder_timings()
2712 			vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;  in intel_set_transcoder_timings()
2714 			vsyncshift = adjusted_mode->crtc_hsync_start -  in intel_set_transcoder_timings()
2715 				adjusted_mode->crtc_htotal / 2;  in intel_set_transcoder_timings()
2717 			vsyncshift += adjusted_mode->crtc_htotal;  in intel_set_transcoder_timings()
2727 			       crtc_vblank_start - crtc_vdisplay);  in intel_set_transcoder_timings()
2742 		       HACTIVE(adjusted_mode->crtc_hdisplay - 1) |  in intel_set_transcoder_timings()
2743 		       HTOTAL(adjusted_mode->crtc_htotal - 1));  in intel_set_transcoder_timings()
2745 		       HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |  in intel_set_transcoder_timings()
2746 		       HBLANK_END(adjusted_mode->crtc_hblank_end - 1));  in intel_set_transcoder_timings()
2748 		       HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |  in intel_set_transcoder_timings()
2749 		       HSYNC_END(adjusted_mode->crtc_hsync_end - 1));  in intel_set_transcoder_timings()
2752 		       VACTIVE(crtc_vdisplay - 1) |  in intel_set_transcoder_timings()
2753 		       VTOTAL(crtc_vtotal - 1));  in intel_set_transcoder_timings()
2755 		       VBLANK_START(crtc_vblank_start - 1) |  in intel_set_transcoder_timings()
2756 		       VBLANK_END(crtc_vblank_end - 1));  in intel_set_transcoder_timings()
2758 		       VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |  in intel_set_transcoder_timings()
2759 		       VSYNC_END(adjusted_mode->crtc_vsync_end - 1));  in intel_set_transcoder_timings()
2768 			       VACTIVE(crtc_vdisplay - 1) |  in intel_set_transcoder_timings()
2769 			       VTOTAL(crtc_vtotal - 1));  in intel_set_transcoder_timings()
2774 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_set_transcoder_timings_lrr()
2775 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_set_transcoder_timings_lrr()
2776 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_set_transcoder_timings_lrr()
2777 	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;  in intel_set_transcoder_timings_lrr()
2780 	crtc_vdisplay = adjusted_mode->crtc_vdisplay;  in intel_set_transcoder_timings_lrr()
2781 	crtc_vtotal = adjusted_mode->crtc_vtotal;  in intel_set_transcoder_timings_lrr()
2782 	crtc_vblank_start = adjusted_mode->crtc_vblank_start;  in intel_set_transcoder_timings_lrr()
2783 	crtc_vblank_end = adjusted_mode->crtc_vblank_end;  in intel_set_transcoder_timings_lrr()
2785 	drm_WARN_ON(&dev_priv->drm, adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);  in intel_set_transcoder_timings_lrr()
2788 	 * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.  in intel_set_transcoder_timings_lrr()
2792 		       VBLANK_START(crtc_vblank_start - 1) |  in intel_set_transcoder_timings_lrr()
2793 		       VBLANK_END(crtc_vblank_end - 1));  in intel_set_transcoder_timings_lrr()
2799 		       VACTIVE(crtc_vdisplay - 1) |  in intel_set_transcoder_timings_lrr()
2800 		       VTOTAL(crtc_vtotal - 1));  in intel_set_transcoder_timings_lrr()
2805 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_set_pipe_src_size()
2806 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_set_pipe_src_size()
2807 	int width = drm_rect_width(&crtc_state->pipe_src);  in intel_set_pipe_src_size()
2808 	int height = drm_rect_height(&crtc_state->pipe_src);  in intel_set_pipe_src_size()
2809 	enum pipe pipe = crtc->pipe;  in intel_set_pipe_src_size()
2815 		       PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));  in intel_set_pipe_src_size()
2820 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);  in intel_pipe_is_interlaced()
2821 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in intel_pipe_is_interlaced()
2838 	struct drm_device *dev = crtc->base.dev;  in intel_get_transcoder_timings()
2840 	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;  in intel_get_transcoder_timings()
2841 	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;  in intel_get_transcoder_timings()
2845 	adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2846 	adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2851 		adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2852 		adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2856 	adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2857 	adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2860 	adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2861 	adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2867 		adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2868 		adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2871 	adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2872 	adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1;  in intel_get_transcoder_timings()
2875 		adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;  in intel_get_transcoder_timings()
2876 		adjusted_mode->crtc_vtotal += 1;  in intel_get_transcoder_timings()
2877 		adjusted_mode->crtc_vblank_end += 1;  in intel_get_transcoder_timings()
2881 		adjusted_mode->crtc_vblank_start =  in intel_get_transcoder_timings()
2882 			adjusted_mode->crtc_vdisplay +  in intel_get_transcoder_timings()
2889 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_joiner_adjust_pipe_src()
2891 	enum pipe primary_pipe, pipe = crtc->pipe;  in intel_joiner_adjust_pipe_src()
2898 	width = drm_rect_width(&crtc_state->pipe_src);  in intel_joiner_adjust_pipe_src()
2900 	drm_rect_translate_to(&crtc_state->pipe_src,  in intel_joiner_adjust_pipe_src()
2901 			      (pipe - primary_pipe) * width, 0);  in intel_joiner_adjust_pipe_src()
2907 	struct drm_device *dev = crtc->base.dev;  in intel_get_pipe_src_size()
2911 	tmp = intel_de_read(dev_priv, PIPESRC(dev_priv, crtc->pipe));  in intel_get_pipe_src_size()
2913 	drm_rect_init(&pipe_config->pipe_src, 0, 0,  in intel_get_pipe_src_size()
2922 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in i9xx_set_pipeconf()
2923 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_set_pipeconf()
2924 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in i9xx_set_pipeconf()
2928 	 * - We keep both pipes enabled on 830  in i9xx_set_pipeconf()
2929 	 * - During modeset the pipe is still disabled and must remain so  in i9xx_set_pipeconf()
2930 	 * - During fastset the pipe is already enabled and must remain so  in i9xx_set_pipeconf()
2935 	if (crtc_state->double_wide)  in i9xx_set_pipeconf()
2942 		if (crtc_state->dither && crtc_state->pipe_bpp != 30)  in i9xx_set_pipeconf()
2946 		switch (crtc_state->pipe_bpp) {  in i9xx_set_pipeconf()
2949 			MISSING_CASE(crtc_state->pipe_bpp);  in i9xx_set_pipeconf()
2963 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {  in i9xx_set_pipeconf()
2974 	     crtc_state->limited_color_range)  in i9xx_set_pipeconf()
2977 	val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);  in i9xx_set_pipeconf()
2979 	if (crtc_state->wgc_enable)  in i9xx_set_pipeconf()
2982 	val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);  in i9xx_set_pipeconf()
2999 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in i9xx_get_pfit_config()
3000 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_get_pfit_config()
3017 	if (pipe != crtc->pipe)  in i9xx_get_pfit_config()
3020 	crtc_state->gmch_pfit.control = tmp;  in i9xx_get_pfit_config()
3021 	crtc_state->gmch_pfit.pgm_ratios =  in i9xx_get_pfit_config()
3028 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in bdw_get_pipe_misc_output_format()
3031 	tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));  in bdw_get_pipe_misc_output_format()
3034 		/* We support 4:2:0 in full blend mode only */  in bdw_get_pipe_misc_output_format()
3035 		drm_WARN_ON(&dev_priv->drm,  in bdw_get_pipe_misc_output_format()
3049 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_get_pipe_config()
3055 	power_domain = POWER_DOMAIN_PIPE(crtc->pipe);  in i9xx_get_pipe_config()
3060 	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;  in i9xx_get_pipe_config()
3061 	pipe_config->sink_format = pipe_config->output_format;  in i9xx_get_pipe_config()
3062 	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;  in i9xx_get_pipe_config()
3063 	pipe_config->shared_dpll = NULL;  in i9xx_get_pipe_config()
3068 			    TRANSCONF(dev_priv, pipe_config->cpu_transcoder));  in i9xx_get_pipe_config()
3076 			pipe_config->pipe_bpp = 18;  in i9xx_get_pipe_config()
3079 			pipe_config->pipe_bpp = 24;  in i9xx_get_pipe_config()
3082 			pipe_config->pipe_bpp = 30;  in i9xx_get_pipe_config()
3092 		pipe_config->limited_color_range = true;  in i9xx_get_pipe_config()
3094 	pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp);  in i9xx_get_pipe_config()
3096 	pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;  in i9xx_get_pipe_config()
3100 		pipe_config->wgc_enable = true;  in i9xx_get_pipe_config()
3105 		pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE;  in i9xx_get_pipe_config()
3112 	i9xx_dpll_get_hw_state(crtc, &pipe_config->dpll_hw_state);  in i9xx_get_pipe_config()
3115 		tmp = pipe_config->dpll_hw_state.i9xx.dpll_md;  in i9xx_get_pipe_config()
3116 		pipe_config->pixel_multiplier =  in i9xx_get_pipe_config()
3121 		tmp = pipe_config->dpll_hw_state.i9xx.dpll;  in i9xx_get_pipe_config()
3122 		pipe_config->pixel_multiplier =  in i9xx_get_pipe_config()
3127 		 * port and will be fixed up in the encoder->get_config  in i9xx_get_pipe_config()
3129 		pipe_config->pixel_multiplier = 1;  in i9xx_get_pipe_config()
3144 	pipe_config->hw.adjusted_mode.crtc_clock =  in i9xx_get_pipe_config()
3145 		pipe_config->port_clock / pipe_config->pixel_multiplier;  in i9xx_get_pipe_config()
3157 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in ilk_set_pipeconf()
3158 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_set_pipeconf()
3159 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in ilk_set_pipeconf()
3163 	 * - During modeset the pipe is still disabled and must remain so  in ilk_set_pipeconf()
3164 	 * - During fastset the pipe is already enabled and must remain so  in ilk_set_pipeconf()
3169 	switch (crtc_state->pipe_bpp) {  in ilk_set_pipeconf()
3172 		MISSING_CASE(crtc_state->pipe_bpp);  in ilk_set_pipeconf()
3188 	if (crtc_state->dither)  in ilk_set_pipeconf()
3191 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)  in ilk_set_pipeconf()
3200 	drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&  in ilk_set_pipeconf()
3201 		    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);  in ilk_set_pipeconf()
3203 	if (crtc_state->limited_color_range &&  in ilk_set_pipeconf()
3207 	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)  in ilk_set_pipeconf()
3210 	val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);  in ilk_set_pipeconf()
3212 	val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);  in ilk_set_pipeconf()
3213 	val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);  in ilk_set_pipeconf()
3221 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in hsw_set_transconf()
3222 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_set_transconf()
3223 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;  in hsw_set_transconf()
3227 	 * - During modeset the pipe is still disabled and must remain so  in hsw_set_transconf()
3228 	 * - During fastset the pipe is already enabled and must remain so  in hsw_set_transconf()
3233 	if (IS_HASWELL(dev_priv) && crtc_state->dither)  in hsw_set_transconf()
3236 	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)  in hsw_set_transconf()
3242 	    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)  in hsw_set_transconf()
3251 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in bdw_set_pipe_misc()
3252 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in bdw_set_pipe_misc()
3255 	switch (crtc_state->pipe_bpp) {  in bdw_set_pipe_misc()
3271 		MISSING_CASE(crtc_state->pipe_bpp);  in bdw_set_pipe_misc()
3275 	if (crtc_state->dither)  in bdw_set_pipe_misc()
3278 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||  in bdw_set_pipe_misc()
3279 	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)  in bdw_set_pipe_misc()
3282 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)  in bdw_set_pipe_misc()
3296 	intel_de_write(dev_priv, PIPE_MISC(crtc->pipe), val);  in bdw_set_pipe_misc()
3301 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in bdw_get_pipe_misc_bpp()
3304 	tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));  in bdw_get_pipe_misc_bpp()
3349 	m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;  in intel_get_m_n()
3350 	m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;  in intel_get_m_n()
3351 	m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;  in intel_get_m_n()
3352 	m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;  in intel_get_m_n()
3353 	m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;  in intel_get_m_n()
3360 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_cpu_transcoder_get_m1_n1()
3361 	enum pipe pipe = crtc->pipe;  in intel_cpu_transcoder_get_m1_n1()
3379 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_cpu_transcoder_get_m2_n2()
3393 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in ilk_get_pfit_config()
3394 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ilk_get_pfit_config()
3398 	ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));  in ilk_get_pfit_config()
3405 		pipe = crtc->pipe;  in ilk_get_pfit_config()
3407 	crtc_state->pch_pfit.enabled = true;  in ilk_get_pfit_config()
3409 	pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));  in ilk_get_pfit_config()
3410 	size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));  in ilk_get_pfit_config()
3412 	drm_rect_init(&crtc_state->pch_pfit.dst,  in ilk_get_pfit_config()
3423 	drm_WARN_ON(&dev_priv->drm, pipe != crtc->pipe);  in ilk_get_pfit_config()
3429 	struct drm_device *dev = crtc->base.dev;  in ilk_get_pipe_config()
3436 	power_domain = POWER_DOMAIN_PIPE(crtc->pipe);  in ilk_get_pipe_config()
3441 	pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;  in ilk_get_pipe_config()
3442 	pipe_config->shared_dpll = NULL;  in ilk_get_pipe_config()
3446 			    TRANSCONF(dev_priv, pipe_config->cpu_transcoder));  in ilk_get_pipe_config()
3452 		pipe_config->pipe_bpp = 18;  in ilk_get_pipe_config()
3455 		pipe_config->pipe_bpp = 24;  in ilk_get_pipe_config()
3458 		pipe_config->pipe_bpp = 30;  in ilk_get_pipe_config()
3461 		pipe_config->pipe_bpp = 36;  in ilk_get_pipe_config()
3468 		pipe_config->limited_color_range = true;  in ilk_get_pipe_config()
3473 		pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;  in ilk_get_pipe_config()
3476 		pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;  in ilk_get_pipe_config()
3480 	pipe_config->sink_format = pipe_config->output_format;  in ilk_get_pipe_config()
3482 	pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp);  in ilk_get_pipe_config()
3484 	pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;  in ilk_get_pipe_config()
3486 	pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp);  in ilk_get_pipe_config()
3490 	pipe_config->pixel_multiplier = 1;  in ilk_get_pipe_config()
3518 	return pipes & DISPLAY_RUNTIME_INFO(i915)->pipe_mask;  in joiner_pipes()
3545 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc,  in enabled_joiner_pipes()
3548 		enum pipe pipe = crtc->pipe;  in enabled_joiner_pipes()
3579 	drm_WARN(&dev_priv->drm, *secondary_pipes != *primary_pipes << 1,  in enabled_joiner_pipes()
3593 	return fls(primary_pipes) - 1;  in get_joiner_primary_pipe()
3610 	next_primary_pipe = ffs(primary_pipes) - 1;  in get_joiner_secondary_pipes()
3612 	return secondary_pipes & GENMASK(next_primary_pipe - 1, primary_pipe);  in get_joiner_secondary_pipes()
3627 	struct drm_device *dev = crtc->base.dev;  in hsw_enabled_transcoders()
3674 		if (trans_pipe == crtc->pipe)  in hsw_enabled_transcoders()
3679 	cpu_transcoder = (enum transcoder) crtc->pipe;  in hsw_enabled_transcoders()
3683 	/* joiner secondary -> consider the primary pipe's transcoder as well */  in hsw_enabled_transcoders()
3685 	if (secondary_pipes & BIT(crtc->pipe)) {  in hsw_enabled_transcoders()
3687 			get_joiner_primary_pipe(crtc->pipe, primary_pipes, secondary_pipes);  in hsw_enabled_transcoders()
3717 	drm_WARN_ON(&i915->drm,  in assert_enabled_transcoders()
3722 	/* Only DSI transcoders can be ganged */  in assert_enabled_transcoders()
3723 	drm_WARN_ON(&i915->drm,  in assert_enabled_transcoders()
3732 	struct drm_device *dev = crtc->base.dev;  in hsw_get_transcoder_state()
3748 	pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1;  in hsw_get_transcoder_state()
3751 						       POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))  in hsw_get_transcoder_state()
3754 	if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) {  in hsw_get_transcoder_state()
3756 				    TRANS_DDI_FUNC_CTL(dev_priv, pipe_config->cpu_transcoder));  in hsw_get_transcoder_state()
3759 			pipe_config->pch_pfit.force_thru = true;  in hsw_get_transcoder_state()
3763 			    TRANSCONF(dev_priv, pipe_config->cpu_transcoder));  in hsw_get_transcoder_state()
3773 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in bxt_get_dsi_transcoder_state()
3798 		/* XXX: this works for video mode only */  in bxt_get_dsi_transcoder_state()
3804 		if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))  in bxt_get_dsi_transcoder_state()
3807 		pipe_config->cpu_transcoder = cpu_transcoder;  in bxt_get_dsi_transcoder_state()
3811 	return transcoder_is_dsi(pipe_config->cpu_transcoder);  in bxt_get_dsi_transcoder_state()
3816 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_joiner_get_config()
3817 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in intel_joiner_get_config()
3819 	enum pipe pipe = crtc->pipe;  in intel_joiner_get_config()
3826 	crtc_state->joiner_pipes =  in intel_joiner_get_config()
3834 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_get_pipe_config()
3838 	if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,  in hsw_get_pipe_config()
3839 						       POWER_DOMAIN_PIPE(crtc->pipe)))  in hsw_get_pipe_config()
3842 	pipe_config->shared_dpll = NULL;  in hsw_get_pipe_config()
3844 	active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains);  in hsw_get_pipe_config()
3847 	    bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) {  in hsw_get_pipe_config()
3848 		drm_WARN_ON(&dev_priv->drm, active);  in hsw_get_pipe_config()
3858 	if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||  in hsw_get_pipe_config()
3862 	if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder))  in hsw_get_pipe_config()
3869 					TRANSCONF(dev_priv, pipe_config->cpu_transcoder));  in hsw_get_pipe_config()
3872 			pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;  in hsw_get_pipe_config()
3874 			pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;  in hsw_get_pipe_config()
3876 		pipe_config->output_format =  in hsw_get_pipe_config()
3880 	pipe_config->sink_format = pipe_config->output_format;  in hsw_get_pipe_config()
3884 	tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));  in hsw_get_pipe_config()
3885 	pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);  in hsw_get_pipe_config()
3887 		pipe_config->ips_linetime =  in hsw_get_pipe_config()
3890 	if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,  in hsw_get_pipe_config()
3891 						      POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {  in hsw_get_pipe_config()
3900 	if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&  in hsw_get_pipe_config()
3901 	    !transcoder_is_dsi(pipe_config->cpu_transcoder)) {  in hsw_get_pipe_config()
3902 		pipe_config->pixel_multiplier =  in hsw_get_pipe_config()
3904 				      TRANS_MULT(dev_priv, pipe_config->cpu_transcoder)) + 1;  in hsw_get_pipe_config()
3906 		pipe_config->pixel_multiplier = 1;  in hsw_get_pipe_config()
3909 	if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {  in hsw_get_pipe_config()
3910 		tmp = intel_de_read(dev_priv, hsw_chicken_trans_reg(dev_priv, pipe_config->cpu_transcoder));  in hsw_get_pipe_config()
3912 		pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;  in hsw_get_pipe_config()
3915 		pipe_config->framestart_delay = 1;  in hsw_get_pipe_config()
3919 	intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains);  in hsw_get_pipe_config()
3926 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_crtc_get_pipe_config()
3927 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in intel_crtc_get_pipe_config()
3929 	if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state))  in intel_crtc_get_pipe_config()
3932 	crtc_state->hw.active = true;  in intel_crtc_get_pipe_config()
3943 	 * The calculation for the data clock -> pixel clock is:  in intel_dotclock_calculate()
3948 	 * and for link freq (10kbs units) -> pixel clock it is:  in intel_dotclock_calculate()
3955 	if (!m_n->link_n)  in intel_dotclock_calculate()
3958 	return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq * 10),  in intel_dotclock_calculate()
3959 				m_n->link_n * intel_dp_link_symbol_size(link_freq));  in intel_dotclock_calculate()
3967 		dotclock = intel_dotclock_calculate(pipe_config->port_clock,  in intel_crtc_dotclock()
3968 						    &pipe_config->dp_m_n);  in intel_crtc_dotclock()
3969 	else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)  in intel_crtc_dotclock()
3970 		dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24,  in intel_crtc_dotclock()
3971 					     pipe_config->pipe_bpp);  in intel_crtc_dotclock()
3973 		dotclock = pipe_config->port_clock;  in intel_crtc_dotclock()
3975 	if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&  in intel_crtc_dotclock()
3979 	if (pipe_config->pixel_multiplier)  in intel_crtc_dotclock()
3980 		dotclock /= pipe_config->pixel_multiplier;  in intel_crtc_dotclock()
3985 /* Returns the currently programmed mode of the given encoder. */
3989 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);  in intel_encoder_current_mode()
3991 	struct drm_display_mode *mode;  in intel_encoder_current_mode()  local
3995 	if (!encoder->get_hw_state(encoder, &pipe))  in intel_encoder_current_mode()
4000 	mode = kzalloc(sizeof(*mode), GFP_KERNEL);  in intel_encoder_current_mode()
4001 	if (!mode)  in intel_encoder_current_mode()
4006 		kfree(mode);  in intel_encoder_current_mode()
4011 		intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);  in intel_encoder_current_mode()
4012 		kfree(mode);  in intel_encoder_current_mode()
4018 	intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);  in intel_encoder_current_mode()
4020 	intel_crtc_destroy_state(&crtc->base, &crtc_state->uapi);  in intel_encoder_current_mode()
4022 	return mode;  in intel_encoder_current_mode()
4029 	return a == b || (a->cloneable & BIT(b->type) &&  in encoders_cloneable()
4030 			  b->cloneable & BIT(a->type));  in encoders_cloneable()
4042 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in check_single_encoder_cloning()
4043 		if (connector_state->crtc != &crtc->base)  in check_single_encoder_cloning()
4047 			to_intel_encoder(connector_state->best_encoder);  in check_single_encoder_cloning()
4062 		linked = plane_state->planar_linked_plane;  in icl_add_linked_planes()
4071 		drm_WARN_ON(state->base.dev,  in icl_add_linked_planes()
4072 			    linked_plane_state->planar_linked_plane != plane);  in icl_add_linked_planes()
4073 		drm_WARN_ON(state->base.dev,  in icl_add_linked_planes()
4074 			    linked_plane_state->planar_slave == plane_state->planar_slave);  in icl_add_linked_planes()
4083 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in icl_check_nv12_planes()
4095 	 * in the crtc_state->active_planes mask.  in icl_check_nv12_planes()
4098 		if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)  in icl_check_nv12_planes()
4101 		plane_state->planar_linked_plane = NULL;  in icl_check_nv12_planes()
4102 		if (plane_state->planar_slave && !plane_state->uapi.visible) {  in icl_check_nv12_planes()
4103 			crtc_state->enabled_planes &= ~BIT(plane->id);  in icl_check_nv12_planes()
4104 			crtc_state->active_planes &= ~BIT(plane->id);  in icl_check_nv12_planes()
4105 			crtc_state->update_planes |= BIT(plane->id);  in icl_check_nv12_planes()
4106 			crtc_state->data_rate[plane->id] = 0;  in icl_check_nv12_planes()
4107 			crtc_state->rel_data_rate[plane->id] = 0;  in icl_check_nv12_planes()
4110 		plane_state->planar_slave = false;  in icl_check_nv12_planes()
4113 	if (!crtc_state->nv12_planes)  in icl_check_nv12_planes()
4119 		if (plane->pipe != crtc->pipe ||  in icl_check_nv12_planes()
4120 		    !(crtc_state->nv12_planes & BIT(plane->id)))  in icl_check_nv12_planes()
4123 		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {  in icl_check_nv12_planes()
4124 			if (!icl_is_nv12_y_plane(dev_priv, linked->id))  in icl_check_nv12_planes()
4127 			if (crtc_state->active_planes & BIT(linked->id))  in icl_check_nv12_planes()
4138 			drm_dbg_kms(&dev_priv->drm,  in icl_check_nv12_planes()
4140 				    hweight8(crtc_state->nv12_planes));  in icl_check_nv12_planes()
4142 			return -EINVAL;  in icl_check_nv12_planes()
4145 		plane_state->planar_linked_plane = linked;  in icl_check_nv12_planes()
4147 		linked_state->planar_slave = true;  in icl_check_nv12_planes()
4148 		linked_state->planar_linked_plane = plane;  in icl_check_nv12_planes()
4149 		crtc_state->enabled_planes |= BIT(linked->id);  in icl_check_nv12_planes()
4150 		crtc_state->active_planes |= BIT(linked->id);  in icl_check_nv12_planes()
4151 		crtc_state->update_planes |= BIT(linked->id);  in icl_check_nv12_planes()
4152 		crtc_state->data_rate[linked->id] =  in icl_check_nv12_planes()
4153 			crtc_state->data_rate_y[plane->id];  in icl_check_nv12_planes()
4154 		crtc_state->rel_data_rate[linked->id] =  in icl_check_nv12_planes()
4155 			crtc_state->rel_data_rate_y[plane->id];  in icl_check_nv12_planes()
4156 		drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",  in icl_check_nv12_planes()
4157 			    linked->base.name, plane->base.name);  in icl_check_nv12_planes()
4160 		linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;  in icl_check_nv12_planes()
4161 		linked_state->color_ctl = plane_state->color_ctl;  in icl_check_nv12_planes()
4162 		linked_state->view = plane_state->view;  in icl_check_nv12_planes()
4163 		linked_state->decrypt = plane_state->decrypt;  in icl_check_nv12_planes()
4166 		linked_state->uapi.src = plane_state->uapi.src;  in icl_check_nv12_planes()
4167 		linked_state->uapi.dst = plane_state->uapi.dst;  in icl_check_nv12_planes()
4169 		if (icl_is_hdr_plane(dev_priv, plane->id)) {  in icl_check_nv12_planes()
4170 			if (linked->id == PLANE_7)  in icl_check_nv12_planes()
4171 				plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;  in icl_check_nv12_planes()
4172 			else if (linked->id == PLANE_6)  in icl_check_nv12_planes()
4173 				plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;  in icl_check_nv12_planes()
4174 			else if (linked->id == PLANE_5)  in icl_check_nv12_planes()
4175 				plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;  in icl_check_nv12_planes()
4176 			else if (linked->id == PLANE_4)  in icl_check_nv12_planes()
4177 				plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;  in icl_check_nv12_planes()
4179 				MISSING_CASE(linked->id);  in icl_check_nv12_planes()
4189 		&crtc_state->hw.pipe_mode;  in hsw_linetime_wm()
4192 	if (!crtc_state->hw.enable)  in hsw_linetime_wm()
4195 	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,  in hsw_linetime_wm()
4196 					pipe_mode->crtc_clock);  in hsw_linetime_wm()
4205 		&crtc_state->hw.pipe_mode;  in hsw_ips_linetime_wm()
4208 	if (!crtc_state->hw.enable)  in hsw_ips_linetime_wm()
4211 	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,  in hsw_ips_linetime_wm()
4212 					cdclk_state->logical.cdclk);  in hsw_ips_linetime_wm()
4219 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in skl_linetime_wm()
4220 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in skl_linetime_wm()
4222 		&crtc_state->hw.pipe_mode;  in skl_linetime_wm()
4225 	if (!crtc_state->hw.enable)  in skl_linetime_wm()
4228 	linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,  in skl_linetime_wm()
4229 				   crtc_state->pixel_rate);  in skl_linetime_wm()
4242 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in hsw_compute_linetime_wm()
4248 		crtc_state->linetime = skl_linetime_wm(crtc_state);  in hsw_compute_linetime_wm()
4250 		crtc_state->linetime = hsw_linetime_wm(crtc_state);  in hsw_compute_linetime_wm()
4259 	crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,  in hsw_compute_linetime_wm()
4268 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_crtc_atomic_check()
4275 	    !crtc_state->hw.active)  in intel_crtc_atomic_check()
4276 		crtc_state->update_wm_post = true;  in intel_crtc_atomic_check()
4290 		drm_dbg_kms(&dev_priv->drm,  in intel_crtc_atomic_check()
4302 		drm_dbg_kms(&dev_priv->drm,  in intel_crtc_atomic_check()
4345 	struct drm_connector *connector = conn_state->connector;  in compute_sink_pipe_bpp()
4346 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);  in compute_sink_pipe_bpp()
4347 	const struct drm_display_info *info = &connector->display_info;  in compute_sink_pipe_bpp()
4350 	switch (conn_state->max_bpc) {  in compute_sink_pipe_bpp()
4364 		MISSING_CASE(conn_state->max_bpc);  in compute_sink_pipe_bpp()
4365 		return -EINVAL;  in compute_sink_pipe_bpp()
4368 	if (bpp < crtc_state->pipe_bpp) {  in compute_sink_pipe_bpp()
4369 		drm_dbg_kms(&i915->drm,  in compute_sink_pipe_bpp()
4372 			    connector->base.id, connector->name,  in compute_sink_pipe_bpp()
4373 			    bpp, 3 * info->bpc,  in compute_sink_pipe_bpp()
4374 			    3 * conn_state->max_requested_bpc,  in compute_sink_pipe_bpp()
4375 			    crtc_state->pipe_bpp);  in compute_sink_pipe_bpp()
4377 		crtc_state->pipe_bpp = bpp;  in compute_sink_pipe_bpp()
4387 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in compute_baseline_pipe_bpp()
4402 	crtc_state->pipe_bpp = bpp;  in compute_baseline_pipe_bpp()
4405 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in compute_baseline_pipe_bpp()
4408 		if (connector_state->crtc != &crtc->base)  in compute_baseline_pipe_bpp()
4421 	struct drm_device *dev = state->base.dev;  in check_digital_port_conflicts()
4429 	 * We're going to peek into connector->state,  in check_digital_port_conflicts()
4432 	drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);  in check_digital_port_conflicts()
4445 			drm_atomic_get_new_connector_state(&state->base,  in check_digital_port_conflicts()
4448 			connector_state = connector->state;  in check_digital_port_conflicts()
4450 		if (!connector_state->best_encoder)  in check_digital_port_conflicts()
4453 		encoder = to_intel_encoder(connector_state->best_encoder);  in check_digital_port_conflicts()
4455 		drm_WARN_ON(dev, !connector_state->crtc);  in check_digital_port_conflicts()
4457 		switch (encoder->type) {  in check_digital_port_conflicts()
4466 			if (used_ports & BIT(encoder->port))  in check_digital_port_conflicts()
4469 			used_ports |= BIT(encoder->port);  in check_digital_port_conflicts()
4473 				1 << encoder->port;  in check_digital_port_conflicts()
4497 	drm_property_replace_blob(&crtc_state->hw.degamma_lut,  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4498 				  crtc_state->uapi.degamma_lut);  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4499 	drm_property_replace_blob(&crtc_state->hw.gamma_lut,  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4500 				  crtc_state->uapi.gamma_lut);  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4501 	drm_property_replace_blob(&crtc_state->hw.ctm,  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4502 				  crtc_state->uapi.ctm);  in intel_crtc_copy_uapi_to_hw_state_nomodeset()
4514 	crtc_state->hw.enable = crtc_state->uapi.enable;  in intel_crtc_copy_uapi_to_hw_state_modeset()
4515 	crtc_state->hw.active = crtc_state->uapi.active;  in intel_crtc_copy_uapi_to_hw_state_modeset()
4516 	drm_mode_copy(&crtc_state->hw.mode,  in intel_crtc_copy_uapi_to_hw_state_modeset()
4517 		      &crtc_state->uapi.mode);  in intel_crtc_copy_uapi_to_hw_state_modeset()
4518 	drm_mode_copy(&crtc_state->hw.adjusted_mode,  in intel_crtc_copy_uapi_to_hw_state_modeset()
4519 		      &crtc_state->uapi.adjusted_mode);  in intel_crtc_copy_uapi_to_hw_state_modeset()
4520 	crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;  in intel_crtc_copy_uapi_to_hw_state_modeset()
4535 	drm_property_replace_blob(&secondary_crtc_state->hw.degamma_lut,  in copy_joiner_crtc_state_nomodeset()
4536 				  primary_crtc_state->hw.degamma_lut);  in copy_joiner_crtc_state_nomodeset()
4537 	drm_property_replace_blob(&secondary_crtc_state->hw.gamma_lut,  in copy_joiner_crtc_state_nomodeset()
4538 				  primary_crtc_state->hw.gamma_lut);  in copy_joiner_crtc_state_nomodeset()
4539 	drm_property_replace_blob(&secondary_crtc_state->hw.ctm,  in copy_joiner_crtc_state_nomodeset()
4540 				  primary_crtc_state->hw.ctm);  in copy_joiner_crtc_state_nomodeset()
4542 	secondary_crtc_state->uapi.color_mgmt_changed = primary_crtc_state->uapi.color_mgmt_changed;  in copy_joiner_crtc_state_nomodeset()
4556 	WARN_ON(primary_crtc_state->joiner_pipes !=  in copy_joiner_crtc_state_modeset()
4557 		secondary_crtc_state->joiner_pipes);  in copy_joiner_crtc_state_modeset()
4561 		return -ENOMEM;  in copy_joiner_crtc_state_modeset()
4564 	saved_state->uapi = secondary_crtc_state->uapi;  in copy_joiner_crtc_state_modeset()
4565 	saved_state->scaler_state = secondary_crtc_state->scaler_state;  in copy_joiner_crtc_state_modeset()
4566 	saved_state->shared_dpll = secondary_crtc_state->shared_dpll;  in copy_joiner_crtc_state_modeset()
4567 	saved_state->crc_enabled = secondary_crtc_state->crc_enabled;  in copy_joiner_crtc_state_modeset()
4570 	if (secondary_crtc_state->dp_tunnel_ref.tunnel)  in copy_joiner_crtc_state_modeset()
4571 		drm_dp_tunnel_ref_put(&secondary_crtc_state->dp_tunnel_ref);  in copy_joiner_crtc_state_modeset()
4575 	/* Re-init hw state */  in copy_joiner_crtc_state_modeset()
4576 	memset(&secondary_crtc_state->hw, 0, sizeof(secondary_crtc_state->hw));  in copy_joiner_crtc_state_modeset()
4577 	secondary_crtc_state->hw.enable = primary_crtc_state->hw.enable;  in copy_joiner_crtc_state_modeset()
4578 	secondary_crtc_state->hw.active = primary_crtc_state->hw.active;  in copy_joiner_crtc_state_modeset()
4579 	drm_mode_copy(&secondary_crtc_state->hw.mode,  in copy_joiner_crtc_state_modeset()
4580 		      &primary_crtc_state->hw.mode);  in copy_joiner_crtc_state_modeset()
4581 	drm_mode_copy(&secondary_crtc_state->hw.pipe_mode,  in copy_joiner_crtc_state_modeset()
4582 		      &primary_crtc_state->hw.pipe_mode);  in copy_joiner_crtc_state_modeset()
4583 	drm_mode_copy(&secondary_crtc_state->hw.adjusted_mode,  in copy_joiner_crtc_state_modeset()
4584 		      &primary_crtc_state->hw.adjusted_mode);  in copy_joiner_crtc_state_modeset()
4585 	secondary_crtc_state->hw.scaling_filter = primary_crtc_state->hw.scaling_filter;  in copy_joiner_crtc_state_modeset()
4587 	if (primary_crtc_state->dp_tunnel_ref.tunnel)  in copy_joiner_crtc_state_modeset()
4588 		drm_dp_tunnel_ref_get(primary_crtc_state->dp_tunnel_ref.tunnel,  in copy_joiner_crtc_state_modeset()
4589 				      &secondary_crtc_state->dp_tunnel_ref);  in copy_joiner_crtc_state_modeset()
4593 	secondary_crtc_state->uapi.mode_changed = primary_crtc_state->uapi.mode_changed;  in copy_joiner_crtc_state_modeset()
4594 	secondary_crtc_state->uapi.connectors_changed = primary_crtc_state->uapi.connectors_changed;  in copy_joiner_crtc_state_modeset()
4595 	secondary_crtc_state->uapi.active_changed = primary_crtc_state->uapi.active_changed;  in copy_joiner_crtc_state_modeset()
4597 	WARN_ON(primary_crtc_state->joiner_pipes !=  in copy_joiner_crtc_state_modeset()
4598 		secondary_crtc_state->joiner_pipes);  in copy_joiner_crtc_state_modeset()
4609 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_crtc_prepare_cleared_state()
4614 		return -ENOMEM;  in intel_crtc_prepare_cleared_state()
4616 	/* free the old crtc_state->hw members */  in intel_crtc_prepare_cleared_state()
4626 	saved_state->uapi = crtc_state->uapi;  in intel_crtc_prepare_cleared_state()
4627 	saved_state->inherited = crtc_state->inherited;  in intel_crtc_prepare_cleared_state()
4628 	saved_state->scaler_state = crtc_state->scaler_state;  in intel_crtc_prepare_cleared_state()
4629 	saved_state->shared_dpll = crtc_state->shared_dpll;  in intel_crtc_prepare_cleared_state()
4630 	saved_state->dpll_hw_state = crtc_state->dpll_hw_state;  in intel_crtc_prepare_cleared_state()
4631 	memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,  in intel_crtc_prepare_cleared_state()
4632 	       sizeof(saved_state->icl_port_dplls));  in intel_crtc_prepare_cleared_state()
4633 	saved_state->crc_enabled = crtc_state->crc_enabled;  in intel_crtc_prepare_cleared_state()
4636 		saved_state->wm = crtc_state->wm;  in intel_crtc_prepare_cleared_state()
4651 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in intel_modeset_pipe_config()
4659 	crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;  in intel_modeset_pipe_config()
4661 	crtc_state->framestart_delay = 1;  in intel_modeset_pipe_config()
4668 	if (!(crtc_state->hw.adjusted_mode.flags &  in intel_modeset_pipe_config()
4670 		crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;  in intel_modeset_pipe_config()
4672 	if (!(crtc_state->hw.adjusted_mode.flags &  in intel_modeset_pipe_config()
4674 		crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;  in intel_modeset_pipe_config()
4680 	crtc_state->fec_enable = limits->force_fec_pipes & BIT(crtc->pipe);  in intel_modeset_pipe_config()
4681 	crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];  in intel_modeset_pipe_config()
4683 	if (crtc_state->pipe_bpp > fxp_q4_to_int(crtc_state->max_link_bpp_x16)) {  in intel_modeset_pipe_config()
4684 		drm_dbg_kms(&i915->drm,  in intel_modeset_pipe_config()
4686 			    crtc->base.base.id, crtc->base.name,  in intel_modeset_pipe_config()
4687 			    FXP_Q4_ARGS(crtc_state->max_link_bpp_x16));  in intel_modeset_pipe_config()
4688 		crtc_state->bw_constrained = true;  in intel_modeset_pipe_config()
4691 	base_bpp = crtc_state->pipe_bpp;  in intel_modeset_pipe_config()
4697 	 * is stored in the crtc timings. We use the requested mode to do this  in intel_modeset_pipe_config()
4698 	 * computation to clearly distinguish it from the adjusted mode, which  in intel_modeset_pipe_config()
4701 	drm_mode_get_hv_timing(&crtc_state->hw.mode,  in intel_modeset_pipe_config()
4703 	drm_rect_init(&crtc_state->pipe_src, 0, 0,  in intel_modeset_pipe_config()
4706 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in intel_modeset_pipe_config()
4708 			to_intel_encoder(connector_state->best_encoder);  in intel_modeset_pipe_config()
4710 		if (connector_state->crtc != &crtc->base)  in intel_modeset_pipe_config()
4714 			drm_dbg_kms(&i915->drm,  in intel_modeset_pipe_config()
4716 				    encoder->base.base.id, encoder->base.name);  in intel_modeset_pipe_config()
4717 			return -EINVAL;  in intel_modeset_pipe_config()
4724 		if (encoder->compute_output_type)  in intel_modeset_pipe_config()
4725 			crtc_state->output_types |=  in intel_modeset_pipe_config()
4726 				BIT(encoder->compute_output_type(encoder, crtc_state,  in intel_modeset_pipe_config()
4729 			crtc_state->output_types |= BIT(encoder->type);  in intel_modeset_pipe_config()
4733 	crtc_state->port_clock = 0;  in intel_modeset_pipe_config()
4734 	crtc_state->pixel_multiplier = 1;  in intel_modeset_pipe_config()
4737 	drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode,  in intel_modeset_pipe_config()
4740 	/* Pass our mode to the connectors and the CRTC to give them a chance to  in intel_modeset_pipe_config()
4742 	 * a chance to reject the mode entirely.  in intel_modeset_pipe_config()
4744 	for_each_new_connector_in_state(&state->base, connector, connector_state, i) {  in intel_modeset_pipe_config()
4746 			to_intel_encoder(connector_state->best_encoder);  in intel_modeset_pipe_config()
4748 		if (connector_state->crtc != &crtc->base)  in intel_modeset_pipe_config()
4751 		ret = encoder->compute_config(encoder, crtc_state,  in intel_modeset_pipe_config()
4753 		if (ret == -EDEADLK)  in intel_modeset_pipe_config()
4756 			drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n",  in intel_modeset_pipe_config()
4757 				    encoder->base.base.id, encoder->base.name, ret);  in intel_modeset_pipe_config()
4763 	 * done afterwards in case the encoder adjusts the mode. */  in intel_modeset_pipe_config()
4764 	if (!crtc_state->port_clock)  in intel_modeset_pipe_config()
4765 		crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock  in intel_modeset_pipe_config()
4766 			* crtc_state->pixel_multiplier;  in intel_modeset_pipe_config()
4769 	if (ret == -EDEADLK)  in intel_modeset_pipe_config()
4772 		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n",  in intel_modeset_pipe_config()
4773 			    crtc->base.base.id, crtc->base.name, ret);  in intel_modeset_pipe_config()
4777 	/* Dithering seems to not pass-through bits correctly when it should, so  in intel_modeset_pipe_config()
4781 	crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&  in intel_modeset_pipe_config()
4782 		!crtc_state->dither_force_disable;  in intel_modeset_pipe_config()
4783 	drm_dbg_kms(&i915->drm,  in intel_modeset_pipe_config()
4785 		    crtc->base.base.id, crtc->base.name,  in intel_modeset_pipe_config()
4786 		    base_bpp, crtc_state->pipe_bpp, crtc_state->dither);  in intel_modeset_pipe_config()
4801 	for_each_new_connector_in_state(&state->base, connector,  in intel_modeset_pipe_config_late()
4804 			to_intel_encoder(conn_state->best_encoder);  in intel_modeset_pipe_config_late()
4807 		if (conn_state->crtc != &crtc->base ||  in intel_modeset_pipe_config_late()
4808 		    !encoder->compute_config_late)  in intel_modeset_pipe_config_late()
4811 		ret = encoder->compute_config_late(encoder, crtc_state,  in intel_modeset_pipe_config_late()
4830 	diff = abs(clock1 - clock2);  in intel_fuzzy_clock_check()
4842 	return m_n->tu == m2_n2->tu &&  in intel_compare_link_m_n()
4843 		m_n->data_m == m2_n2->data_m &&  in intel_compare_link_m_n()
4844 		m_n->data_n == m2_n2->data_n &&  in intel_compare_link_m_n()
4845 		m_n->link_m == m2_n2->link_m &&  in intel_compare_link_m_n()
4846 		m_n->link_n == m2_n2->link_n;  in intel_compare_link_m_n()
4860 	return a->pixelformat == b->pixelformat &&  in intel_compare_dp_vsc_sdp()
4861 		a->colorimetry == b->colorimetry &&  in intel_compare_dp_vsc_sdp()
4862 		a->bpc == b->bpc &&  in intel_compare_dp_vsc_sdp()
4863 		a->dynamic_range == b->dynamic_range &&  in intel_compare_dp_vsc_sdp()
4864 		a->content_type == b->content_type;  in intel_compare_dp_vsc_sdp()
4871 	return a->vtotal == b->vtotal &&  in intel_compare_dp_as_sdp()
4872 		a->target_rr == b->target_rr &&  in intel_compare_dp_as_sdp()
4873 		a->duration_incr_ms == b->duration_incr_ms &&  in intel_compare_dp_as_sdp()
4874 		a->duration_decr_ms == b->duration_decr_ms &&  in intel_compare_dp_as_sdp()
4875 		a->mode == b->mode;  in intel_compare_dp_as_sdp()
4898 			   crtc->base.base.id, crtc->base.name, name, &vaf);  in pipe_config_mismatch()
4901 			   crtc->base.base.id, crtc->base.name, name, &vaf);  in pipe_config_mismatch()
4913 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in pipe_config_infoframe_mismatch()
4928 	hdmi_infoframe_log(loglevel, i915->drm.dev, a);  in pipe_config_infoframe_mismatch()
4930 	hdmi_infoframe_log(loglevel, i915->drm.dev, b);  in pipe_config_infoframe_mismatch()
4957 		p = drm_dbg_printer(&i915->drm, DRM_UT_KMS, NULL);  in pipe_config_dp_as_sdp_mismatch()
4961 		p = drm_err_printer(&i915->drm, NULL);  in pipe_config_dp_as_sdp_mismatch()
4978 	for (i = len - 1; i >= 0; i--) {  in memcmp_diff_len()
5021 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in pipe_config_pll_mismatch()
5023 	pipe_config_mismatch(p, fastset, crtc, name, " "); /* stupid -Werror=format-zero-length */  in pipe_config_pll_mismatch()
5038 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in pipe_config_cx0pll_mismatch()
5039 	char *chipname = a->use_c10 ? "C10" : "C20";  in pipe_config_cx0pll_mismatch()
5054 	struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);  in intel_pipe_config_compare()
5055 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);  in intel_pipe_config_compare()
5060 		p = drm_dbg_printer(&dev_priv->drm, DRM_UT_KMS, NULL);  in intel_pipe_config_compare()
5062 		p = drm_err_printer(&dev_priv->drm, NULL);  in intel_pipe_config_compare()
5065 	if (current_config->name != pipe_config->name) { \  in intel_pipe_config_compare()
5066 		BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \  in intel_pipe_config_compare()
5070 				     current_config->name, \  in intel_pipe_config_compare()
5071 				     pipe_config->name); \  in intel_pipe_config_compare()
5077 	if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \  in intel_pipe_config_compare()
5078 		BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \  in intel_pipe_config_compare()
5082 				     current_config->name & (mask), \  in intel_pipe_config_compare()
5083 				     pipe_config->name & (mask)); \  in intel_pipe_config_compare()
5089 	if (current_config->name != pipe_config->name) { \  in intel_pipe_config_compare()
5090 		BUILD_BUG_ON_MSG(__same_type(current_config->name, bool), \  in intel_pipe_config_compare()
5094 				     current_config->name, \  in intel_pipe_config_compare()
5095 				     pipe_config->name); \  in intel_pipe_config_compare()
5101 	if (current_config->name != pipe_config->name) { \  in intel_pipe_config_compare()
5104 				     current_config->name, \  in intel_pipe_config_compare()
5105 				     pipe_config->name); \  in intel_pipe_config_compare()
5111 	if (current_config->name != pipe_config->name) { \  in intel_pipe_config_compare()
5112 		BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \  in intel_pipe_config_compare()
5116 				     str_yes_no(current_config->name), \  in intel_pipe_config_compare()
5117 				     str_yes_no(pipe_config->name)); \  in intel_pipe_config_compare()
5123 	if (current_config->name != pipe_config->name) { \  in intel_pipe_config_compare()
5126 				     current_config->name, \  in intel_pipe_config_compare()
5127 				     pipe_config->name); \  in intel_pipe_config_compare()
5133 	if (!intel_compare_link_m_n(&current_config->name, \  in intel_pipe_config_compare()
5134 				    &pipe_config->name)) { \  in intel_pipe_config_compare()
5138 				     current_config->name.tu, \  in intel_pipe_config_compare()
5139 				     current_config->name.data_m, \  in intel_pipe_config_compare()
5140 				     current_config->name.data_n, \  in intel_pipe_config_compare()
5141 				     current_config->name.link_m, \  in intel_pipe_config_compare()
5142 				     current_config->name.link_n, \  in intel_pipe_config_compare()
5143 				     pipe_config->name.tu, \  in intel_pipe_config_compare()
5144 				     pipe_config->name.data_m, \  in intel_pipe_config_compare()
5145 				     pipe_config->name.data_n, \  in intel_pipe_config_compare()
5146 				     pipe_config->name.link_m, \  in intel_pipe_config_compare()
5147 				     pipe_config->name.link_n); \  in intel_pipe_config_compare()
5153 	if (!intel_dpll_compare_hw_state(dev_priv, &current_config->name, \  in intel_pipe_config_compare()
5154 					 &pipe_config->name)) { \  in intel_pipe_config_compare()
5156 					 &current_config->name, \  in intel_pipe_config_compare()
5157 					 &pipe_config->name); \  in intel_pipe_config_compare()
5163 	if (!intel_cx0pll_compare_hw_state(&current_config->name, \  in intel_pipe_config_compare()
5164 					   &pipe_config->name)) { \  in intel_pipe_config_compare()
5166 					    &current_config->name, \  in intel_pipe_config_compare()
5167 					    &pipe_config->name); \  in intel_pipe_config_compare()
5183 	if (!fastset || !pipe_config->update_lrr) { \  in intel_pipe_config_compare()
5197 	if ((current_config->name ^ pipe_config->name) & (mask)) { \  in intel_pipe_config_compare()
5201 				     current_config->name & (mask), \  in intel_pipe_config_compare()
5202 				     pipe_config->name & (mask)); \  in intel_pipe_config_compare()
5208 	if (!intel_compare_infoframe(&current_config->infoframes.name, \  in intel_pipe_config_compare()
5209 				     &pipe_config->infoframes.name)) { \  in intel_pipe_config_compare()
5211 					       &current_config->infoframes.name, \  in intel_pipe_config_compare()
5212 					       &pipe_config->infoframes.name); \  in intel_pipe_config_compare()
5218 	if (!intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \  in intel_pipe_config_compare()
5219 				      &pipe_config->infoframes.name)) { \  in intel_pipe_config_compare()
5221 						&current_config->infoframes.name, \  in intel_pipe_config_compare()
5222 						&pipe_config->infoframes.name); \  in intel_pipe_config_compare()
5228 	if (!intel_compare_dp_as_sdp(&current_config->infoframes.name, \  in intel_pipe_config_compare()
5229 				      &pipe_config->infoframes.name)) { \  in intel_pipe_config_compare()
5231 						&current_config->infoframes.name, \  in intel_pipe_config_compare()
5232 						&pipe_config->infoframes.name); \  in intel_pipe_config_compare()
5238 	BUILD_BUG_ON(sizeof(current_config->name) != (len)); \  in intel_pipe_config_compare()
5239 	BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \  in intel_pipe_config_compare()
5240 	if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \  in intel_pipe_config_compare()
5242 					    current_config->name, \  in intel_pipe_config_compare()
5243 					    pipe_config->name, \  in intel_pipe_config_compare()
5250 	if (current_config->gamma_mode == pipe_config->gamma_mode && \  in intel_pipe_config_compare()
5252 				   current_config->lut, pipe_config->lut, \  in intel_pipe_config_compare()
5279 	((current_config->quirks | pipe_config->quirks) & (quirk))  in intel_pipe_config_compare()
5295 		if (!fastset || !pipe_config->update_m_n)  in intel_pipe_config_compare()
5385 	 * this requirement -> check these only if using panel replay  in intel_pipe_config_compare()
5387 	if (current_config->active_planes &&  in intel_pipe_config_compare()
5388 	    (current_config->has_panel_replay ||  in intel_pipe_config_compare()
5389 	     pipe_config->has_panel_replay)) {  in intel_pipe_config_compare()
5399 	if (dev_priv->display.dpll.mgr)  in intel_pipe_config_compare()
5403 	if (dev_priv->display.dpll.mgr || HAS_GMCH(dev_priv))  in intel_pipe_config_compare()
5416 	if (!fastset || !pipe_config->update_m_n) {  in intel_pipe_config_compare()
5424 	if (current_config->has_psr || pipe_config->has_psr)  in intel_pipe_config_compare()
5518 		assert_plane(plane, plane_state->planar_slave ||  in intel_verify_planes()
5519 			     plane_state->uapi.visible);  in intel_verify_planes()
5526 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_modeset_pipe()
5527 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);  in intel_modeset_pipe()
5530 	drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Full modeset due to %s\n",  in intel_modeset_pipe()
5531 		    crtc->base.base.id, crtc->base.name, reason);  in intel_modeset_pipe()
5533 	ret = drm_atomic_add_affected_connectors(&state->base,  in intel_modeset_pipe()
5534 						 &crtc->base);  in intel_modeset_pipe()
5550 	crtc_state->uapi.mode_changed = true;  in intel_modeset_pipe()
5556  * intel_modeset_pipes_in_mask_early - force a full modeset on a set of pipes
5570 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_modeset_pipes_in_mask_early()
5573 	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, mask) {  in intel_modeset_pipes_in_mask_early()
5577 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in intel_modeset_pipes_in_mask_early()
5581 		if (!crtc_state->hw.enable ||  in intel_modeset_pipes_in_mask_early()
5596 	crtc_state->uapi.mode_changed = true;  in intel_crtc_flag_modeset()
5598 	crtc_state->update_pipe = false;  in intel_crtc_flag_modeset()
5599 	crtc_state->update_m_n = false;  in intel_crtc_flag_modeset()
5600 	crtc_state->update_lrr = false;  in intel_crtc_flag_modeset()
5604  * intel_modeset_all_pipes_late - force a full modeset on all pipes
5617 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_modeset_all_pipes_late()
5620 	for_each_intel_crtc(&dev_priv->drm, crtc) {  in intel_modeset_all_pipes_late()
5624 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in intel_modeset_all_pipes_late()
5628 		if (!crtc_state->hw.active ||  in intel_modeset_all_pipes_late()
5638 		crtc_state->update_planes |= crtc_state->active_planes;  in intel_modeset_all_pipes_late()
5639 		crtc_state->async_flip_planes = 0;  in intel_modeset_all_pipes_late()
5640 		crtc_state->do_async_flip = false;  in intel_modeset_all_pipes_late()
5654 	state = drm_atomic_state_alloc(&i915->drm);  in intel_modeset_commit_pipes()
5656 		return -ENOMEM;  in intel_modeset_commit_pipes()
5658 	state->acquire_ctx = ctx;  in intel_modeset_commit_pipes()
5659 	to_intel_atomic_state(state)->internal = true;  in intel_modeset_commit_pipes()
5661 	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, pipe_mask) {  in intel_modeset_commit_pipes()
5670 		crtc_state->uapi.connectors_changed = true;  in intel_modeset_commit_pipes()
5681  * This implements the workaround described in the "notes" section of the mode
5697 		if (!crtc_state->hw.active ||  in hsw_mode_set_planes_workaround()
5706 			first_pipe = crtc->pipe;  in hsw_mode_set_planes_workaround()
5715 	for_each_intel_crtc(state->base.dev, crtc) {  in hsw_mode_set_planes_workaround()
5716 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in hsw_mode_set_planes_workaround()
5720 		crtc_state->hsw_workaround_pipe = INVALID_PIPE;  in hsw_mode_set_planes_workaround()
5722 		if (!crtc_state->hw.active ||  in hsw_mode_set_planes_workaround()
5730 		enabled_pipe = crtc->pipe;  in hsw_mode_set_planes_workaround()
5734 		first_crtc_state->hsw_workaround_pipe = enabled_pipe;  in hsw_mode_set_planes_workaround()
5736 		other_crtc_state->hsw_workaround_pipe = first_pipe;  in hsw_mode_set_planes_workaround()
5749 		if (crtc_state->hw.active)  in intel_calc_active_pipes()
5750 			active_pipes |= BIT(crtc->pipe);  in intel_calc_active_pipes()
5752 			active_pipes &= ~BIT(crtc->pipe);  in intel_calc_active_pipes()
5760 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_modeset_checks()
5762 	state->modeset = true;  in intel_modeset_checks()
5773 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);  in intel_crtc_check_fastset()
5774 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in intel_crtc_check_fastset()
5777 	if (old_crtc_state->vrr.in_range != new_crtc_state->vrr.in_range)  in intel_crtc_check_fastset()
5778 		new_crtc_state->update_lrr = false;  in intel_crtc_check_fastset()
5781 		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] fastset requirement not met, forcing full modeset\n",  in intel_crtc_check_fastset()
5782 			    crtc->base.base.id, crtc->base.name);  in intel_crtc_check_fastset()
5784 		new_crtc_state->uapi.mode_changed = false;  in intel_crtc_check_fastset()
5786 	if (intel_compare_link_m_n(&old_crtc_state->dp_m_n,  in intel_crtc_check_fastset()
5787 				   &new_crtc_state->dp_m_n))  in intel_crtc_check_fastset()
5788 		new_crtc_state->update_m_n = false;  in intel_crtc_check_fastset()
5790 …if ((old_crtc_state->hw.adjusted_mode.crtc_vtotal == new_crtc_state->hw.adjusted_mode.crtc_vtotal …  in intel_crtc_check_fastset()
5791 …old_crtc_state->hw.adjusted_mode.crtc_vblank_end == new_crtc_state->hw.adjusted_mode.crtc_vblank_e…  in intel_crtc_check_fastset()
5792 		new_crtc_state->update_lrr = false;  in intel_crtc_check_fastset()
5797 		new_crtc_state->update_pipe = true;  in intel_crtc_check_fastset()
5804 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_crtc_add_planes_to_state()
5807 	for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {  in intel_crtc_add_planes_to_state()
5810 		if ((plane_ids_mask & BIT(plane->id)) == 0)  in intel_crtc_add_planes_to_state()
5830 					      old_crtc_state->enabled_planes |  in intel_atomic_add_affected_planes()
5831 					      new_crtc_state->enabled_planes);  in intel_atomic_add_affected_planes()
5852 		if (plane->pipe == crtc->pipe)  in intel_crtc_add_joiner_planes()
5853 			plane_ids |= BIT(plane->id);  in intel_crtc_add_joiner_planes()
5861 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_joiner_add_affected_planes()
5869 		for_each_intel_crtc_in_pipe_mask(&i915->drm, other,  in intel_joiner_add_affected_planes()
5870 						 crtc_state->joiner_pipes) {  in intel_joiner_add_affected_planes()
5887 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_atomic_check_planes()
5905 			drm_dbg_atomic(&dev_priv->drm,  in intel_atomic_check_planes()
5907 				       plane->base.base.id, plane->base.name);  in intel_atomic_check_planes()
5928 		old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);  in intel_atomic_check_planes()
5929 		new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);  in intel_atomic_check_planes()
5949 		struct drm_i915_private *i915 = to_i915(crtc->base.dev);  in intel_atomic_check_crtcs()
5954 			drm_dbg_atomic(&i915->drm,  in intel_atomic_check_crtcs()
5956 				       crtc->base.base.id, crtc->base.name);  in intel_atomic_check_crtcs()
5972 		if (new_crtc_state->hw.enable &&  in intel_cpu_transcoders_need_modeset()
5973 		    transcoders & BIT(new_crtc_state->cpu_transcoder) &&  in intel_cpu_transcoders_need_modeset()
5989 		if (new_crtc_state->hw.enable &&  in intel_pipes_need_modeset()
5990 		    pipes & BIT(crtc->pipe) &&  in intel_pipes_need_modeset()
6001 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_atomic_check_joiner()
6006 	if (!primary_crtc_state->joiner_pipes)  in intel_atomic_check_joiner()
6010 	if (drm_WARN_ON(&i915->drm,  in intel_atomic_check_joiner()
6011 			primary_crtc->pipe != joiner_primary_pipe(primary_crtc_state)))  in intel_atomic_check_joiner()
6012 		return -EINVAL;  in intel_atomic_check_joiner()
6014 	if (primary_crtc_state->joiner_pipes & ~joiner_pipes(i915)) {  in intel_atomic_check_joiner()
6015 		drm_dbg_kms(&i915->drm,  in intel_atomic_check_joiner()
6018 			    primary_crtc->base.base.id, primary_crtc->base.name,  in intel_atomic_check_joiner()
6019 			    primary_crtc_state->joiner_pipes, joiner_pipes(i915));  in intel_atomic_check_joiner()
6020 		return -EINVAL;  in intel_atomic_check_joiner()
6023 	for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc,  in intel_atomic_check_joiner()
6028 		secondary_crtc_state = intel_atomic_get_crtc_state(&state->base, secondary_crtc);  in intel_atomic_check_joiner()
6033 		if (secondary_crtc_state->uapi.enable) {  in intel_atomic_check_joiner()
6034 			drm_dbg_kms(&i915->drm,  in intel_atomic_check_joiner()
6037 				    secondary_crtc->base.base.id, secondary_crtc->base.name,  in intel_atomic_check_joiner()
6038 				    primary_crtc->base.base.id, primary_crtc->base.name);  in intel_atomic_check_joiner()
6039 			return -EINVAL;  in intel_atomic_check_joiner()
6049 		if (WARN_ON(drm_crtc_index(&primary_crtc->base) >  in intel_atomic_check_joiner()
6050 			    drm_crtc_index(&secondary_crtc->base)))  in intel_atomic_check_joiner()
6051 			return -EINVAL;  in intel_atomic_check_joiner()
6053 		drm_dbg_kms(&i915->drm,  in intel_atomic_check_joiner()
6055 			    secondary_crtc->base.base.id, secondary_crtc->base.name,  in intel_atomic_check_joiner()
6056 			    primary_crtc->base.base.id, primary_crtc->base.name);  in intel_atomic_check_joiner()
6058 		secondary_crtc_state->joiner_pipes =  in intel_atomic_check_joiner()
6059 			primary_crtc_state->joiner_pipes;  in intel_atomic_check_joiner()
6072 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in kill_joiner_secondaries()
6077 	for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc,  in kill_joiner_secondaries()
6082 		secondary_crtc_state->joiner_pipes = 0;  in kill_joiner_secondaries()
6087 	primary_crtc_state->joiner_pipes = 0;  in kill_joiner_secondaries()
6111 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_async_flip_check_uapi()
6119 	if (!new_crtc_state->uapi.async_flip)  in intel_async_flip_check_uapi()
6122 	if (!new_crtc_state->uapi.active) {  in intel_async_flip_check_uapi()
6123 		drm_dbg_kms(&i915->drm,  in intel_async_flip_check_uapi()
6125 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_uapi()
6126 		return -EINVAL;  in intel_async_flip_check_uapi()
6130 		drm_dbg_kms(&i915->drm,  in intel_async_flip_check_uapi()
6132 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_uapi()
6133 		return -EINVAL;  in intel_async_flip_check_uapi()
6140 	if (new_crtc_state->joiner_pipes) {  in intel_async_flip_check_uapi()
6141 		drm_dbg_kms(&i915->drm,  in intel_async_flip_check_uapi()
6143 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_uapi()
6144 		return -EINVAL;  in intel_async_flip_check_uapi()
6149 		if (plane->pipe != crtc->pipe)  in intel_async_flip_check_uapi()
6159 		if (!plane->async_flip) {  in intel_async_flip_check_uapi()
6160 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_uapi()
6162 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_uapi()
6163 			return -EINVAL;  in intel_async_flip_check_uapi()
6166 		if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) {  in intel_async_flip_check_uapi()
6167 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_uapi()
6169 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_uapi()
6170 			return -EINVAL;  in intel_async_flip_check_uapi()
6179 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_async_flip_check_hw()
6188 	if (!new_crtc_state->uapi.async_flip)  in intel_async_flip_check_hw()
6191 	if (!new_crtc_state->hw.active) {  in intel_async_flip_check_hw()
6192 		drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6194 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_hw()
6195 		return -EINVAL;  in intel_async_flip_check_hw()
6199 		drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6201 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_hw()
6202 		return -EINVAL;  in intel_async_flip_check_hw()
6205 	if (old_crtc_state->active_planes != new_crtc_state->active_planes) {  in intel_async_flip_check_hw()
6206 		drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6208 			    crtc->base.base.id, crtc->base.name);  in intel_async_flip_check_hw()
6209 		return -EINVAL;  in intel_async_flip_check_hw()
6214 		if (plane->pipe != crtc->pipe)  in intel_async_flip_check_hw()
6222 		if (drm_WARN_ON(&i915->drm,  in intel_async_flip_check_hw()
6223 				new_crtc_state->do_async_flip && !plane->async_flip))  in intel_async_flip_check_hw()
6224 			return -EINVAL;  in intel_async_flip_check_hw()
6234 		if (!plane->async_flip)  in intel_async_flip_check_hw()
6242 		switch (new_plane_state->hw.fb->modifier) {  in intel_async_flip_check_hw()
6251 				drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6253 					    plane->base.base.id, plane->base.name,  in intel_async_flip_check_hw()
6254 					    new_plane_state->hw.fb->modifier, DISPLAY_VER(i915));  in intel_async_flip_check_hw()
6255 				return -EINVAL;  in intel_async_flip_check_hw()
6267 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6269 				    plane->base.base.id, plane->base.name,  in intel_async_flip_check_hw()
6270 				    new_plane_state->hw.fb->modifier);  in intel_async_flip_check_hw()
6271 			return -EINVAL;  in intel_async_flip_check_hw()
6274 		if (new_plane_state->hw.fb->format->num_planes > 1) {  in intel_async_flip_check_hw()
6275 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6277 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6278 			return -EINVAL;  in intel_async_flip_check_hw()
6285 		if (!new_crtc_state->do_async_flip)  in intel_async_flip_check_hw()
6288 		if (old_plane_state->view.color_plane[0].mapping_stride !=  in intel_async_flip_check_hw()
6289 		    new_plane_state->view.color_plane[0].mapping_stride) {  in intel_async_flip_check_hw()
6290 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6292 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6293 			return -EINVAL;  in intel_async_flip_check_hw()
6296 		if (old_plane_state->hw.fb->modifier !=  in intel_async_flip_check_hw()
6297 		    new_plane_state->hw.fb->modifier) {  in intel_async_flip_check_hw()
6298 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6300 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6301 			return -EINVAL;  in intel_async_flip_check_hw()
6304 		if (old_plane_state->hw.fb->format !=  in intel_async_flip_check_hw()
6305 		    new_plane_state->hw.fb->format) {  in intel_async_flip_check_hw()
6306 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6308 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6309 			return -EINVAL;  in intel_async_flip_check_hw()
6312 		if (old_plane_state->hw.rotation !=  in intel_async_flip_check_hw()
6313 		    new_plane_state->hw.rotation) {  in intel_async_flip_check_hw()
6314 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6316 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6317 			return -EINVAL;  in intel_async_flip_check_hw()
6320 		if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||  in intel_async_flip_check_hw()
6321 		    !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {  in intel_async_flip_check_hw()
6322 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6323 				    "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n",  in intel_async_flip_check_hw()
6324 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6325 			return -EINVAL;  in intel_async_flip_check_hw()
6328 		if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {  in intel_async_flip_check_hw()
6329 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6331 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6332 			return -EINVAL;  in intel_async_flip_check_hw()
6335 		if (old_plane_state->hw.pixel_blend_mode !=  in intel_async_flip_check_hw()
6336 		    new_plane_state->hw.pixel_blend_mode) {  in intel_async_flip_check_hw()
6337 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6338 				    "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n",  in intel_async_flip_check_hw()
6339 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6340 			return -EINVAL;  in intel_async_flip_check_hw()
6343 		if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {  in intel_async_flip_check_hw()
6344 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6346 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6347 			return -EINVAL;  in intel_async_flip_check_hw()
6350 		if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {  in intel_async_flip_check_hw()
6351 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6353 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6354 			return -EINVAL;  in intel_async_flip_check_hw()
6358 		if (old_plane_state->decrypt != new_plane_state->decrypt) {  in intel_async_flip_check_hw()
6359 			drm_dbg_kms(&i915->drm,  in intel_async_flip_check_hw()
6361 				    plane->base.base.id, plane->base.name);  in intel_async_flip_check_hw()
6362 			return -EINVAL;  in intel_async_flip_check_hw()
6371 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_joiner_add_affected_crtcs()
6379 		affected_pipes |= crtc_state->joiner_pipes;  in intel_joiner_add_affected_crtcs()
6381 			modeset_pipes |= crtc_state->joiner_pipes;  in intel_joiner_add_affected_crtcs()
6384 	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) {  in intel_joiner_add_affected_crtcs()
6385 		crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);  in intel_joiner_add_affected_crtcs()
6390 	for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) {  in intel_joiner_add_affected_crtcs()
6395 		crtc_state->uapi.mode_changed = true;  in intel_joiner_add_affected_crtcs()
6397 		ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);  in intel_joiner_add_affected_crtcs()
6407 		/* Kill old joiner link, we may re-establish afterwards */  in intel_joiner_add_affected_crtcs()
6420 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_atomic_check_config()
6445 		if (drm_WARN_ON(&i915->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))  in intel_atomic_check_config()
6452 		if (!new_crtc_state->hw.enable)  in intel_atomic_check_config()
6464 		if (drm_WARN_ON(&i915->drm, intel_crtc_is_joiner_secondary(new_crtc_state)))  in intel_atomic_check_config()
6467 		if (!new_crtc_state->hw.enable)  in intel_atomic_check_config()
6477 		*failed_pipe = crtc->pipe;  in intel_atomic_check_config()
6501 			if (ret == -EINVAL &&  in intel_atomic_check_config_and_link()
6514 		if (ret != -EAGAIN)  in intel_atomic_check_config_and_link()
6521  * intel_atomic_check - validate state object
6536 		return -ENODEV;  in intel_atomic_check()
6544 		if (!state->internal)  in intel_atomic_check()
6545 			new_crtc_state->inherited = false;  in intel_atomic_check()
6547 		if (new_crtc_state->inherited != old_crtc_state->inherited)  in intel_atomic_check()
6548 			new_crtc_state->uapi.mode_changed = true;  in intel_atomic_check()
6550 		if (new_crtc_state->uapi.scaling_filter !=  in intel_atomic_check()
6551 		    old_crtc_state->uapi.scaling_filter)  in intel_atomic_check()
6552 			new_crtc_state->uapi.mode_changed = true;  in intel_atomic_check()
6557 	ret = drm_atomic_helper_check_modeset(dev, &state->base);  in intel_atomic_check()
6576 			drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable);  in intel_atomic_check()
6607 		if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))  in intel_atomic_check()
6614 			enum transcoder master = new_crtc_state->mst_master_transcoder;  in intel_atomic_check()
6621 			u8 trans = new_crtc_state->sync_mode_slaves_mask;  in intel_atomic_check()
6623 			if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)  in intel_atomic_check()
6624 				trans |= BIT(new_crtc_state->master_transcoder);  in intel_atomic_check()
6630 		if (new_crtc_state->joiner_pipes) {  in intel_atomic_check()
6631 			if (intel_pipes_need_modeset(state, new_crtc_state->joiner_pipes))  in intel_atomic_check()
6647 		drm_dbg_kms(&dev_priv->drm,  in intel_atomic_check()
6649 		ret = -EINVAL;  in intel_atomic_check()
6703 		drm_WARN_ON(&dev_priv->drm,  in intel_atomic_check()
6719 	if (ret == -EDEADLK)  in intel_atomic_check()
6739 	ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);  in intel_atomic_prepare_commit()
6752 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_crtc_arm_fifo_underrun()
6754 	if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes)  in intel_crtc_arm_fifo_underrun()
6755 		intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);  in intel_crtc_arm_fifo_underrun()
6757 	if (crtc_state->has_pch_encoder) {  in intel_crtc_arm_fifo_underrun()
6768 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);  in intel_pipe_fastset()
6769 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_pipe_fastset()
6773 	 * that in compute_mode_changes we check the native mode (not the pfit  in intel_pipe_fastset()
6774 	 * mode) to see if we can flip rather than do a full mode set. In the  in intel_pipe_fastset()
6783 		if (new_crtc_state->pch_pfit.enabled)  in intel_pipe_fastset()
6786 		if (new_crtc_state->pch_pfit.enabled)  in intel_pipe_fastset()
6788 		else if (old_crtc_state->pch_pfit.enabled)  in intel_pipe_fastset()
6804 	if (new_crtc_state->update_m_n)  in intel_pipe_fastset()
6805 		intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,  in intel_pipe_fastset()
6806 					       &new_crtc_state->dp_m_n);  in intel_pipe_fastset()
6808 	if (new_crtc_state->update_lrr)  in intel_pipe_fastset()
6815 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in commit_pipe_pre_planes()
6845 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in commit_pipe_post_planes()
6865 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_enable_crtc()
6873 	for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,  in intel_enable_crtc()
6882 	dev_priv->display.funcs.display->crtc_enable(state, crtc);  in intel_enable_crtc()
6884 	/* vblanks work again, re-enable pipe CRC. */  in intel_enable_crtc()
6891 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_pre_update_crtc()
6898 	if (old_crtc_state->inherited ||  in intel_pre_update_crtc()
6905 		if (new_crtc_state->preload_luts &&  in intel_pre_update_crtc()
6925 	drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF));  in intel_pre_update_crtc()
6959 	    new_crtc_state->update_m_n || new_crtc_state->update_lrr)  in intel_update_crtc()
6961 						 new_crtc_state->vrr.enable);  in intel_update_crtc()
6970 	    old_crtc_state->inherited)  in intel_update_crtc()
6977 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in intel_old_crtc_state_disables()
6986 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc,  in intel_old_crtc_state_disables()
6990 	dev_priv->display.funcs.display->crtc_disable(state, crtc);  in intel_old_crtc_state_disables()
6992 	for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc,  in intel_old_crtc_state_disables()
6997 		pipe_crtc->active = false;  in intel_old_crtc_state_disables()
7000 		if (!new_pipe_crtc_state->hw.active)  in intel_old_crtc_state_disables()
7007 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_commit_modeset_disables()
7024 		if (!old_crtc_state->hw.active)  in intel_commit_modeset_disables()
7027 		disable_pipes |= BIT(crtc->pipe);  in intel_commit_modeset_disables()
7031 		if ((disable_pipes & BIT(crtc->pipe)) == 0)  in intel_commit_modeset_disables()
7036 		drm_vblank_work_flush_all(&crtc->base);  in intel_commit_modeset_disables()
7041 		if ((disable_pipes & BIT(crtc->pipe)) == 0)  in intel_commit_modeset_disables()
7063 		if ((disable_pipes & BIT(crtc->pipe)) == 0)  in intel_commit_modeset_disables()
7074 	drm_WARN_ON(&i915->drm, disable_pipes);  in intel_commit_modeset_disables()
7084 		if (!new_crtc_state->hw.active)  in intel_commit_modeset_enables()
7092 		if (!new_crtc_state->hw.active)  in intel_commit_modeset_enables()
7101 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);  in skl_commit_modeset_enables()
7109 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
7111 		if (!new_crtc_state->hw.active)  in skl_commit_modeset_enables()
7116 			entries[pipe] = old_crtc_state->wm.skl.ddb;  in skl_commit_modeset_enables()
7133 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
7150 			enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
7155 			if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,  in skl_commit_modeset_enables()
7159 			entries[pipe] = new_crtc_state->wm.skl.ddb;  in skl_commit_modeset_enables()
7170 			if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,  in skl_commit_modeset_enables()
7171 						 &old_crtc_state->wm.skl.ddb) &&  in skl_commit_modeset_enables()
7186 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
7208 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
7225 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
7238 		enum pipe pipe = crtc->pipe;  in skl_commit_modeset_enables()
7243 		drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,  in skl_commit_modeset_enables()
7246 		entries[pipe] = new_crtc_state->wm.skl.ddb;  in skl_commit_modeset_enables()
7252 	drm_WARN_ON(&dev_priv->drm, modeset_pipes);  in skl_commit_modeset_enables()
7253 	drm_WARN_ON(&dev_priv->drm, update_pipes);  in skl_commit_modeset_enables()
7258 	struct drm_i915_private *i915 = to_i915(intel_state->base.dev);  in intel_atomic_commit_fence_wait()
7263 	for_each_new_plane_in_state(&intel_state->base, plane, new_plane_state, i) {  in intel_atomic_commit_fence_wait()
7264 		if (new_plane_state->fence) {  in intel_atomic_commit_fence_wait()
7265 			ret = dma_fence_wait_timeout(new_plane_state->fence, false,  in intel_atomic_commit_fence_wait()
7270 			dma_fence_put(new_plane_state->fence);  in intel_atomic_commit_fence_wait()
7271 			new_plane_state->fence = NULL;  in intel_atomic_commit_fence_wait()
7280 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_atomic_cleanup_work()
7288 	drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);  in intel_atomic_cleanup_work()
7289 	drm_atomic_helper_commit_cleanup_done(&state->base);  in intel_atomic_cleanup_work()
7290 	drm_atomic_state_put(&state->base);  in intel_atomic_cleanup_work()
7295 	struct drm_i915_private *i915 = to_i915(state->base.dev);  in intel_atomic_prepare_plane_clear_colors()
7301 		struct drm_framebuffer *fb = plane_state->hw.fb;  in intel_atomic_prepare_plane_clear_colors()
7317 		 * - 4 x 4 bytes per-channel value  in intel_atomic_prepare_plane_clear_colors()
7319 		 * - 8 bytes native color value used by the display  in intel_atomic_prepare_plane_clear_colors()
7321 		 *    above per-channel values)  in intel_atomic_prepare_plane_clear_colors()
7328 						     fb->offsets[cc_plane] + 16,  in intel_atomic_prepare_plane_clear_colors()
7329 						     &plane_state->ccval,  in intel_atomic_prepare_plane_clear_colors()
7330 						     sizeof(plane_state->ccval));  in intel_atomic_prepare_plane_clear_colors()
7332 		drm_WARN_ON(&i915->drm, ret);  in intel_atomic_prepare_plane_clear_colors()
7338 	struct drm_device *dev = state->base.dev;  in intel_atomic_commit_tail()
7350 	drm_atomic_helper_wait_for_dependencies(&state->base);  in intel_atomic_commit_tail()
7351 	drm_dp_mst_atomic_wait_for_dependencies(&state->base);  in intel_atomic_commit_tail()
7363 	 * 3. Due to some long delay PSR is re-entered  in intel_atomic_commit_tail()
7364 	 * 4. DC5 entry -> DMC saves the already written new  in intel_atomic_commit_tail()
7367 	 * 5. DC5 exit -> DMC restores a mixture of old and  in intel_atomic_commit_tail()
7369 	 * 6. PSR exit -> hardware latches a mixture of old and  in intel_atomic_commit_tail()
7370 	 *    new register values -> corrupted frame, or worse  in intel_atomic_commit_tail()
7389 			intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);  in intel_atomic_commit_tail()
7396 	/* FIXME: Eventually get rid of our crtc->config pointer */  in intel_atomic_commit_tail()
7398 		crtc->config = new_crtc_state;  in intel_atomic_commit_tail()
7408 	if (state->modeset) {  in intel_atomic_commit_tail()
7409 		drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);  in intel_atomic_commit_tail()
7423 		if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {  in intel_atomic_commit_tail()
7424 			spin_lock_irq(&dev->event_lock);  in intel_atomic_commit_tail()
7425 			drm_crtc_send_vblank_event(&crtc->base,  in intel_atomic_commit_tail()
7426 						   new_crtc_state->uapi.event);  in intel_atomic_commit_tail()
7427 			spin_unlock_irq(&dev->event_lock);  in intel_atomic_commit_tail()
7429 			new_crtc_state->uapi.event = NULL;  in intel_atomic_commit_tail()
7438 		if (new_crtc_state->do_async_flip)  in intel_atomic_commit_tail()
7443 	dev_priv->display.funcs.display->commit_modeset_enables(state);  in intel_atomic_commit_tail()
7445 	if (state->modeset)  in intel_atomic_commit_tail()
7453 	 * - wrap the optimization/post_plane_update stuff into a per-crtc work.  in intel_atomic_commit_tail()
7454 	 * - schedule that vblank worker _before_ calling hw_done  in intel_atomic_commit_tail()
7455 	 * - at the start of commit_tail, cancel it _synchrously  in intel_atomic_commit_tail()
7456 	 * - switch over to the vblank wait helper in the core after that since  in intel_atomic_commit_tail()
7459 	drm_atomic_helper_wait_for_flip_done(dev, &state->base);  in intel_atomic_commit_tail()
7462 		if (new_crtc_state->do_async_flip)  in intel_atomic_commit_tail()
7470 	 * optimal watermarks on platforms that need two-step watermark  in intel_atomic_commit_tail()
7479 		 * So re-enable underrun reporting after some planes get enabled.  in intel_atomic_commit_tail()
7486 			intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);  in intel_atomic_commit_tail()
7496 		intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);  in intel_atomic_commit_tail()
7514 		 * FIXME get rid of this funny new->old swapping  in intel_atomic_commit_tail()
7516 		old_crtc_state->dsb_color_vblank = fetch_and_zero(&new_crtc_state->dsb_color_vblank);  in intel_atomic_commit_tail()
7517 		old_crtc_state->dsb_color_commit = fetch_and_zero(&new_crtc_state->dsb_color_commit);  in intel_atomic_commit_tail()
7524 	if (state->modeset)  in intel_atomic_commit_tail()
7530 	drm_atomic_helper_commit_hw_done(&state->base);  in intel_atomic_commit_tail()
7533 	if (state->modeset) {  in intel_atomic_commit_tail()
7537 		 * so enable debugging for the next modeset - and hope we catch  in intel_atomic_commit_tail()
7540 		intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);  in intel_atomic_commit_tail()
7543 	 * Delay re-enabling DC states by 17 ms to avoid the off->on->off  in intel_atomic_commit_tail()
7547 	intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);  in intel_atomic_commit_tail()
7552 	 * are executed inline. For out-of-line asynchronous modesets/flips,  in intel_atomic_commit_tail()
7557 	INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);  in intel_atomic_commit_tail()
7558 	queue_work(system_highpri_wq, &state->base.commit_work);  in intel_atomic_commit_tail()
7577 		intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),  in intel_atomic_track_fbs()
7578 					to_intel_frontbuffer(new_plane_state->hw.fb),  in intel_atomic_track_fbs()
7579 					plane->frontbuffer_bit);  in intel_atomic_track_fbs()
7586 	ret = drm_atomic_helper_setup_commit(&state->base, nonblock);  in intel_atomic_setup_commit()
7601 	ret = drm_atomic_helper_swap_state(&state->base, true);  in intel_atomic_swap_state()
7621 	state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);  in intel_atomic_commit()
7631 	 * Unset state->legacy_cursor_update before the call to  in intel_atomic_commit()
7640 	if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) {  in intel_atomic_commit()
7646 			if (new_crtc_state->wm.need_postvbl_update ||  in intel_atomic_commit()
7647 			    new_crtc_state->update_wm_post)  in intel_atomic_commit()
7648 				state->base.legacy_cursor_update = false;  in intel_atomic_commit()
7653 		drm_dbg_atomic(&dev_priv->drm,  in intel_atomic_commit()
7655 		intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);  in intel_atomic_commit()
7671 		drm_atomic_helper_unprepare_planes(dev, &state->base);  in intel_atomic_commit()
7672 		intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);  in intel_atomic_commit()
7676 	drm_atomic_state_get(&state->base);  in intel_atomic_commit()
7677 	INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);  in intel_atomic_commit()
7679 	if (nonblock && state->modeset) {  in intel_atomic_commit()
7680 		queue_work(dev_priv->display.wq.modeset, &state->base.commit_work);  in intel_atomic_commit()
7682 		queue_work(dev_priv->display.wq.flip, &state->base.commit_work);  in intel_atomic_commit()
7684 		if (state->modeset)  in intel_atomic_commit()
7685 			flush_workqueue(dev_priv->display.wq.modeset);  in intel_atomic_commit()
7693  * intel_plane_destroy - destroy a plane
7712 	drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);  in intel_get_pipe_from_crtc_id_ioctl()
7714 		return -ENOENT;  in intel_get_pipe_from_crtc_id_ioctl()
7717 	pipe_from_crtc_id->pipe = crtc->pipe;  in intel_get_pipe_from_crtc_id_ioctl()
7724 	struct drm_device *dev = encoder->base.dev;  in intel_encoder_possible_clones()
7730 			possible_clones |= drm_encoder_mask(&source_encoder->base);  in intel_encoder_possible_clones()
7738 	struct drm_device *dev = encoder->base.dev;  in intel_encoder_possible_crtcs()
7742 	for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask)  in intel_encoder_possible_crtcs()
7743 		possible_crtcs |= drm_crtc_mask(&crtc->base);  in intel_encoder_possible_crtcs()
7778 	if (!dev_priv->display.vbt.int_crt_support)  in intel_ddi_crt_present()
7786 	return !drm_WARN(&i915->drm, !(DISPLAY_RUNTIME_INFO(i915)->port_mask & BIT(port)),  in assert_port_valid()
7792 	struct intel_display *display = &dev_priv->display;  in intel_setup_outputs()
7848 		if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support)  in intel_setup_outputs()
7854 		 * (no way to plug in a DP->HDMI dongle) the DDC pins for  in intel_setup_outputs()
7861 		 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap  in intel_setup_outputs()
7905 			drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");  in intel_setup_outputs()
7908 				drm_dbg_kms(&dev_priv->drm,  in intel_setup_outputs()
7920 			drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");  in intel_setup_outputs()
7927 				drm_dbg_kms(&dev_priv->drm,  in intel_setup_outputs()
7948 	for_each_intel_encoder(&dev_priv->drm, encoder) {  in intel_setup_outputs()
7949 		encoder->base.possible_crtcs =  in intel_setup_outputs()
7951 		encoder->base.possible_clones =  in intel_setup_outputs()
7957 	drm_helper_move_panel_connectors_to_head(&dev_priv->drm);  in intel_setup_outputs()
7962 	int max_dotclock = i915->display.cdclk.max_dotclk_freq;  in max_dotclock()
7972 				      const struct drm_display_mode *mode)  in intel_mode_valid()  argument
7980 	 * of DBLSCAN modes to the output's mode list when they detect  in intel_mode_valid()
7981 	 * the scaling mode property on the connector. And they don't  in intel_mode_valid()
7986 	 * reject modes with the DBLSCAN flag in encoder->compute_config().  in intel_mode_valid()
7987 	 * And we always reject DBLSCAN modes in connector->mode_valid()  in intel_mode_valid()
7988 	 * as we never want such modes on the connector's mode list.  in intel_mode_valid()
7991 	if (mode->vscan > 1)  in intel_mode_valid()
7994 	if (mode->flags & DRM_MODE_FLAG_HSKEW)  in intel_mode_valid()
7997 	if (mode->flags & (DRM_MODE_FLAG_CSYNC |  in intel_mode_valid()
8002 	if (mode->flags & (DRM_MODE_FLAG_BCAST |  in intel_mode_valid()
8011 	if (mode->clock > max_dotclock(dev_priv))  in intel_mode_valid()
8038 	if (mode->hdisplay > hdisplay_max ||  in intel_mode_valid()
8039 	    mode->hsync_start > htotal_max ||  in intel_mode_valid()
8040 	    mode->hsync_end > htotal_max ||  in intel_mode_valid()
8041 	    mode->htotal > htotal_max)  in intel_mode_valid()
8044 	if (mode->vdisplay > vdisplay_max ||  in intel_mode_valid()
8045 	    mode->vsync_start > vtotal_max ||  in intel_mode_valid()
8046 	    mode->vsync_end > vtotal_max ||  in intel_mode_valid()
8047 	    mode->vtotal > vtotal_max)  in intel_mode_valid()
8054 						     const struct drm_display_mode *mode)  in intel_cpu_transcoder_mode_valid()  argument
8061 		if (mode->hdisplay < 64 ||  in intel_cpu_transcoder_mode_valid()
8062 		    mode->htotal - mode->hdisplay < 32)  in intel_cpu_transcoder_mode_valid()
8065 		if (mode->vtotal - mode->vdisplay < 5)  in intel_cpu_transcoder_mode_valid()
8068 		if (mode->htotal - mode->hdisplay < 32)  in intel_cpu_transcoder_mode_valid()
8071 		if (mode->vtotal - mode->vdisplay < 3)  in intel_cpu_transcoder_mode_valid()
8080 	    mode->hsync_start == mode->hdisplay)  in intel_cpu_transcoder_mode_valid()
8088 				const struct drm_display_mode *mode,  in intel_mode_valid_max_plane_size()  argument
8113 	if (mode->hdisplay > plane_width_max)  in intel_mode_valid_max_plane_size()
8116 	if (mode->vdisplay > plane_height_max)  in intel_mode_valid_max_plane_size()
8168  * intel_init_display_hooks - initialize the display modesetting hooks
8174 		dev_priv->display.funcs.display = &skl_display_funcs;  in intel_init_display_hooks()
8176 		dev_priv->display.funcs.display = &ddi_display_funcs;  in intel_init_display_hooks()
8178 		dev_priv->display.funcs.display = &pch_split_display_funcs;  in intel_init_display_hooks()
8181 		dev_priv->display.funcs.display = &vlv_display_funcs;  in intel_init_display_hooks()
8183 		dev_priv->display.funcs.display = &i9xx_display_funcs;  in intel_init_display_hooks()
8196 		return -ENOMEM;  in intel_initial_commit()
8200 	state->acquire_ctx = &ctx;  in intel_initial_commit()
8201 	to_intel_atomic_state(state)->internal = true;  in intel_initial_commit()
8213 		if (crtc_state->hw.active) {  in intel_initial_commit()
8216 			ret = drm_atomic_add_affected_planes(state, &crtc->base);  in intel_initial_commit()
8226 			crtc_state->uapi.color_mgmt_changed = true;  in intel_initial_commit()
8229 						    crtc_state->uapi.encoder_mask) {  in intel_initial_commit()
8230 				if (encoder->initial_fastset_check &&  in intel_initial_commit()
8231 				    !encoder->initial_fastset_check(encoder, crtc_state)) {  in intel_initial_commit()
8233 										 &crtc->base);  in intel_initial_commit()
8244 	if (ret == -EDEADLK) {  in intel_initial_commit()
8273 	drm_WARN_ON(&dev_priv->drm,  in i830_enable_pipe()
8276 	drm_dbg_kms(&dev_priv->drm,  in i830_enable_pipe()
8283 		((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |  in i830_enable_pipe()
8289 		       HACTIVE(640 - 1) | HTOTAL(800 - 1));  in i830_enable_pipe()
8291 		       HBLANK_START(640 - 1) | HBLANK_END(800 - 1));  in i830_enable_pipe()
8293 		       HSYNC_START(656 - 1) | HSYNC_END(752 - 1));  in i830_enable_pipe()
8295 		       VACTIVE(480 - 1) | VTOTAL(525 - 1));  in i830_enable_pipe()
8297 		       VBLANK_START(480 - 1) | VBLANK_END(525 - 1));  in i830_enable_pipe()
8299 		       VSYNC_START(490 - 1) | VSYNC_END(492 - 1));  in i830_enable_pipe()
8301 		       PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));  in i830_enable_pipe()
8307 	 * Apparently we need to have VGA mode enabled prior to changing  in i830_enable_pipe()
8343 	drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",  in i830_disable_pipe()
8346 	drm_WARN_ON(&dev_priv->drm,  in i830_disable_pipe()
8348 	drm_WARN_ON(&dev_priv->drm,  in i830_disable_pipe()
8350 	drm_WARN_ON(&dev_priv->drm,  in i830_disable_pipe()
8352 	drm_WARN_ON(&dev_priv->drm,  in i830_disable_pipe()
8354 	drm_WARN_ON(&dev_priv->drm,  in i830_disable_pipe()
8372 	drm_connector_list_iter_begin(&i915->drm, &conn_iter);  in intel_hpd_poll_fini()
8374 		if (connector->modeset_retry_work.func &&  in intel_hpd_poll_fini()
8375 		    cancel_work_sync(&connector->modeset_retry_work))  in intel_hpd_poll_fini()
8376 			drm_connector_put(&connector->base);  in intel_hpd_poll_fini()
8377 		if (connector->hdcp.shim) {  in intel_hpd_poll_fini()
8378 			cancel_delayed_work_sync(&connector->hdcp.check_work);  in intel_hpd_poll_fini()
8379 			cancel_work_sync(&connector->hdcp.prop_work);  in intel_hpd_poll_fini()