Lines Matching +full:hpd +full:- +full:reliable +full:- +full:delay
99 level = intel_bios_hdmi_level_shift(encoder->devdata); in intel_ddi_hdmi_level()
101 level = trans->hdmi_default_entry; in intel_ddi_hdmi_level()
124 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_prepare_dp_ddi_buffers()
127 enum port port = encoder->port; in hsw_prepare_dp_ddi_buffers()
130 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in hsw_prepare_dp_ddi_buffers()
131 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in hsw_prepare_dp_ddi_buffers()
136 intel_bios_dp_boost_level(encoder->devdata)) in hsw_prepare_dp_ddi_buffers()
141 trans->entries[i].hsw.trans1 | iboost_bit); in hsw_prepare_dp_ddi_buffers()
143 trans->entries[i].hsw.trans2); in hsw_prepare_dp_ddi_buffers()
155 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_prepare_hdmi_ddi_buffers()
159 enum port port = encoder->port; in hsw_prepare_hdmi_ddi_buffers()
162 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in hsw_prepare_hdmi_ddi_buffers()
163 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in hsw_prepare_hdmi_ddi_buffers()
168 intel_bios_hdmi_boost_level(encoder->devdata)) in hsw_prepare_hdmi_ddi_buffers()
173 trans->entries[level].hsw.trans1 | iboost_bit); in hsw_prepare_hdmi_ddi_buffers()
175 trans->entries[level].hsw.trans2); in hsw_prepare_hdmi_ddi_buffers()
186 drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n", in mtl_wait_ddi_buf_idle()
200 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", in intel_wait_ddi_buf_idle()
206 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_wait_ddi_buf_active()
207 enum port port = encoder->port; in intel_wait_ddi_buf_active()
240 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", in intel_wait_ddi_buf_active()
246 switch (pll->info->id) { in hsw_pll_to_ddi_pll_sel()
260 MISSING_CASE(pll->info->id); in hsw_pll_to_ddi_pll_sel()
268 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_pll_to_ddi_clk_sel()
269 int clock = crtc_state->port_clock; in icl_pll_to_ddi_clk_sel()
270 const enum intel_dpll_id id = pll->info->id; in icl_pll_to_ddi_clk_sel()
332 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_init_dp_buf_reg()
337 intel_dp->DP = dig_port->saved_port_bits | in intel_ddi_init_dp_buf_reg()
338 DDI_PORT_WIDTH(crtc_state->lane_count) | in intel_ddi_init_dp_buf_reg()
343 intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT; in intel_ddi_init_dp_buf_reg()
345 intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT; in intel_ddi_init_dp_buf_reg()
349 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock); in intel_ddi_init_dp_buf_reg()
351 intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP; in intel_ddi_init_dp_buf_reg()
380 if (pipe_config->has_pch_encoder) in ddi_dotclock_get()
383 pipe_config->hw.adjusted_mode.crtc_clock = in ddi_dotclock_get()
390 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_set_dp_msa()
391 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_ddi_set_dp_msa()
392 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_set_dp_msa()
398 drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)); in intel_ddi_set_dp_msa()
402 switch (crtc_state->pipe_bpp) { in intel_ddi_set_dp_msa()
416 MISSING_CASE(crtc_state->pipe_bpp); in intel_ddi_set_dp_msa()
421 drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range && in intel_ddi_set_dp_msa()
422 crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB); in intel_ddi_set_dp_msa()
424 if (crtc_state->limited_color_range) in intel_ddi_set_dp_msa()
432 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444) in intel_ddi_set_dp_msa()
460 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_config_transcoder_dp2()
461 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_config_transcoder_dp2()
480 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_transcoder_func_reg_val_get()
481 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_ddi_transcoder_func_reg_val_get()
482 enum pipe pipe = crtc->pipe; in intel_ddi_transcoder_func_reg_val_get()
483 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_transcoder_func_reg_val_get()
484 enum port port = encoder->port; in intel_ddi_transcoder_func_reg_val_get()
494 switch (crtc_state->pipe_bpp) { in intel_ddi_transcoder_func_reg_val_get()
496 MISSING_CASE(crtc_state->pipe_bpp); in intel_ddi_transcoder_func_reg_val_get()
512 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) in intel_ddi_transcoder_func_reg_val_get()
514 if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) in intel_ddi_transcoder_func_reg_val_get()
523 /* On Haswell, can only use the always-on power well for in intel_ddi_transcoder_func_reg_val_get()
527 if (crtc_state->pch_pfit.force_thru) in intel_ddi_transcoder_func_reg_val_get()
542 if (crtc_state->has_hdmi_sink) in intel_ddi_transcoder_func_reg_val_get()
547 if (crtc_state->hdmi_scrambling) in intel_ddi_transcoder_func_reg_val_get()
549 if (crtc_state->hdmi_high_tmds_clock_ratio) in intel_ddi_transcoder_func_reg_val_get()
552 temp |= TRANS_DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_transcoder_func_reg_val_get()
555 temp |= (crtc_state->fdi_lanes - 1) << 1; in intel_ddi_transcoder_func_reg_val_get()
561 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_transcoder_func_reg_val_get()
566 master = crtc_state->mst_master_transcoder; in intel_ddi_transcoder_func_reg_val_get()
567 drm_WARN_ON(&dev_priv->drm, in intel_ddi_transcoder_func_reg_val_get()
573 temp |= DDI_PORT_WIDTH(crtc_state->lane_count); in intel_ddi_transcoder_func_reg_val_get()
577 crtc_state->master_transcoder != INVALID_TRANSCODER) { in intel_ddi_transcoder_func_reg_val_get()
579 bdw_trans_port_sync_master_select(crtc_state->master_transcoder); in intel_ddi_transcoder_func_reg_val_get()
591 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_enable_transcoder_func()
592 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_ddi_enable_transcoder_func()
593 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_enable_transcoder_func()
596 enum transcoder master_transcoder = crtc_state->master_transcoder; in intel_ddi_enable_transcoder_func()
625 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_config_transcoder_func()
626 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_ddi_config_transcoder_func()
627 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_config_transcoder_func()
639 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_disable_transcoder_func()
640 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_ddi_disable_transcoder_func()
641 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_disable_transcoder_func()
652 drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); in intel_ddi_disable_transcoder_func()
674 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); in intel_ddi_disable_transcoder_func()
675 /* Quirk time at 100ms for reliable operation */ in intel_ddi_disable_transcoder_func()
684 struct drm_device *dev = intel_encoder->base.dev; in intel_ddi_toggle_hdcp_bits()
690 intel_encoder->power_domain); in intel_ddi_toggle_hdcp_bits()
692 return -ENXIO; in intel_ddi_toggle_hdcp_bits()
696 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); in intel_ddi_toggle_hdcp_bits()
702 struct drm_device *dev = intel_connector->base.dev; in intel_ddi_connector_get_hw_state()
705 int type = intel_connector->base.connector_type; in intel_ddi_connector_get_hw_state()
706 enum port port = encoder->port; in intel_ddi_connector_get_hw_state()
714 encoder->power_domain); in intel_ddi_connector_get_hw_state()
718 if (!encoder->get_hw_state(encoder, &pipe)) { in intel_ddi_connector_get_hw_state()
763 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); in intel_ddi_connector_get_hw_state()
771 struct drm_device *dev = encoder->base.dev; in intel_ddi_get_encoder_pipes()
773 enum port port = encoder->port; in intel_ddi_get_encoder_pipes()
783 encoder->power_domain); in intel_ddi_get_encoder_pipes()
850 drm_dbg_kms(&dev_priv->drm, in intel_ddi_get_encoder_pipes()
852 encoder->base.base.id, encoder->base.name); in intel_ddi_get_encoder_pipes()
855 drm_dbg_kms(&dev_priv->drm, in intel_ddi_get_encoder_pipes()
857 encoder->base.base.id, encoder->base.name, in intel_ddi_get_encoder_pipes()
859 *pipe_mask = BIT(ffs(*pipe_mask) - 1); in intel_ddi_get_encoder_pipes()
863 drm_dbg_kms(&dev_priv->drm, in intel_ddi_get_encoder_pipes()
864 … "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n", in intel_ddi_get_encoder_pipes()
865 encoder->base.base.id, encoder->base.name, in intel_ddi_get_encoder_pipes()
876 drm_err(&dev_priv->drm, in intel_ddi_get_encoder_pipes()
878 encoder->base.base.id, encoder->base.name, tmp); in intel_ddi_get_encoder_pipes()
881 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); in intel_ddi_get_encoder_pipes()
895 *pipe = ffs(pipe_mask) - 1; in intel_ddi_get_hw_state()
904 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_ddi_main_link_aux_domain()
919 if (intel_psr_needs_aux_io_power(&dig_port->base, crtc_state)) in intel_ddi_main_link_aux_domain()
920 return intel_display_power_aux_io_domain(i915, dig_port->aux_ch); in intel_ddi_main_link_aux_domain()
923 intel_encoder_is_tc(&dig_port->base))) in intel_ddi_main_link_aux_domain()
933 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in main_link_aux_power_domain_get()
937 drm_WARN_ON(&i915->drm, dig_port->aux_wakeref); in main_link_aux_power_domain_get()
942 dig_port->aux_wakeref = intel_display_power_get(i915, domain); in main_link_aux_power_domain_get()
949 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in main_link_aux_power_domain_put()
954 wf = fetch_and_zero(&dig_port->aux_wakeref); in main_link_aux_power_domain_put()
964 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_get_power_domains()
969 * happen since fake-MST encoders don't set their get_power_domains() in intel_ddi_get_power_domains()
972 if (drm_WARN_ON(&dev_priv->drm, in intel_ddi_get_power_domains()
979 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); in intel_ddi_get_power_domains()
980 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, in intel_ddi_get_power_domains()
981 dig_port->ddi_io_power_domain); in intel_ddi_get_power_domains()
990 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_enable_transcoder_clock()
991 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_ddi_enable_transcoder_clock()
992 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_enable_transcoder_clock()
1002 val = TGL_TRANS_CLK_SEL_PORT(encoder->port); in intel_ddi_enable_transcoder_clock()
1004 val = TRANS_CLK_SEL_PORT(encoder->port); in intel_ddi_enable_transcoder_clock()
1011 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_ddi_disable_transcoder_clock()
1012 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in intel_ddi_disable_transcoder_clock()
1045 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in skl_ddi_set_iboost()
1049 iboost = intel_bios_hdmi_boost_level(encoder->devdata); in skl_ddi_set_iboost()
1051 iboost = intel_bios_dp_boost_level(encoder->devdata); in skl_ddi_set_iboost()
1057 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in skl_ddi_set_iboost()
1058 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in skl_ddi_set_iboost()
1061 iboost = trans->entries[level].hsw.i_boost; in skl_ddi_set_iboost()
1066 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost); in skl_ddi_set_iboost()
1070 _skl_ddi_set_iboost(dev_priv, encoder->port, iboost); in skl_ddi_set_iboost()
1072 if (encoder->port == PORT_A && dig_port->max_lanes == 4) in skl_ddi_set_iboost()
1079 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in intel_ddi_dp_voltage_max()
1080 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_dp_voltage_max()
1083 encoder->get_buf_trans(encoder, crtc_state, &n_entries); in intel_ddi_dp_voltage_max()
1085 if (drm_WARN_ON(&dev_priv->drm, n_entries < 1)) in intel_ddi_dp_voltage_max()
1087 if (drm_WARN_ON(&dev_priv->drm, in intel_ddi_dp_voltage_max()
1091 return index_to_dp_signal_levels[n_entries - 1] & in intel_ddi_dp_voltage_max()
1096 * We assume that the full set of pre-emphasis values can be
1108 if (crtc_state->port_clock > 600000) in icl_combo_phy_loadgen_select()
1111 if (crtc_state->lane_count == 4) in icl_combo_phy_loadgen_select()
1120 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in icl_ddi_combo_vswing_program()
1126 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in icl_ddi_combo_vswing_program()
1127 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in icl_ddi_combo_vswing_program()
1134 intel_dp->hobl_active = is_hobl_buf_trans(trans); in icl_ddi_combo_vswing_program()
1136 intel_dp->hobl_active ? val : 0); in icl_ddi_combo_vswing_program()
1154 SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) | in icl_ddi_combo_vswing_program()
1155 SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) | in icl_ddi_combo_vswing_program()
1166 POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) | in icl_ddi_combo_vswing_program()
1167 POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) | in icl_ddi_combo_vswing_program()
1168 CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff)); in icl_ddi_combo_vswing_program()
1177 N_SCALAR(trans->entries[level].icl.dw7_n_scalar)); in icl_ddi_combo_vswing_program()
1184 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in icl_combo_phy_set_signal_levels()
1223 /* 5. Program swing and de-emphasis */ in icl_combo_phy_set_signal_levels()
1235 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in icl_mg_phy_set_signal_levels()
1243 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in icl_mg_phy_set_signal_levels()
1244 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in icl_mg_phy_set_signal_levels()
1262 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); in icl_mg_phy_set_signal_levels()
1268 CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12)); in icl_mg_phy_set_signal_levels()
1280 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | in icl_mg_phy_set_signal_levels()
1281 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | in icl_mg_phy_set_signal_levels()
1289 CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) | in icl_mg_phy_set_signal_levels()
1290 CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) | in icl_mg_phy_set_signal_levels()
1304 crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0); in icl_mg_phy_set_signal_levels()
1312 crtc_state->port_clock > 500000 ? in icl_mg_phy_set_signal_levels()
1319 crtc_state->port_clock > 500000 ? in icl_mg_phy_set_signal_levels()
1336 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in tgl_dkl_phy_set_signal_levels()
1344 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in tgl_dkl_phy_set_signal_levels()
1345 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in tgl_dkl_phy_set_signal_levels()
1359 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | in tgl_dkl_phy_set_signal_levels()
1360 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | in tgl_dkl_phy_set_signal_levels()
1361 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); in tgl_dkl_phy_set_signal_levels()
1369 DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) | in tgl_dkl_phy_set_signal_levels()
1370 DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) | in tgl_dkl_phy_set_signal_levels()
1371 DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing)); in tgl_dkl_phy_set_signal_levels()
1411 drm_WARN(display->drm, 1, in translate_signal_level()
1412 "Unsupported voltage swing/pre-emphasis level: 0x%x\n", in translate_signal_level()
1422 u8 train_set = intel_dp->train_set[lane]; in intel_ddi_dp_level()
1438 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_level()
1442 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in intel_ddi_level()
1443 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) in intel_ddi_level()
1452 if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries)) in intel_ddi_level()
1453 level = n_entries - 1; in intel_ddi_level()
1462 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_set_signal_levels()
1465 enum port port = encoder->port; in hsw_set_signal_levels()
1477 drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n", in hsw_set_signal_levels()
1480 intel_dp->DP &= ~DDI_BUF_EMP_MASK; in hsw_set_signal_levels()
1481 intel_dp->DP |= signal_levels; in hsw_set_signal_levels()
1483 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); in hsw_set_signal_levels()
1490 mutex_lock(&i915->display.dpll.lock); in _icl_ddi_enable_clock()
1500 mutex_unlock(&i915->display.dpll.lock); in _icl_ddi_enable_clock()
1506 mutex_lock(&i915->display.dpll.lock); in _icl_ddi_disable_clock()
1510 mutex_unlock(&i915->display.dpll.lock); in _icl_ddi_disable_clock()
1533 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in adls_ddi_enable_clock()
1534 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in adls_ddi_enable_clock()
1537 if (drm_WARN_ON(&i915->drm, !pll)) in adls_ddi_enable_clock()
1542 pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy), in adls_ddi_enable_clock()
1548 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in adls_ddi_disable_clock()
1557 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in adls_ddi_is_clock_enabled()
1566 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in adls_ddi_get_pll()
1577 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in rkl_ddi_enable_clock()
1578 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in rkl_ddi_enable_clock()
1581 if (drm_WARN_ON(&i915->drm, !pll)) in rkl_ddi_enable_clock()
1586 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), in rkl_ddi_enable_clock()
1592 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in rkl_ddi_disable_clock()
1601 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in rkl_ddi_is_clock_enabled()
1610 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in rkl_ddi_get_pll()
1621 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in dg1_ddi_enable_clock()
1622 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in dg1_ddi_enable_clock()
1625 if (drm_WARN_ON(&i915->drm, !pll)) in dg1_ddi_enable_clock()
1632 if (drm_WARN_ON(&i915->drm, in dg1_ddi_enable_clock()
1633 (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) || in dg1_ddi_enable_clock()
1634 (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C))) in dg1_ddi_enable_clock()
1639 DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), in dg1_ddi_enable_clock()
1645 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in dg1_ddi_disable_clock()
1654 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in dg1_ddi_is_clock_enabled()
1663 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in dg1_ddi_get_pll()
1687 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_combo_enable_clock()
1688 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_ddi_combo_enable_clock()
1691 if (drm_WARN_ON(&i915->drm, !pll)) in icl_ddi_combo_enable_clock()
1696 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy), in icl_ddi_combo_enable_clock()
1702 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_combo_disable_clock()
1711 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_combo_is_clock_enabled()
1720 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_combo_get_pll()
1731 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in jsl_ddi_tc_enable_clock()
1732 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in jsl_ddi_tc_enable_clock()
1733 enum port port = encoder->port; in jsl_ddi_tc_enable_clock()
1735 if (drm_WARN_ON(&i915->drm, !pll)) in jsl_ddi_tc_enable_clock()
1749 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in jsl_ddi_tc_disable_clock()
1750 enum port port = encoder->port; in jsl_ddi_tc_disable_clock()
1759 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in jsl_ddi_tc_is_clock_enabled()
1760 enum port port = encoder->port; in jsl_ddi_tc_is_clock_enabled()
1774 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_tc_enable_clock()
1775 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_ddi_tc_enable_clock()
1777 enum port port = encoder->port; in icl_ddi_tc_enable_clock()
1779 if (drm_WARN_ON(&i915->drm, !pll)) in icl_ddi_tc_enable_clock()
1785 mutex_lock(&i915->display.dpll.lock); in icl_ddi_tc_enable_clock()
1790 mutex_unlock(&i915->display.dpll.lock); in icl_ddi_tc_enable_clock()
1795 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_tc_disable_clock()
1797 enum port port = encoder->port; in icl_ddi_tc_disable_clock()
1799 mutex_lock(&i915->display.dpll.lock); in icl_ddi_tc_disable_clock()
1804 mutex_unlock(&i915->display.dpll.lock); in icl_ddi_tc_disable_clock()
1811 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_tc_is_clock_enabled()
1813 enum port port = encoder->port; in icl_ddi_tc_is_clock_enabled()
1828 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_tc_get_pll()
1830 enum port port = encoder->port; in icl_ddi_tc_get_pll()
1858 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in bxt_ddi_get_pll()
1861 switch (encoder->port) { in bxt_ddi_get_pll()
1872 MISSING_CASE(encoder->port); in bxt_ddi_get_pll()
1882 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in skl_ddi_enable_clock()
1883 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in skl_ddi_enable_clock()
1884 enum port port = encoder->port; in skl_ddi_enable_clock()
1886 if (drm_WARN_ON(&i915->drm, !pll)) in skl_ddi_enable_clock()
1889 mutex_lock(&i915->display.dpll.lock); in skl_ddi_enable_clock()
1894 DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) | in skl_ddi_enable_clock()
1897 mutex_unlock(&i915->display.dpll.lock); in skl_ddi_enable_clock()
1902 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in skl_ddi_disable_clock()
1903 enum port port = encoder->port; in skl_ddi_disable_clock()
1905 mutex_lock(&i915->display.dpll.lock); in skl_ddi_disable_clock()
1910 mutex_unlock(&i915->display.dpll.lock); in skl_ddi_disable_clock()
1915 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in skl_ddi_is_clock_enabled()
1916 enum port port = encoder->port; in skl_ddi_is_clock_enabled()
1927 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in skl_ddi_get_pll()
1928 enum port port = encoder->port; in skl_ddi_get_pll()
1950 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in hsw_ddi_enable_clock()
1951 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in hsw_ddi_enable_clock()
1952 enum port port = encoder->port; in hsw_ddi_enable_clock()
1954 if (drm_WARN_ON(&i915->drm, !pll)) in hsw_ddi_enable_clock()
1962 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in hsw_ddi_disable_clock()
1963 enum port port = encoder->port; in hsw_ddi_disable_clock()
1970 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in hsw_ddi_is_clock_enabled()
1971 enum port port = encoder->port; in hsw_ddi_is_clock_enabled()
1978 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in hsw_ddi_get_pll()
1979 enum port port = encoder->port; in hsw_ddi_get_pll()
2017 if (encoder->enable_clock) in intel_ddi_enable_clock()
2018 encoder->enable_clock(encoder, crtc_state); in intel_ddi_enable_clock()
2023 if (encoder->disable_clock) in intel_ddi_disable_clock()
2024 encoder->disable_clock(encoder); in intel_ddi_disable_clock()
2029 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_sanitize_encoder_pll_mapping()
2037 if (encoder->type == INTEL_OUTPUT_DP_MST) in intel_ddi_sanitize_encoder_pll_mapping()
2040 if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) { in intel_ddi_sanitize_encoder_pll_mapping()
2049 if (drm_WARN_ON(&i915->drm, is_mst)) in intel_ddi_sanitize_encoder_pll_mapping()
2053 port_mask = BIT(encoder->port); in intel_ddi_sanitize_encoder_pll_mapping()
2054 ddi_clk_needed = encoder->base.crtc; in intel_ddi_sanitize_encoder_pll_mapping()
2056 if (encoder->type == INTEL_OUTPUT_DSI) { in intel_ddi_sanitize_encoder_pll_mapping()
2064 for_each_intel_encoder(&i915->drm, other_encoder) { in intel_ddi_sanitize_encoder_pll_mapping()
2068 if (drm_WARN_ON(&i915->drm, in intel_ddi_sanitize_encoder_pll_mapping()
2069 port_mask & BIT(other_encoder->port))) in intel_ddi_sanitize_encoder_pll_mapping()
2079 if (ddi_clk_needed || !encoder->is_clock_enabled || in intel_ddi_sanitize_encoder_pll_mapping()
2080 !encoder->is_clock_enabled(encoder)) in intel_ddi_sanitize_encoder_pll_mapping()
2083 drm_dbg_kms(&i915->drm, in intel_ddi_sanitize_encoder_pll_mapping()
2085 encoder->base.base.id, encoder->base.name); in intel_ddi_sanitize_encoder_pll_mapping()
2087 encoder->disable_clock(encoder); in intel_ddi_sanitize_encoder_pll_mapping()
2094 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); in icl_program_mg_dp_mode()
2095 enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base); in icl_program_mg_dp_mode()
2102 if (!intel_encoder_is_tc(&dig_port->base) || in icl_program_mg_dp_mode()
2119 width = crtc_state->lane_count; in icl_program_mg_dp_mode()
2123 drm_WARN_ON(&dev_priv->drm, in icl_program_mg_dp_mode()
2181 return crtc_state->mst_master_transcoder; in tgl_dp_tp_transcoder()
2183 return crtc_state->cpu_transcoder; in tgl_dp_tp_transcoder()
2189 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in dp_tp_ctl_reg()
2195 return DP_TP_CTL(encoder->port); in dp_tp_ctl_reg()
2201 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in dp_tp_status_reg()
2207 return DP_TP_STATUS(encoder->port); in dp_tp_status_reg()
2216 if (!crtc_state->vrr.enable) in intel_dp_sink_set_msa_timing_par_ignore_state()
2219 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL, in intel_dp_sink_set_msa_timing_par_ignore_state()
2221 drm_dbg_kms(display->drm, in intel_dp_sink_set_msa_timing_par_ignore_state()
2232 if (!crtc_state->fec_enable) in intel_dp_sink_set_fec_ready()
2235 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, in intel_dp_sink_set_fec_ready()
2237 drm_dbg_kms(display->drm, "Failed to set FEC_READY to %s in the sink\n", in intel_dp_sink_set_fec_ready()
2241 drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_STATUS, in intel_dp_sink_set_fec_ready()
2243 drm_dbg_kms(display->drm, "Failed to clear FEC detected flags\n"); in intel_dp_sink_set_fec_ready()
2260 struct drm_i915_private *i915 = to_i915(aux->drm_dev); in wait_for_fec_detected()
2272 if (err == -ETIMEDOUT) in wait_for_fec_detected()
2273 drm_dbg_kms(&i915->drm, "Timeout waiting for FEC %s to get detected\n", in wait_for_fec_detected()
2276 drm_dbg_kms(&i915->drm, "FEC detected status read error: %d\n", status); in wait_for_fec_detected()
2283 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); in intel_ddi_wait_for_fec_status()
2287 if (!crtc_state->fec_enable) in intel_ddi_wait_for_fec_status()
2298 drm_err(&i915->drm, in intel_ddi_wait_for_fec_status()
2307 wait_for_fec_detected(&intel_dp->aux, enabled); in intel_ddi_wait_for_fec_status()
2313 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_enable_fec()
2315 if (!crtc_state->fec_enable) in intel_ddi_enable_fec()
2325 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_disable_fec()
2327 if (!crtc_state->fec_enable) in intel_ddi_disable_fec()
2338 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_power_up_lanes()
2344 dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; in intel_ddi_power_up_lanes()
2347 crtc_state->lane_count, in intel_ddi_power_up_lanes()
2369 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_ddi_mso_get_config()
2370 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_ddi_mso_get_config()
2371 enum pipe pipe = crtc->pipe; in intel_ddi_mso_get_config()
2379 pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE; in intel_ddi_mso_get_config()
2380 if (!pipe_config->splitter.enable) in intel_ddi_mso_get_config()
2383 if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) { in intel_ddi_mso_get_config()
2384 pipe_config->splitter.enable = false; in intel_ddi_mso_get_config()
2390 drm_WARN(&i915->drm, true, in intel_ddi_mso_get_config()
2394 pipe_config->splitter.link_count = 2; in intel_ddi_mso_get_config()
2397 pipe_config->splitter.link_count = 4; in intel_ddi_mso_get_config()
2401 pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1); in intel_ddi_mso_get_config()
2406 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_mso_configure()
2407 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_ddi_mso_configure()
2408 enum pipe pipe = crtc->pipe; in intel_ddi_mso_configure()
2414 if (crtc_state->splitter.enable) { in intel_ddi_mso_configure()
2416 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap); in intel_ddi_mso_configure()
2417 if (crtc_state->splitter.link_count == 2) in intel_ddi_mso_configure()
2448 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in mtl_ddi_enable_d2d()
2449 enum port port = encoder->port; in mtl_ddi_enable_d2d()
2465 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", in mtl_ddi_enable_d2d()
2473 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in mtl_port_buf_ctl_program()
2475 enum port port = encoder->port; in mtl_port_buf_ctl_program()
2480 val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count)); in mtl_port_buf_ctl_program()
2488 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL) in mtl_port_buf_ctl_program()
2496 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in mtl_port_buf_ctl_io_selection()
2502 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port), in mtl_port_buf_ctl_io_selection()
2515 crtc_state->port_clock, in mtl_ddi_pre_enable_dp()
2516 crtc_state->lane_count); in mtl_ddi_pre_enable_dp()
2549 * 6.b If DP v2.0/128b mode - Configure TRANS_DP2_CTL register settings. in mtl_ddi_pre_enable_dp()
2570 to_intel_connector(conn_state->connector), in mtl_ddi_pre_enable_dp()
2589 * stream or multi-stream master transcoder" can just be performed in mtl_ddi_pre_enable_dp()
2598 * 6.m If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle in mtl_ddi_pre_enable_dp()
2621 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in tgl_ddi_pre_enable_dp()
2626 crtc_state->port_clock, in tgl_ddi_pre_enable_dp()
2627 crtc_state->lane_count); in tgl_ddi_pre_enable_dp()
2646 * 3. For non-TBT Type-C ports, set FIA lane count in tgl_ddi_pre_enable_dp()
2650 * hsw_crtc_enable()->intel_encoders_pre_pll_enable(). in tgl_ddi_pre_enable_dp()
2657 * hsw_crtc_enable()->intel_enable_shared_dpll(). We need only in tgl_ddi_pre_enable_dp()
2664 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); in tgl_ddi_pre_enable_dp()
2665 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, in tgl_ddi_pre_enable_dp()
2666 dig_port->ddi_io_power_domain); in tgl_ddi_pre_enable_dp()
2678 * stream or multi-stream master transcoder" can just be performed in tgl_ddi_pre_enable_dp()
2706 encoder->set_signal_levels(encoder, crtc_state); in tgl_ddi_pre_enable_dp()
2725 to_intel_connector(conn_state->connector), in tgl_ddi_pre_enable_dp()
2740 * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle in tgl_ddi_pre_enable_dp()
2763 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_ddi_pre_enable_dp()
2764 enum port port = encoder->port; in hsw_ddi_pre_enable_dp()
2769 drm_WARN_ON(&dev_priv->drm, in hsw_ddi_pre_enable_dp()
2772 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A); in hsw_ddi_pre_enable_dp()
2775 crtc_state->port_clock, in hsw_ddi_pre_enable_dp()
2776 crtc_state->lane_count); in hsw_ddi_pre_enable_dp()
2789 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); in hsw_ddi_pre_enable_dp()
2790 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, in hsw_ddi_pre_enable_dp()
2791 dig_port->ddi_io_power_domain); in hsw_ddi_pre_enable_dp()
2799 encoder->set_signal_levels(encoder, crtc_state); in hsw_ddi_pre_enable_dp()
2808 to_intel_connector(conn_state->connector), in hsw_ddi_pre_enable_dp()
2829 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_pre_enable_dp()
2836 if (crtc_state->has_panel_replay) in intel_ddi_pre_enable_dp()
2859 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; in intel_ddi_pre_enable_hdmi()
2860 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_pre_enable_hdmi()
2865 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref); in intel_ddi_pre_enable_hdmi()
2866 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv, in intel_ddi_pre_enable_hdmi()
2867 dig_port->ddi_io_power_domain); in intel_ddi_pre_enable_hdmi()
2873 dig_port->set_infoframes(encoder, in intel_ddi_pre_enable_hdmi()
2874 crtc_state->has_infoframe, in intel_ddi_pre_enable_hdmi()
2883 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_pre_enable()
2884 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_ddi_pre_enable()
2885 enum pipe pipe = crtc->pipe; in intel_ddi_pre_enable()
2889 * - conn_state will be NULL in intel_ddi_pre_enable()
2890 * - encoder will be the main encoder (ie. mst->primary) in intel_ddi_pre_enable()
2891 * - the main connector associated with this port in intel_ddi_pre_enable()
2893 * - crtc_state will be the state of the first stream to in intel_ddi_pre_enable()
2900 drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder); in intel_ddi_pre_enable()
2915 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) in intel_ddi_pre_enable()
2916 dig_port->set_infoframes(encoder, in intel_ddi_pre_enable()
2917 crtc_state->has_infoframe, in intel_ddi_pre_enable()
2925 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in mtl_ddi_disable_d2d_link()
2926 enum port port = encoder->port; in mtl_ddi_disable_d2d_link()
2942 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", in mtl_ddi_disable_d2d_link()
2949 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in mtl_disable_ddi_buf()
2950 enum port port = encoder->port; in mtl_disable_ddi_buf()
2976 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in disable_ddi_buf()
2977 enum port port = encoder->port; in disable_ddi_buf()
3001 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_disable_ddi_buf()
3020 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_post_disable_dp()
3022 struct intel_dp *intel_dp = &dig_port->dp; in intel_ddi_post_disable_dp()
3039 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; in intel_ddi_post_disable_dp()
3056 * From TGL spec: "If single stream or multi-stream master transcoder: in intel_ddi_post_disable_dp()
3066 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); in intel_ddi_post_disable_dp()
3070 dig_port->ddi_io_power_domain, in intel_ddi_post_disable_dp()
3075 /* De-select Thunderbolt */ in intel_ddi_post_disable_dp()
3077 intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, encoder->port), in intel_ddi_post_disable_dp()
3086 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_post_disable_hdmi()
3088 struct intel_hdmi *intel_hdmi = &dig_port->hdmi; in intel_ddi_post_disable_hdmi()
3091 dig_port->set_infoframes(encoder, false, in intel_ddi_post_disable_hdmi()
3102 wakeref = fetch_and_zero(&dig_port->ddi_io_wakeref); in intel_ddi_post_disable_hdmi()
3105 dig_port->ddi_io_power_domain, in intel_ddi_post_disable_hdmi()
3118 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_post_disable_hdmi_or_sst()
3121 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, in intel_ddi_post_disable_hdmi_or_sst()
3133 for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc, in intel_ddi_post_disable_hdmi_or_sst()
3158 * - old_conn_state will be NULL in intel_ddi_post_disable()
3159 * - encoder will be the main encoder (ie. mst->primary) in intel_ddi_post_disable()
3160 * - the main connector associated with this port in intel_ddi_post_disable()
3162 * - old_crtc_state will be the state of the last stream to in intel_ddi_post_disable()
3198 if (!crtc_state->sync_mode_slaves_mask) in trans_port_sync_stop_link_train()
3201 for_each_new_connector_in_state(&state->base, conn, conn_state, i) { in trans_port_sync_stop_link_train()
3203 to_intel_encoder(conn_state->best_encoder); in trans_port_sync_stop_link_train()
3204 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc); in trans_port_sync_stop_link_train()
3213 if (slave_crtc_state->master_transcoder != in trans_port_sync_stop_link_train()
3214 crtc_state->cpu_transcoder) in trans_port_sync_stop_link_train()
3232 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_enable_ddi_dp()
3235 enum port port = encoder->port; in intel_enable_ddi_dp()
3243 if (!dig_port->lspcon.active || intel_dp_has_hdmi_sink(&dig_port->dp)) in intel_enable_ddi_dp()
3270 drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9); in gen9_chicken_trans_reg_by_port()
3272 if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E)) in gen9_chicken_trans_reg_by_port()
3283 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_enable_ddi_hdmi()
3285 struct drm_connector *connector = conn_state->connector; in intel_enable_ddi_hdmi()
3286 enum port port = encoder->port; in intel_enable_ddi_hdmi()
3290 crtc_state->hdmi_high_tmds_clock_ratio, in intel_enable_ddi_hdmi()
3291 crtc_state->hdmi_scrambling)) in intel_enable_ddi_hdmi()
3292 drm_dbg_kms(&dev_priv->drm, in intel_enable_ddi_hdmi()
3294 connector->base.id, connector->name); in intel_enable_ddi_hdmi()
3303 encoder->set_signal_levels(encoder, crtc_state); in intel_enable_ddi_hdmi()
3353 buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE; in intel_enable_ddi_hdmi()
3355 u8 lane_count = mtl_get_port_width(crtc_state->lane_count); in intel_enable_ddi_hdmi()
3360 if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL) in intel_enable_ddi_hdmi()
3371 drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port)); in intel_enable_ddi_hdmi()
3385 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_enable_ddi()
3397 for_each_intel_crtc_in_pipe_mask_reverse(&i915->drm, pipe_crtc, in intel_enable_ddi()
3421 to_intel_connector(old_conn_state->connector); in intel_disable_ddi_dp()
3423 intel_dp->link_trained = false; in intel_disable_ddi_dp()
3440 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_disable_ddi_hdmi()
3441 struct drm_connector *connector = old_conn_state->connector; in intel_disable_ddi_hdmi()
3445 drm_dbg_kms(&i915->drm, in intel_disable_ddi_hdmi()
3447 connector->base.id, connector->name); in intel_disable_ddi_hdmi()
3457 intel_hdcp_disable(to_intel_connector(old_conn_state->connector)); in intel_disable_ddi()
3498 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_update_active_dpll()
3507 for_each_intel_crtc_in_pipe_mask(&i915->drm, pipe_crtc, in intel_ddi_update_active_dpll()
3518 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_pre_pll_enable()
3523 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_ddi_pre_pll_enable()
3525 intel_tc_port_get_link(dig_port, crtc_state->lane_count); in intel_ddi_pre_pll_enable()
3534 * Type-C ports. Skip this step for TBT. in intel_ddi_pre_pll_enable()
3536 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count); in intel_ddi_pre_pll_enable()
3539 crtc_state->lane_lat_optim_mask); in intel_ddi_pre_pll_enable()
3544 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in adlp_tbt_to_dp_alt_switch_wa()
3556 struct intel_encoder *encoder = &dig_port->base; in mtl_ddi_prepare_link_retrain()
3557 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in mtl_ddi_prepare_link_retrain()
3558 enum port port = encoder->port; in mtl_ddi_prepare_link_retrain()
3575 if (crtc_state->enhanced_framing) in mtl_ddi_prepare_link_retrain()
3585 encoder->set_signal_levels(encoder, crtc_state); in mtl_ddi_prepare_link_retrain()
3591 intel_dp->DP |= DDI_BUF_CTL_ENABLE; in mtl_ddi_prepare_link_retrain()
3593 intel_dp->DP |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE; in mtl_ddi_prepare_link_retrain()
3595 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); in mtl_ddi_prepare_link_retrain()
3606 struct intel_encoder *encoder = &dig_port->base; in intel_ddi_prepare_link_retrain()
3607 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_prepare_link_retrain()
3608 enum port port = encoder->port; in intel_ddi_prepare_link_retrain()
3635 if (crtc_state->enhanced_framing) in intel_ddi_prepare_link_retrain()
3645 intel_dp->DP |= DDI_BUF_CTL_ENABLE; in intel_ddi_prepare_link_retrain()
3646 intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP); in intel_ddi_prepare_link_retrain()
3656 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in intel_ddi_set_link_train()
3657 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_set_link_train()
3687 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; in intel_ddi_set_idle_link_train()
3688 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_set_idle_link_train()
3689 enum port port = encoder->port; in intel_ddi_set_idle_link_train()
3697 * issue where we enable the pipe while not in idle link-training mode. in intel_ddi_set_idle_link_train()
3707 drm_err(&dev_priv->drm, in intel_ddi_set_idle_link_train()
3726 if (crtc_state->port_clock > 594000) in tgl_ddi_min_voltage_level()
3734 if (crtc_state->port_clock > 594000) in jsl_ddi_min_voltage_level()
3742 if (crtc_state->port_clock > 594000) in icl_ddi_min_voltage_level()
3750 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in intel_ddi_compute_min_voltage_level()
3753 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); in intel_ddi_compute_min_voltage_level()
3755 crtc_state->min_voltage_level = tgl_ddi_min_voltage_level(crtc_state); in intel_ddi_compute_min_voltage_level()
3757 crtc_state->min_voltage_level = jsl_ddi_min_voltage_level(crtc_state); in intel_ddi_compute_min_voltage_level()
3759 crtc_state->min_voltage_level = icl_ddi_min_voltage_level(crtc_state); in intel_ddi_compute_min_voltage_level()
3788 return master_select - 1; in bdw_transcoder_master_readout()
3793 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); in bdw_get_trans_port_sync_config()
3798 crtc_state->master_transcoder = in bdw_get_trans_port_sync_config()
3799 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder); in bdw_get_trans_port_sync_config()
3813 crtc_state->cpu_transcoder) in bdw_get_trans_port_sync_config()
3814 crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder); in bdw_get_trans_port_sync_config()
3819 drm_WARN_ON(&dev_priv->drm, in bdw_get_trans_port_sync_config()
3820 crtc_state->master_transcoder != INVALID_TRANSCODER && in bdw_get_trans_port_sync_config()
3821 crtc_state->sync_mode_slaves_mask); in bdw_get_trans_port_sync_config()
3827 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_read_func_ctl()
3828 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_ddi_read_func_ctl()
3829 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; in intel_ddi_read_func_ctl()
3844 pipe_config->hw.adjusted_mode.flags |= flags; in intel_ddi_read_func_ctl()
3848 pipe_config->pipe_bpp = 18; in intel_ddi_read_func_ctl()
3851 pipe_config->pipe_bpp = 24; in intel_ddi_read_func_ctl()
3854 pipe_config->pipe_bpp = 30; in intel_ddi_read_func_ctl()
3857 pipe_config->pipe_bpp = 36; in intel_ddi_read_func_ctl()
3865 pipe_config->has_hdmi_sink = true; in intel_ddi_read_func_ctl()
3867 pipe_config->infoframes.enable |= in intel_ddi_read_func_ctl()
3870 if (pipe_config->infoframes.enable) in intel_ddi_read_func_ctl()
3871 pipe_config->has_infoframe = true; in intel_ddi_read_func_ctl()
3874 pipe_config->hdmi_scrambling = true; in intel_ddi_read_func_ctl()
3876 pipe_config->hdmi_high_tmds_clock_ratio = true; in intel_ddi_read_func_ctl()
3879 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); in intel_ddi_read_func_ctl()
3881 pipe_config->lane_count = in intel_ddi_read_func_ctl()
3884 pipe_config->lane_count = 4; in intel_ddi_read_func_ctl()
3887 if (encoder->type == INTEL_OUTPUT_EDP) in intel_ddi_read_func_ctl()
3888 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); in intel_ddi_read_func_ctl()
3890 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); in intel_ddi_read_func_ctl()
3891 pipe_config->lane_count = in intel_ddi_read_func_ctl()
3895 &pipe_config->dp_m_n); in intel_ddi_read_func_ctl()
3897 &pipe_config->dp_m2_n2); in intel_ddi_read_func_ctl()
3899 pipe_config->enhanced_framing = in intel_ddi_read_func_ctl()
3904 pipe_config->fec_enable = in intel_ddi_read_func_ctl()
3908 if (dig_port->lspcon.active && intel_dp_has_hdmi_sink(&dig_port->dp)) in intel_ddi_read_func_ctl()
3909 pipe_config->infoframes.enable |= in intel_ddi_read_func_ctl()
3912 pipe_config->infoframes.enable |= in intel_ddi_read_func_ctl()
3918 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); in intel_ddi_read_func_ctl()
3919 pipe_config->enhanced_framing = in intel_ddi_read_func_ctl()
3926 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST); in intel_ddi_read_func_ctl()
3927 pipe_config->lane_count = in intel_ddi_read_func_ctl()
3931 pipe_config->mst_master_transcoder = in intel_ddi_read_func_ctl()
3935 &pipe_config->dp_m_n); in intel_ddi_read_func_ctl()
3938 pipe_config->fec_enable = in intel_ddi_read_func_ctl()
3942 pipe_config->infoframes.enable |= in intel_ddi_read_func_ctl()
3953 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_get_config()
3954 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; in intel_ddi_get_config()
3957 if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) in intel_ddi_get_config()
3964 pipe_config->has_audio = in intel_ddi_get_config()
3967 if (encoder->type == INTEL_OUTPUT_EDP) in intel_ddi_get_config()
3968 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); in intel_ddi_get_config()
3973 pipe_config->lane_lat_optim_mask = in intel_ddi_get_config()
3982 &pipe_config->infoframes.avi); in intel_ddi_get_config()
3985 &pipe_config->infoframes.spd); in intel_ddi_get_config()
3988 &pipe_config->infoframes.hdmi); in intel_ddi_get_config()
3991 &pipe_config->infoframes.drm); in intel_ddi_get_config()
4009 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_get_clock()
4011 struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; in intel_ddi_get_clock()
4014 if (drm_WARN_ON(&i915->drm, !pll)) in intel_ddi_get_clock()
4017 port_dpll->pll = pll; in intel_ddi_get_clock()
4018 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); in intel_ddi_get_clock()
4019 drm_WARN_ON(&i915->drm, !pll_active); in intel_ddi_get_clock()
4023 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, in intel_ddi_get_clock()
4024 &crtc_state->dpll_hw_state); in intel_ddi_get_clock()
4030 intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll); in mtl_ddi_get_config()
4032 if (crtc_state->dpll_hw_state.cx0pll.tbt_mode) in mtl_ddi_get_config()
4033 crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); in mtl_ddi_get_config()
4035 crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll); in mtl_ddi_get_config()
4043 intel_mpllb_readout_hw_state(encoder, &crtc_state->dpll_hw_state.mpllb); in dg2_ddi_get_config()
4044 crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->dpll_hw_state.mpllb); in dg2_ddi_get_config()
4079 return pll->info->id == DPLL_ID_ICL_TBTPLL; in icl_ddi_tc_pll_is_tbt()
4086 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_tc_port_pll_type()
4087 const struct intel_shared_dpll *pll = crtc_state->shared_dpll; in icl_ddi_tc_port_pll_type()
4089 if (drm_WARN_ON(&i915->drm, !pll)) in icl_ddi_tc_port_pll_type()
4102 if (!encoder->port_pll_type) in intel_ddi_port_pll_type()
4105 return encoder->port_pll_type(encoder, crtc_state); in intel_ddi_port_pll_type()
4112 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in icl_ddi_tc_get_clock()
4117 if (drm_WARN_ON(&i915->drm, !pll)) in icl_ddi_tc_get_clock()
4125 port_dpll = &crtc_state->icl_port_dplls[port_dpll_id]; in icl_ddi_tc_get_clock()
4127 port_dpll->pll = pll; in icl_ddi_tc_get_clock()
4128 pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state); in icl_ddi_tc_get_clock()
4129 drm_WARN_ON(&i915->drm, !pll_active); in icl_ddi_tc_get_clock()
4133 if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll)) in icl_ddi_tc_get_clock()
4134 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port); in icl_ddi_tc_get_clock()
4136 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, in icl_ddi_tc_get_clock()
4137 &crtc_state->dpll_hw_state); in icl_ddi_tc_get_clock()
4183 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_initial_fastset_check()
4187 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute TC port DPLLs\n", in intel_ddi_initial_fastset_check()
4188 encoder->base.base.id, encoder->base.name); in intel_ddi_initial_fastset_check()
4189 crtc_state->uapi.mode_changed = true; in intel_ddi_initial_fastset_check()
4205 switch (conn_state->connector->connector_type) { in intel_ddi_compute_output_type()
4213 MISSING_CASE(conn_state->connector->connector_type); in intel_ddi_compute_output_type()
4222 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_ddi_compute_config()
4223 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_ddi_compute_config()
4224 enum port port = encoder->port; in intel_ddi_compute_config()
4228 pipe_config->cpu_transcoder = TRANSCODER_EDP; in intel_ddi_compute_config()
4231 pipe_config->has_hdmi_sink = in intel_ddi_compute_config()
4242 if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A && in intel_ddi_compute_config()
4243 pipe_config->cpu_transcoder == TRANSCODER_EDP) in intel_ddi_compute_config()
4244 pipe_config->pch_pfit.force_thru = in intel_ddi_compute_config()
4245 pipe_config->pch_pfit.enabled || in intel_ddi_compute_config()
4246 pipe_config->crc_enabled; in intel_ddi_compute_config()
4249 pipe_config->lane_lat_optim_mask = in intel_ddi_compute_config()
4250 bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); in intel_ddi_compute_config()
4264 mode1->clock == mode2->clock; /* we want an exact match */ in mode_equal()
4270 return m_n_1->tu == m_n_2->tu && in m_n_equal()
4271 m_n_1->data_m == m_n_2->data_m && in m_n_equal()
4272 m_n_1->data_n == m_n_2->data_n && in m_n_equal()
4273 m_n_1->link_m == m_n_2->link_m && in m_n_equal()
4274 m_n_1->link_n == m_n_2->link_n; in m_n_equal()
4284 return crtc_state1->hw.active && crtc_state2->hw.active && in crtcs_port_sync_compatible()
4285 !crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes && in crtcs_port_sync_compatible()
4286 crtc_state1->output_types == crtc_state2->output_types && in crtcs_port_sync_compatible()
4287 crtc_state1->output_format == crtc_state2->output_format && in crtcs_port_sync_compatible()
4288 crtc_state1->lane_count == crtc_state2->lane_count && in crtcs_port_sync_compatible()
4289 crtc_state1->port_clock == crtc_state2->port_clock && in crtcs_port_sync_compatible()
4290 mode_equal(&crtc_state1->hw.adjusted_mode, in crtcs_port_sync_compatible()
4291 &crtc_state2->hw.adjusted_mode) && in crtcs_port_sync_compatible()
4292 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n); in crtcs_port_sync_compatible()
4301 struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev); in intel_ddi_port_sync_transcoders()
4303 to_intel_atomic_state(ref_crtc_state->uapi.state); in intel_ddi_port_sync_transcoders()
4317 for_each_new_connector_in_state(&state->base, connector, conn_state, i) { in intel_ddi_port_sync_transcoders()
4318 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc); in intel_ddi_port_sync_transcoders()
4324 if (!connector->has_tile || in intel_ddi_port_sync_transcoders()
4325 connector->tile_group->id != in intel_ddi_port_sync_transcoders()
4333 transcoders |= BIT(crtc_state->cpu_transcoder); in intel_ddi_port_sync_transcoders()
4343 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_compute_config_late()
4344 struct drm_connector *connector = conn_state->connector; in intel_ddi_compute_config_late()
4347 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n", in intel_ddi_compute_config_late()
4348 encoder->base.base.id, encoder->base.name, in intel_ddi_compute_config_late()
4349 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); in intel_ddi_compute_config_late()
4351 if (connector->has_tile) in intel_ddi_compute_config_late()
4353 connector->tile_group->id); in intel_ddi_compute_config_late()
4360 crtc_state->master_transcoder = TRANSCODER_EDP; in intel_ddi_compute_config_late()
4362 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1; in intel_ddi_compute_config_late()
4364 if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) { in intel_ddi_compute_config_late()
4365 crtc_state->master_transcoder = INVALID_TRANSCODER; in intel_ddi_compute_config_late()
4366 crtc_state->sync_mode_slaves_mask = in intel_ddi_compute_config_late()
4367 port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); in intel_ddi_compute_config_late()
4375 struct drm_i915_private *i915 = to_i915(encoder->dev); in intel_ddi_encoder_destroy()
4379 if (intel_encoder_is_tc(&dig_port->base)) in intel_ddi_encoder_destroy()
4384 kfree(dig_port->hdcp_port_data.streams); in intel_ddi_encoder_destroy()
4393 intel_dp->reset_link_params = true; in intel_ddi_encoder_reset()
4397 if (intel_encoder_is_tc(&dig_port->base)) in intel_ddi_encoder_reset()
4419 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); in intel_ddi_init_dp_connector()
4421 enum port port = dig_port->base.port; in intel_ddi_init_dp_connector()
4427 dig_port->dp.output_reg = DDI_BUF_CTL(port); in intel_ddi_init_dp_connector()
4429 dig_port->dp.prepare_link_retrain = mtl_ddi_prepare_link_retrain; in intel_ddi_init_dp_connector()
4431 dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain; in intel_ddi_init_dp_connector()
4432 dig_port->dp.set_link_train = intel_ddi_set_link_train; in intel_ddi_init_dp_connector()
4433 dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train; in intel_ddi_init_dp_connector()
4435 dig_port->dp.voltage_max = intel_ddi_dp_voltage_max; in intel_ddi_init_dp_connector()
4436 dig_port->dp.preemph_max = intel_ddi_dp_preemph_max; in intel_ddi_init_dp_connector()
4443 if (dig_port->base.type == INTEL_OUTPUT_EDP) { in intel_ddi_init_dp_connector()
4444 struct drm_device *dev = dig_port->base.base.dev; in intel_ddi_init_dp_connector()
4447 privacy_screen = drm_privacy_screen_get(dev->dev, NULL); in intel_ddi_init_dp_connector()
4449 drm_connector_attach_privacy_screen_provider(&connector->base, in intel_ddi_init_dp_connector()
4451 } else if (PTR_ERR(privacy_screen) != -ENODEV) { in intel_ddi_init_dp_connector()
4452 drm_warn(dev, "Error getting privacy-screen\n"); in intel_ddi_init_dp_connector()
4462 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_hdmi_reset_link()
4464 struct intel_connector *connector = hdmi->attached_connector; in intel_hdmi_reset_link()
4465 struct i2c_adapter *ddc = connector->base.ddc; in intel_hdmi_reset_link()
4472 if (connector->base.status != connector_status_connected) in intel_hdmi_reset_link()
4475 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, in intel_hdmi_reset_link()
4480 conn_state = connector->base.state; in intel_hdmi_reset_link()
4482 crtc = to_intel_crtc(conn_state->crtc); in intel_hdmi_reset_link()
4486 ret = drm_modeset_lock(&crtc->base.mutex, ctx); in intel_hdmi_reset_link()
4490 crtc_state = to_intel_crtc_state(crtc->base.state); in intel_hdmi_reset_link()
4492 drm_WARN_ON(&dev_priv->drm, in intel_hdmi_reset_link()
4495 if (!crtc_state->hw.active) in intel_hdmi_reset_link()
4498 if (!crtc_state->hdmi_high_tmds_clock_ratio && in intel_hdmi_reset_link()
4499 !crtc_state->hdmi_scrambling) in intel_hdmi_reset_link()
4502 if (conn_state->commit && in intel_hdmi_reset_link()
4503 !try_wait_for_completion(&conn_state->commit->hw_done)) in intel_hdmi_reset_link()
4508 drm_err(&dev_priv->drm, "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n", in intel_hdmi_reset_link()
4509 connector->base.base.id, connector->base.name, ret); in intel_hdmi_reset_link()
4514 crtc_state->hdmi_high_tmds_clock_ratio && in intel_hdmi_reset_link()
4516 crtc_state->hdmi_scrambling) in intel_hdmi_reset_link()
4528 return intel_modeset_commit_pipes(dev_priv, BIT(crtc->pipe), ctx); in intel_hdmi_reset_link()
4533 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_ddi_link_check()
4537 drm_WARN_ON(&i915->drm, !dig_port->dp.attached_connector); in intel_ddi_link_check()
4547 struct intel_dp *intel_dp = &dig_port->dp; in intel_ddi_hotplug()
4553 if (intel_dp->compliance.test_active && in intel_ddi_hotplug()
4554 intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { in intel_ddi_hotplug()
4563 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { in intel_ddi_hotplug()
4566 drm_WARN_ON(encoder->base.dev, ret); in intel_ddi_hotplug()
4573 * Unpowered type-c dongles can take some time to boot and be in intel_ddi_hotplug()
4581 * since the HPD interrupt may be raised before the DDC lines get in intel_ddi_hotplug()
4582 * disconnected (due to how the required length of DDC vs. HPD in intel_ddi_hotplug()
4588 * Type-c connectors which get their HPD signal deasserted then in intel_ddi_hotplug()
4590 * connector, introduce a delay until the AUX channel communication in intel_ddi_hotplug()
4591 * becomes functional. Retry the detection for 5 seconds on type-c in intel_ddi_hotplug()
4592 * connectors to account for this delay. in intel_ddi_hotplug()
4595 connector->hotplug_retries < (is_tc ? 5 : 1) && in intel_ddi_hotplug()
4596 !dig_port->dp.is_mst) in intel_ddi_hotplug()
4604 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in lpt_digital_port_connected()
4605 u32 bit = dev_priv->display.hotplug.pch_hpd[encoder->hpd_pin]; in lpt_digital_port_connected()
4612 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_digital_port_connected()
4613 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; in hsw_digital_port_connected()
4620 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in bdw_digital_port_connected()
4621 u32 bit = dev_priv->display.hotplug.hpd[encoder->hpd_pin]; in bdw_digital_port_connected()
4630 enum port port = dig_port->base.port; in intel_ddi_init_hdmi_connector()
4636 dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); in intel_ddi_init_hdmi_connector()
4644 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); in intel_ddi_a_force_4_lanes()
4646 if (dig_port->base.port != PORT_A) in intel_ddi_a_force_4_lanes()
4649 if (dig_port->saved_port_bits & DDI_A_4_LANES) in intel_ddi_a_force_4_lanes()
4664 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); in intel_ddi_max_lanes()
4665 enum port port = dig_port->base.port; in intel_ddi_max_lanes()
4685 drm_dbg_kms(&dev_priv->drm, in intel_ddi_max_lanes()
4687 dig_port->saved_port_bits |= DDI_A_4_LANES; in intel_ddi_max_lanes()
4698 return HPD_PORT_D + port - PORT_D_XELPD; in xelpd_hpd_pin()
4700 return HPD_PORT_TC1 + port - PORT_TC1; in xelpd_hpd_pin()
4702 return HPD_PORT_A + port - PORT_A; in xelpd_hpd_pin()
4709 return HPD_PORT_C + port - PORT_TC1; in dg1_hpd_pin()
4711 return HPD_PORT_A + port - PORT_A; in dg1_hpd_pin()
4718 return HPD_PORT_TC1 + port - PORT_TC1; in tgl_hpd_pin()
4720 return HPD_PORT_A + port - PORT_A; in tgl_hpd_pin()
4730 return HPD_PORT_C + port - PORT_TC1; in rkl_hpd_pin()
4732 return HPD_PORT_A + port - PORT_A; in rkl_hpd_pin()
4739 return HPD_PORT_TC1 + port - PORT_C; in icl_hpd_pin()
4741 return HPD_PORT_A + port - PORT_A; in icl_hpd_pin()
4753 return HPD_PORT_A + port - PORT_A; in ehl_hpd_pin()
4761 return HPD_PORT_A + port - PORT_A; in skl_hpd_pin()
4806 #define port_tc_name(port) ((port) - PORT_TC1 + '1')
4807 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1')
4825 return true; /* no strap for DDI-E */ in port_strap_detected()
4839 return !drm_WARN(&i915->drm, !IS_ALDERLAKE_P(i915) && in assert_has_icl_dsi()
4848 for_each_intel_encoder(&i915->drm, encoder) { in port_in_use()
4850 if (encoder->port == port) in port_in_use()
4860 struct drm_i915_private *dev_priv = to_i915(display->drm); in intel_ddi_init()
4872 drm_dbg_kms(&dev_priv->drm, in intel_ddi_init()
4881 drm_dbg_kms(&dev_priv->drm, in intel_ddi_init()
4904 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", in intel_ddi_init()
4921 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n", in intel_ddi_init()
4926 drm_dbg_kms(&dev_priv->drm, in intel_ddi_init()
4933 dev_priv->display.snps.phy_failed_calibration & BIT(phy)) { in intel_ddi_init()
4934 drm_dbg_kms(&dev_priv->drm, in intel_ddi_init()
4943 dig_port->aux_ch = AUX_CH_NONE; in intel_ddi_init()
4945 encoder = &dig_port->base; in intel_ddi_init()
4946 encoder->devdata = devdata; in intel_ddi_init()
4949 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, in intel_ddi_init()
4952 port_name(port - PORT_D_XELPD + PORT_D), in intel_ddi_init()
4957 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, in intel_ddi_init()
4967 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, in intel_ddi_init()
4975 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs, in intel_ddi_init()
4982 mutex_init(&dig_port->hdcp_mutex); in intel_ddi_init()
4983 dig_port->num_hdcp_streams = 0; in intel_ddi_init()
4985 encoder->hotplug = intel_ddi_hotplug; in intel_ddi_init()
4986 encoder->compute_output_type = intel_ddi_compute_output_type; in intel_ddi_init()
4987 encoder->compute_config = intel_ddi_compute_config; in intel_ddi_init()
4988 encoder->compute_config_late = intel_ddi_compute_config_late; in intel_ddi_init()
4989 encoder->enable = intel_enable_ddi; in intel_ddi_init()
4990 encoder->pre_pll_enable = intel_ddi_pre_pll_enable; in intel_ddi_init()
4991 encoder->pre_enable = intel_ddi_pre_enable; in intel_ddi_init()
4992 encoder->disable = intel_disable_ddi; in intel_ddi_init()
4993 encoder->post_pll_disable = intel_ddi_post_pll_disable; in intel_ddi_init()
4994 encoder->post_disable = intel_ddi_post_disable; in intel_ddi_init()
4995 encoder->update_pipe = intel_ddi_update_pipe; in intel_ddi_init()
4996 encoder->audio_enable = intel_audio_codec_enable; in intel_ddi_init()
4997 encoder->audio_disable = intel_audio_codec_disable; in intel_ddi_init()
4998 encoder->get_hw_state = intel_ddi_get_hw_state; in intel_ddi_init()
4999 encoder->sync_state = intel_ddi_sync_state; in intel_ddi_init()
5000 encoder->initial_fastset_check = intel_ddi_initial_fastset_check; in intel_ddi_init()
5001 encoder->suspend = intel_ddi_encoder_suspend; in intel_ddi_init()
5002 encoder->shutdown = intel_ddi_encoder_shutdown; in intel_ddi_init()
5003 encoder->get_power_domains = intel_ddi_get_power_domains; in intel_ddi_init()
5005 encoder->type = INTEL_OUTPUT_DDI; in intel_ddi_init()
5006 encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port); in intel_ddi_init()
5007 encoder->port = port; in intel_ddi_init()
5008 encoder->cloneable = 0; in intel_ddi_init()
5009 encoder->pipe_mask = ~0; in intel_ddi_init()
5012 encoder->enable_clock = intel_mtl_pll_enable; in intel_ddi_init()
5013 encoder->disable_clock = intel_mtl_pll_disable; in intel_ddi_init()
5014 encoder->port_pll_type = intel_mtl_port_pll_type; in intel_ddi_init()
5015 encoder->get_config = mtl_ddi_get_config; in intel_ddi_init()
5017 encoder->enable_clock = intel_mpllb_enable; in intel_ddi_init()
5018 encoder->disable_clock = intel_mpllb_disable; in intel_ddi_init()
5019 encoder->get_config = dg2_ddi_get_config; in intel_ddi_init()
5021 encoder->enable_clock = adls_ddi_enable_clock; in intel_ddi_init()
5022 encoder->disable_clock = adls_ddi_disable_clock; in intel_ddi_init()
5023 encoder->is_clock_enabled = adls_ddi_is_clock_enabled; in intel_ddi_init()
5024 encoder->get_config = adls_ddi_get_config; in intel_ddi_init()
5026 encoder->enable_clock = rkl_ddi_enable_clock; in intel_ddi_init()
5027 encoder->disable_clock = rkl_ddi_disable_clock; in intel_ddi_init()
5028 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled; in intel_ddi_init()
5029 encoder->get_config = rkl_ddi_get_config; in intel_ddi_init()
5031 encoder->enable_clock = dg1_ddi_enable_clock; in intel_ddi_init()
5032 encoder->disable_clock = dg1_ddi_disable_clock; in intel_ddi_init()
5033 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled; in intel_ddi_init()
5034 encoder->get_config = dg1_ddi_get_config; in intel_ddi_init()
5037 encoder->enable_clock = jsl_ddi_tc_enable_clock; in intel_ddi_init()
5038 encoder->disable_clock = jsl_ddi_tc_disable_clock; in intel_ddi_init()
5039 encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled; in intel_ddi_init()
5040 encoder->port_pll_type = icl_ddi_tc_port_pll_type; in intel_ddi_init()
5041 encoder->get_config = icl_ddi_combo_get_config; in intel_ddi_init()
5043 encoder->enable_clock = icl_ddi_combo_enable_clock; in intel_ddi_init()
5044 encoder->disable_clock = icl_ddi_combo_disable_clock; in intel_ddi_init()
5045 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; in intel_ddi_init()
5046 encoder->get_config = icl_ddi_combo_get_config; in intel_ddi_init()
5050 encoder->enable_clock = icl_ddi_tc_enable_clock; in intel_ddi_init()
5051 encoder->disable_clock = icl_ddi_tc_disable_clock; in intel_ddi_init()
5052 encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled; in intel_ddi_init()
5053 encoder->port_pll_type = icl_ddi_tc_port_pll_type; in intel_ddi_init()
5054 encoder->get_config = icl_ddi_tc_get_config; in intel_ddi_init()
5056 encoder->enable_clock = icl_ddi_combo_enable_clock; in intel_ddi_init()
5057 encoder->disable_clock = icl_ddi_combo_disable_clock; in intel_ddi_init()
5058 encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled; in intel_ddi_init()
5059 encoder->get_config = icl_ddi_combo_get_config; in intel_ddi_init()
5062 /* BXT/GLK have fixed PLL->port mapping */ in intel_ddi_init()
5063 encoder->get_config = bxt_ddi_get_config; in intel_ddi_init()
5065 encoder->enable_clock = skl_ddi_enable_clock; in intel_ddi_init()
5066 encoder->disable_clock = skl_ddi_disable_clock; in intel_ddi_init()
5067 encoder->is_clock_enabled = skl_ddi_is_clock_enabled; in intel_ddi_init()
5068 encoder->get_config = skl_ddi_get_config; in intel_ddi_init()
5070 encoder->enable_clock = hsw_ddi_enable_clock; in intel_ddi_init()
5071 encoder->disable_clock = hsw_ddi_disable_clock; in intel_ddi_init()
5072 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled; in intel_ddi_init()
5073 encoder->get_config = hsw_ddi_get_config; in intel_ddi_init()
5077 encoder->set_signal_levels = intel_cx0_phy_set_signal_levels; in intel_ddi_init()
5079 encoder->set_signal_levels = intel_snps_phy_set_signal_levels; in intel_ddi_init()
5082 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; in intel_ddi_init()
5084 encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels; in intel_ddi_init()
5087 encoder->set_signal_levels = icl_combo_phy_set_signal_levels; in intel_ddi_init()
5089 encoder->set_signal_levels = icl_mg_phy_set_signal_levels; in intel_ddi_init()
5091 encoder->set_signal_levels = bxt_dpio_phy_set_signal_levels; in intel_ddi_init()
5093 encoder->set_signal_levels = hsw_set_signal_levels; in intel_ddi_init()
5099 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port); in intel_ddi_init()
5101 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port); in intel_ddi_init()
5103 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port); in intel_ddi_init()
5105 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port); in intel_ddi_init()
5107 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port); in intel_ddi_init()
5109 encoder->hpd_pin = icl_hpd_pin(dev_priv, port); in intel_ddi_init()
5111 encoder->hpd_pin = skl_hpd_pin(dev_priv, port); in intel_ddi_init()
5113 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); in intel_ddi_init()
5116 dig_port->saved_port_bits = in intel_ddi_init()
5120 dig_port->saved_port_bits = in intel_ddi_init()
5125 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL; in intel_ddi_init()
5127 dig_port->dp.output_reg = INVALID_MMIO_REG; in intel_ddi_init()
5128 dig_port->max_lanes = intel_ddi_max_lanes(dig_port); in intel_ddi_init()
5131 dig_port->aux_ch = intel_dp_aux_ch(encoder); in intel_ddi_init()
5132 if (dig_port->aux_ch == AUX_CH_NONE) in intel_ddi_init()
5144 drm_dbg_kms(&dev_priv->drm, in intel_ddi_init()
5145 "VBT says port %c is non-legacy TC and has HDMI (with DP: %s), assume it's %s\n", in intel_ddi_init()
5148 is_legacy ? "legacy" : "non-legacy"); in intel_ddi_init()
5151 encoder->suspend_complete = intel_ddi_tc_encoder_suspend_complete; in intel_ddi_init()
5152 encoder->shutdown_complete = intel_ddi_tc_encoder_shutdown_complete; in intel_ddi_init()
5154 dig_port->lock = intel_tc_port_lock; in intel_ddi_init()
5155 dig_port->unlock = intel_tc_port_unlock; in intel_ddi_init()
5161 drm_WARN_ON(&dev_priv->drm, port > PORT_I); in intel_ddi_init()
5162 dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port); in intel_ddi_init()
5166 dig_port->connected = intel_tc_port_connected; in intel_ddi_init()
5168 dig_port->connected = lpt_digital_port_connected; in intel_ddi_init()
5170 dig_port->connected = bdw_digital_port_connected; in intel_ddi_init()
5172 dig_port->connected = lpt_digital_port_connected; in intel_ddi_init()
5175 dig_port->connected = bdw_digital_port_connected; in intel_ddi_init()
5177 dig_port->connected = lpt_digital_port_connected; in intel_ddi_init()
5180 dig_port->connected = hsw_digital_port_connected; in intel_ddi_init()
5182 dig_port->connected = lpt_digital_port_connected; in intel_ddi_init()
5191 dig_port->hpd_pulse = intel_dp_hpd_pulse; in intel_ddi_init()
5193 if (dig_port->dp.mso_link_count) in intel_ddi_init()
5194 encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv); in intel_ddi_init()
5198 * In theory we don't need the encoder->type check, in intel_ddi_init()
5201 if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { in intel_ddi_init()
5209 drm_encoder_cleanup(&encoder->base); in intel_ddi_init()