Lines Matching full:ddi

117  * Starting with Haswell, DDI port buffers must be programmed with correct
148 * Starting with Haswell, DDI port buffers must be programmed with correct
186 drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n", in mtl_wait_ddi_buf_idle()
200 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n", in intel_wait_ddi_buf_idle()
240 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n", in intel_wait_ddi_buf_active()
674 drm_dbg_kms(display->drm, "Quirk Increase DDI disabled time\n"); in intel_ddi_disable_transcoder_func()
1097 * used on all DDI platforms. Should that change we need to
2073 * For DSI we keep the ddi clocks gated in intel_ddi_sanitize_encoder_pll_mapping()
2084 "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", in intel_ddi_sanitize_encoder_pll_mapping()
2465 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n", in mtl_ddi_enable_d2d()
2554 * 6.c Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST in mtl_ddi_pre_enable_dp()
2574 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit in mtl_ddi_pre_enable_dp()
2692 * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST in tgl_ddi_pre_enable_dp()
2710 * the used lanes of the DDI. in tgl_ddi_pre_enable_dp()
2728 * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit in tgl_ddi_pre_enable_dp()
2942 drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n", in mtl_ddi_disable_d2d_link()
3310 * the bits affect a specific DDI port rather than in intel_enable_ddi_hdmi()
4825 return true; /* no strap for DDI-E */ in port_strap_detected()
4951 "DDI %c/PHY %c", in intel_ddi_init()
4959 "DDI %s%c/PHY %s%c", in intel_ddi_init()
4969 "DDI %c%s/PHY %s%c", in intel_ddi_init()
4977 "DDI %c/PHY %c", port_name(port), phy_name(phy)); in intel_ddi_init()