Lines Matching +full:0 +full:xc02
30 #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A 0x64040
31 #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B 0x64140
32 #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1 0x16F240
33 #define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2 0x16F440
45 … XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1)
46 …ne XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x2)
47 #define XELPDP_PORT_M2P_COMMAND_READ REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x3)
51 #define XELPDP_PORT_M2P_ADDRESS_MASK REG_GENMASK(11, 0)
65 #define XELPDP_PORT_P2M_COMMAND_READ_ACK 0x4
66 #define XELPDP_PORT_P2M_COMMAND_WRITE_ACK 0x5
81 #define _XELPDP_PORT_BUF_CTL1_LN0_A 0x64004
82 #define _XELPDP_PORT_BUF_CTL1_LN0_B 0x64104
83 #define _XELPDP_PORT_BUF_CTL1_LN0_USBC1 0x16F200
84 #define _XELPDP_PORT_BUF_CTL1_LN0_USBC2 0x16F400
98 #define XELPDP_PORT_BUF_PORT_DATA_10BIT REG_FIELD_PREP(XELPDP_PORT_BUF_PORT_DATA_WIDTH_MASK, 0)
129 #define XELPDP_LANE_POWERDOWN_NEW_STATE_MASK REG_GENMASK(3, 0)
144 #define XELPDP_POWER_STATE_ACTIVE_MASK REG_GENMASK(3, 0)
146 #define CX0_P0_STATE_ACTIVE 0x0
147 #define CX0_P2_STATE_READY 0x2
148 #define CX0_P2PG_STATE_DISABLE 0x9
149 #define CX0_P4PG_STATE_DISABLE 0xC
150 #define CX0_P2_STATE_RESET 0x2
152 #define _XELPDP_PORT_MSGBUS_TIMER_LN0_A 0x640d8
153 #define _XELPDP_PORT_MSGBUS_TIMER_LN0_B 0x641d8
154 #define _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC1 0x16f258
155 #define _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC2 0x16f458
166 #define XELPDP_PORT_MSGBUS_TIMER_VAL_MASK REG_GENMASK(23, 0)
167 #define XELPDP_PORT_MSGBUS_TIMER_VAL REG_FIELD_PREP(XELPDP_PORT_MSGBUS_TIMER_VAL_MASK, 0xa000)
169 #define _XELPDP_PORT_CLOCK_CTL_A 0x640E0
170 #define _XELPDP_PORT_CLOCK_CTL_B 0x641E0
171 #define _XELPDP_PORT_CLOCK_CTL_USBC1 0x16F260
172 #define _XELPDP_PORT_CLOCK_CTL_USBC2 0x16F460
191 #define XELPDP_DDI_CLOCK_SELECT_NONE 0x0
192 #define XELPDP_DDI_CLOCK_SELECT_MAXPCLK 0x8
193 #define XELPDP_DDI_CLOCK_SELECT_DIV18CLK 0x9
194 #define XELPDP_DDI_CLOCK_SELECT_TBT_162 0xc
195 #define XELPDP_DDI_CLOCK_SELECT_TBT_270 0xd
196 #define XELPDP_DDI_CLOCK_SELECT_TBT_540 0xe
197 #define XELPDP_DDI_CLOCK_SELECT_TBT_810 0xf
201 #define XELPDP_SSC_ENABLE_PLLB REG_BIT(0)
204 #define PHY_C10_VDR_PLL(idx) (0xC00 + (idx))
206 #define C10_PLL3_MULTIPLIERH_MASK REG_GENMASK8(3, 0)
207 #define C10_PLL15_TXCLKDIV_MASK REG_GENMASK8(2, 0)
210 #define PHY_C10_VDR_CMN(idx) (0xC20 + (idx))
211 #define C10_CMN0_REF_RANGE REG_FIELD_PREP(REG_GENMASK(4, 0), 1)
215 #define PHY_C10_VDR_TX(idx) (0xC30 + (idx))
219 #define PHY_C10_VDR_CONTROL(idx) (0xC70 + (idx) - 1)
222 #define C10_VDR_CTRL_UPDATE_CFG REG_BIT8(0)
223 #define PHY_C10_VDR_CUSTOM_WIDTH 0xD02
224 #define C10_VDR_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0)
225 #define C10_VDR_CUSTOM_WIDTH_8_10 REG_FIELD_PREP(C10_VDR_CUSTOM_WIDTH_MASK, 0)
226 #define PHY_C10_VDR_OVRD 0xD71
227 #define PHY_C10_VDR_OVRD_TX1 REG_BIT8(0)
229 #define PHY_C10_VDR_PRE_OVRD_TX1 0xD80
230 #define C10_PHY_OVRD_LEVEL_MASK REG_GENMASK8(5, 0)
234 ((lane) ^ (tx)) * 0x10 + (control))
237 #define PHY_CX0_TX_CONTROL(tx, control) (0x400 + ((tx) - 1) * 0x200 + (control))
241 #define PHY_C20_WR_ADDRESS_L 0xC02
242 #define PHY_C20_WR_ADDRESS_H 0xC03
243 #define PHY_C20_WR_DATA_L 0xC04
244 #define PHY_C20_WR_DATA_H 0xC05
245 #define PHY_C20_RD_ADDRESS_L 0xC06
246 #define PHY_C20_RD_ADDRESS_H 0xC07
247 #define PHY_C20_RD_DATA_L 0xC08
248 #define PHY_C20_RD_DATA_H 0xC09
249 #define PHY_C20_VDR_CUSTOM_SERDES_RATE 0xD00
250 #define PHY_C20_VDR_HDMI_RATE 0xD01
251 #define PHY_C20_CONTEXT_TOGGLE REG_BIT8(0)
254 #define PHY_C20_VDR_CUSTOM_WIDTH 0xD02
255 #define PHY_C20_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0)
258 #define _MTL_C20_A_TX_CNTX_CFG 0xCF2E
259 #define _MTL_C20_B_TX_CNTX_CFG 0xCF2A
260 #define _MTL_C20_A_CMN_CNTX_CFG 0xCDAA
261 #define _MTL_C20_B_CMN_CNTX_CFG 0xCDA5
262 #define _MTL_C20_A_MPLLA_CFG 0xCCF0
263 #define _MTL_C20_B_MPLLA_CFG 0xCCE5
264 #define _MTL_C20_A_MPLLB_CFG 0xCB5A
265 #define _MTL_C20_B_MPLLB_CFG 0xCB4E
267 #define _XE2HPD_C20_A_TX_CNTX_CFG 0xCF5E
268 #define _XE2HPD_C20_B_TX_CNTX_CFG 0xCF5A
269 #define _XE2HPD_C20_A_CMN_CNTX_CFG 0xCE8E
270 #define _XE2HPD_C20_B_CMN_CNTX_CFG 0xCE89
271 #define _XE2HPD_C20_A_MPLLA_CFG 0xCE58
272 #define _XE2HPD_C20_B_MPLLA_CFG 0xCE4D
273 #define _XE2HPD_C20_A_MPLLB_CFG 0xCCC2
274 #define _XE2HPD_C20_B_MPLLB_CFG 0xCCB6
282 #define C20_PHY_TX_RATE REG_GENMASK(2, 0)
304 #define C20_MULTIPLIER_MASK REG_GENMASK(11, 0)
308 #define C20_PHY_VSWING_PREEMPH_MASK REG_GENMASK8(5, 0)
311 #define RAWLANEAONX_DIG_TX_MPLLB_CAL_DONE_BANK(idx) (0x303D + (idx))
320 #define MPLL_FRACN_DEN 0xFFFF
328 #define MPLLB_ANA_FREQ_VCO_0 0
335 #define MPLL_DIV_MULTIPLIER_MASK REG_GENMASK16(7, 0)
343 #define CP_INT_GS_MASK REG_GENMASK16(6, 0)
351 #define CP_INT_MASK REG_GENMASK16(6, 0)
363 #define HDMI_DIV_MASK REG_GENMASK16(2, 0)