Lines Matching defs:lane
34 #define _XELPDP_PORT_M2P_MSGBUS_CTL(idx, lane) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ argument
39 #define XELPDP_PORT_M2P_MSGBUS_CTL(i915__, port, lane) \ argument
54 #define _XELPDP_PORT_P2M_MSGBUS_STATUS(idx, lane) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \ argument
59 #define XELPDP_PORT_P2M_MSGBUS_STATUS(i915__, port, lane) \ argument
119 #define XELPDP_LANE_PIPE_RESET(lane) _PICK(lane, REG_BIT(31), REG_BIT(30)) argument
120 #define XELPDP_LANE_PHY_CURRENT_STATUS(lane) _PICK(lane, REG_BIT(29), REG_BIT(28)) argument
121 #define XELPDP_LANE_POWERDOWN_UPDATE(lane) _PICK(lane, REG_BIT(25), REG_BIT(24)) argument
126 #define XELPDP_LANE_POWERDOWN_NEW_STATE(lane, val) _PICK(lane, \ argument
156 #define _XELPDP_PORT_MSGBUS_TIMER(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ argument
161 #define XELPDP_PORT_MSGBUS_TIMER(i915__, port, lane) \ argument
182 #define XELPDP_LANE_PCLK_PLL_REQUEST(lane) REG_BIT(31 - ((lane) * 4)) argument
183 #define XELPDP_LANE_PCLK_PLL_ACK(lane) REG_BIT(30 - ((lane) * 4)) argument
184 #define XELPDP_LANE_PCLK_REFCLK_REQUEST(lane) REG_BIT(29 - ((lane) * 4)) argument
185 #define XELPDP_LANE_PCLK_REFCLK_ACK(lane) REG_BIT(28 - ((lane) * 4)) argument
232 #define PHY_CX0_VDROVRD_CTL(lane, tx, control) \ argument