Lines Matching refs:pll_state
2007 struct intel_cx0pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll; in intel_c10pll_update_pll() local
2014 pll_state->ssc_enabled = in intel_c10pll_update_pll()
2019 if (pll_state->ssc_enabled) in intel_c10pll_update_pll()
2022 drm_WARN_ON(&i915->drm, ARRAY_SIZE(pll_state->c10.pll) < 9); in intel_c10pll_update_pll()
2024 pll_state->c10.pll[i] = 0; in intel_c10pll_update_pll()
2051 struct intel_c10pll_state *pll_state) in intel_c10pll_readout_hw_state() argument
2067 for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) in intel_c10pll_readout_hw_state()
2068 pll_state->pll[i] = intel_cx0_read(encoder, lane, PHY_C10_VDR_PLL(i)); in intel_c10pll_readout_hw_state()
2070 pll_state->cmn = intel_cx0_read(encoder, lane, PHY_C10_VDR_CMN(0)); in intel_c10pll_readout_hw_state()
2071 pll_state->tx = intel_cx0_read(encoder, lane, PHY_C10_VDR_TX(0)); in intel_c10pll_readout_hw_state()
2080 const struct intel_c10pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c10; in intel_c10_pll_program() local
2096 for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) in intel_c10_pll_program()
2098 pll_state->pll[i], in intel_c10_pll_program()
2101 intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), pll_state->cmn, MB_WRITE_COMMITTED); in intel_c10_pll_program()
2102 intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_TX(0), pll_state->tx, MB_WRITE_COMMITTED); in intel_c10_pll_program()
2145 static int intel_c20_compute_hdmi_tmds_pll(u64 pixel_clock, struct intel_c20pll_state *pll_state) in intel_c20_compute_hdmi_tmds_pll() argument
2183 pll_state->clock = pixel_clock; in intel_c20_compute_hdmi_tmds_pll()
2184 pll_state->tx[0] = 0xbe88; in intel_c20_compute_hdmi_tmds_pll()
2185 pll_state->tx[1] = 0x9800; in intel_c20_compute_hdmi_tmds_pll()
2186 pll_state->tx[2] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2187 pll_state->cmn[0] = 0x0500; in intel_c20_compute_hdmi_tmds_pll()
2188 pll_state->cmn[1] = 0x0005; in intel_c20_compute_hdmi_tmds_pll()
2189 pll_state->cmn[2] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2190 pll_state->cmn[3] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2191 pll_state->mpllb[0] = (MPLL_TX_CLK_DIV(mpll_tx_clk_div) | in intel_c20_compute_hdmi_tmds_pll()
2193 pll_state->mpllb[1] = (CAL_DAC_CODE(CAL_DAC_CODE_31) | in intel_c20_compute_hdmi_tmds_pll()
2196 pll_state->mpllb[2] = (MPLLB_ANA_FREQ_VCO(mpllb_ana_freq_vco) | in intel_c20_compute_hdmi_tmds_pll()
2199 pll_state->mpllb[3] = (V2I(V2I_2) | in intel_c20_compute_hdmi_tmds_pll()
2202 pll_state->mpllb[4] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2203 pll_state->mpllb[5] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2204 pll_state->mpllb[6] = (C20_MPLLB_FRACEN | SSC_UP_SPREAD); in intel_c20_compute_hdmi_tmds_pll()
2205 pll_state->mpllb[7] = MPLL_FRACN_DEN; in intel_c20_compute_hdmi_tmds_pll()
2206 pll_state->mpllb[8] = mpll_fracn_quot; in intel_c20_compute_hdmi_tmds_pll()
2207 pll_state->mpllb[9] = mpll_fracn_rem; in intel_c20_compute_hdmi_tmds_pll()
2208 pll_state->mpllb[10] = HDMI_DIV(HDMI_DIV_1); in intel_c20_compute_hdmi_tmds_pll()
2303 const struct intel_c20pll_state *pll_state) in intel_c20pll_calc_port_clock() argument
2312 unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]); in intel_c20pll_calc_port_clock()
2314 if (intel_c20phy_use_mpllb(pll_state)) { in intel_c20pll_calc_port_clock()
2316 frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]); in intel_c20pll_calc_port_clock()
2317 frac_quot = pll_state->mpllb[8]; in intel_c20pll_calc_port_clock()
2318 frac_rem = pll_state->mpllb[9]; in intel_c20pll_calc_port_clock()
2319 frac_den = pll_state->mpllb[7]; in intel_c20pll_calc_port_clock()
2320 multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]); in intel_c20pll_calc_port_clock()
2321 tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]); in intel_c20pll_calc_port_clock()
2322 ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]); in intel_c20pll_calc_port_clock()
2326 frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]); in intel_c20pll_calc_port_clock()
2327 frac_quot = pll_state->mplla[8]; in intel_c20pll_calc_port_clock()
2328 frac_rem = pll_state->mplla[9]; in intel_c20pll_calc_port_clock()
2329 frac_den = pll_state->mplla[7]; in intel_c20pll_calc_port_clock()
2330 multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]); in intel_c20pll_calc_port_clock()
2331 tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]); in intel_c20pll_calc_port_clock()
2332 ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]); in intel_c20pll_calc_port_clock()
2333 fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]); in intel_c20pll_calc_port_clock()
2348 struct intel_c20pll_state *pll_state) in intel_c20pll_readout_hw_state() argument
2361 for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { in intel_c20pll_readout_hw_state()
2363 pll_state->tx[i] = intel_c20_sram_read(encoder, in intel_c20pll_readout_hw_state()
2367 pll_state->tx[i] = intel_c20_sram_read(encoder, in intel_c20pll_readout_hw_state()
2373 for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { in intel_c20pll_readout_hw_state()
2375 pll_state->cmn[i] = intel_c20_sram_read(encoder, in intel_c20pll_readout_hw_state()
2379 pll_state->cmn[i] = intel_c20_sram_read(encoder, in intel_c20pll_readout_hw_state()
2384 if (intel_c20phy_use_mpllb(pll_state)) { in intel_c20pll_readout_hw_state()
2386 for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { in intel_c20pll_readout_hw_state()
2388 pll_state->mpllb[i] = intel_c20_sram_read(encoder, in intel_c20pll_readout_hw_state()
2392 pll_state->mpllb[i] = intel_c20_sram_read(encoder, in intel_c20pll_readout_hw_state()
2398 for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { in intel_c20pll_readout_hw_state()
2400 pll_state->mplla[i] = intel_c20_sram_read(encoder, in intel_c20pll_readout_hw_state()
2404 pll_state->mplla[i] = intel_c20_sram_read(encoder, in intel_c20pll_readout_hw_state()
2410 pll_state->clock = intel_c20pll_calc_port_clock(encoder, pll_state); in intel_c20pll_readout_hw_state()
2545 const struct intel_c20pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c20; in intel_c20_pll_program() local
2571 for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { in intel_c20_pll_program()
2575 pll_state->tx[i]); in intel_c20_pll_program()
2579 pll_state->tx[i]); in intel_c20_pll_program()
2583 for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { in intel_c20_pll_program()
2587 pll_state->cmn[i]); in intel_c20_pll_program()
2591 pll_state->cmn[i]); in intel_c20_pll_program()
2595 if (intel_c20phy_use_mpllb(pll_state)) { in intel_c20_pll_program()
2596 for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { in intel_c20_pll_program()
2600 pll_state->mpllb[i]); in intel_c20_pll_program()
2604 pll_state->mpllb[i]); in intel_c20_pll_program()
2607 for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { in intel_c20_pll_program()
2611 pll_state->mplla[i]); in intel_c20_pll_program()
2615 pll_state->mplla[i]); in intel_c20_pll_program()
2651 const struct intel_c10pll_state *pll_state) in intel_c10pll_calc_port_clock() argument
2657 if (pll_state->pll[0] & C10_PLL0_FRACEN) { in intel_c10pll_calc_port_clock()
2658 frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11]; in intel_c10pll_calc_port_clock()
2659 frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13]; in intel_c10pll_calc_port_clock()
2660 frac_den = pll_state->pll[10] << 8 | pll_state->pll[9]; in intel_c10pll_calc_port_clock()
2663 multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 | in intel_c10pll_calc_port_clock()
2664 pll_state->pll[2]) / 2 + 16; in intel_c10pll_calc_port_clock()
2666 tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]); in intel_c10pll_calc_port_clock()
2667 hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]); in intel_c10pll_calc_port_clock()
3278 struct intel_cx0pll_state *pll_state) in intel_cx0pll_readout_hw_state() argument
3280 pll_state->use_c10 = false; in intel_cx0pll_readout_hw_state()
3282 pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)); in intel_cx0pll_readout_hw_state()
3283 if (pll_state->tbt_mode) in intel_cx0pll_readout_hw_state()
3287 intel_c10pll_readout_hw_state(encoder, &pll_state->c10); in intel_cx0pll_readout_hw_state()
3288 pll_state->use_c10 = true; in intel_cx0pll_readout_hw_state()
3290 intel_c20pll_readout_hw_state(encoder, &pll_state->c20); in intel_cx0pll_readout_hw_state()
3347 const struct intel_cx0pll_state *pll_state) in intel_cx0pll_calc_port_clock() argument
3350 return intel_c10pll_calc_port_clock(encoder, &pll_state->c10); in intel_cx0pll_calc_port_clock()
3352 return intel_c20pll_calc_port_clock(encoder, &pll_state->c20); in intel_cx0pll_calc_port_clock()