510 	.cmn = 0x21,
536 	.cmn = 0x21,
562 	.cmn = 0x21,
588 	.cmn = 0x21,
614 	.cmn = 0x21,
640 	.cmn = 0x21,
666 	.cmn = 0x21,
692 	.cmn = 0x21,
718 	.cmn = 0x21,
769 	.cmn = {0x0500, /* cmn cfg0*/
770 		0x0005, /* cmn cfg1 */
771 		0x0000, /* cmn cfg2 */
772 		0x0000, /* cmn cfg3 */
794 	.cmn = {0x0500, /* cmn cfg0*/
795 		0x0005, /* cmn cfg1 */
796 		0x0000, /* cmn cfg2 */
797 		0x0000, /* cmn cfg3 */
819 	.cmn = {0x0500, /* cmn cfg0*/
820 		0x0005, /* cmn cfg1 */
821 		0x0000, /* cmn cfg2 */
822 		0x0000, /* cmn cfg3 */
844 	.cmn = {0x0500, /* cmn cfg0*/
845 		0x0005, /* cmn cfg1 */
846 		0x0000, /* cmn cfg2 */
847 		0x0000, /* cmn cfg3 */
870 	.cmn = {0x0700, /* cmn cfg0*/
871 		0x0005, /* cmn cfg1 */
872 		0x0000, /* cmn cfg2 */
873 		0x0000, /* cmn cfg3 */
894 	.cmn = {0x0500, /* cmn cfg0*/
895 		0x0005, /* cmn cfg1 */
896 		0x0000, /* cmn cfg2 */
897 		0x0000, /* cmn cfg3 */
919 	.cmn = {0x0500, /* cmn cfg0*/
920 		0x0005, /* cmn cfg1 */
921 		0x0000, /* cmn cfg2 */
922 		0x0000, /* cmn cfg3 */
958 	.cmn = { 0x0500,
983 	.cmn = { 0x0500,
1008 	.cmn = { 0x0500,
1033 	.cmn = { 0x0500,
1058 	.cmn = { 0x0500,
1096 	.cmn = {0x0500, /* cmn cfg0*/
1097 		0x0005, /* cmn cfg1 */
1098 		0x0000, /* cmn cfg2 */
1099 		0x0000, /* cmn cfg3 */
1132 	.cmn = 0x1,
1158 	.cmn = 0x1,
1184 	.cmn = 0x1,
1210 	.cmn = 0x1,
1236 	.cmn = 0x1,
1263 	.cmn = 0x1,
1273 	.cmn = 0x1,
1283 	.cmn = 0x1,
1293 	.cmn = 0x1,
1303 	.cmn = 0x1,
1313 	.cmn = 0x1,
1323 	.cmn = 0x1,
1333 	.cmn = 0x1,
1343 	.cmn = 0x1,
1353 	.cmn = 0x1,
1363 	.cmn = 0x1,
1373 	.cmn = 0x1,
1383 	.cmn = 0x1,
1393 	.cmn = 0x1,
1403 	.cmn = 0x1,
1413 	.cmn = 0x1,
1423 	.cmn = 0x1,
1433 	.cmn = 0x1,
1443 	.cmn = 0x1,
1453 	.cmn = 0x1,
1463 	.cmn = 0x1,
1473 	.cmn = 0x1,
1483 	.cmn = 0x1,
1493 	.cmn = 0x1,
1503 	.cmn = 0x1,
1513 	.cmn = 0x1,
1523 	.cmn = 0x1,
1533 	.cmn = 0x1,
1543 	.cmn = 0x1,
1553 	.cmn = 0x1,
1563 	.cmn = 0x1,
1573 	.cmn = 0x1,
1583 	.cmn = 0x1,
1593 	.cmn = 0x1,
1603 	.cmn = 0x1,
1613 	.cmn = 0x1,
1623 	.cmn = 0x1,
1633 	.cmn = 0x1,
1643 	.cmn = 0x1,
1653 	.cmn = 0x1,
1715 	.cmn = { 0x0500, /* cmn cfg0*/
1716 		  0x0005, /* cmn cfg1 */
1717 		  0x0000, /* cmn cfg2 */
1718 		  0x0000, /* cmn cfg3 */
1740 	.cmn = { 0x0500, /* cmn cfg0*/
1741 		  0x0005, /* cmn cfg1 */
1742 		  0x0000, /* cmn cfg2 */
1743 		  0x0000, /* cmn cfg3 */
1765 	.cmn = { 0x0500, /* cmn cfg0*/
1766 		  0x0005, /* cmn cfg1 */
1767 		  0x0000, /* cmn cfg2 */
1768 		  0x0000, /* cmn cfg3 */
1790 	.cmn = { 0x0500, /* cmn cfg0*/
1791 		  0x0005, /* cmn cfg1 */
1792 		  0x0000, /* cmn cfg2 */
1793 		  0x0000, /* cmn cfg3 */
1815 	.cmn = { 0x0500, /* cmn cfg0*/
1816 		  0x0005, /* cmn cfg1 */
1817 		  0x0000, /* cmn cfg2 */
1818 		  0x0000, /* cmn cfg3 */
1840 	.cmn = { 0x0500, /* cmn cfg0*/
1841 		  0x0005, /* cmn cfg1 */
1842 		  0x0000, /* cmn cfg2 */
1843 		  0x0000, /* cmn cfg3 */
1865 	.cmn = { 0x0500, /* cmn cfg0*/
1866 		  0x0005, /* cmn cfg1 */
1867 		  0x0000, /* cmn cfg2 */
1868 		  0x0000, /* cmn cfg3 */
1890 	.cmn = { 0x0500, /* cmn cfg0*/
1891 		  0x0005, /* cmn cfg1 */
1892 		  0x0000, /* cmn cfg2 */
1893 		  0x0000, /* cmn cfg3 */
1915 	.cmn = { 0x0500, /* cmn cfg0*/
1916 		  0x0005, /* cmn cfg1 */
1917 		  0x0000, /* cmn cfg2 */
1918 		  0x0000, /* cmn cfg3 */
1940 	.cmn = { 0x0500, /* cmn cfg0*/
1941 		  0x0005, /* cmn cfg1 */
1942 		  0x0000, /* cmn cfg2 */
1943 		  0x0000, /* cmn cfg3 */
2070 	pll_state->cmn = intel_cx0_read(encoder, lane, PHY_C10_VDR_CMN(0));  in intel_c10pll_readout_hw_state()
2101 	intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), pll_state->cmn, MB_WRITE_COMMITTED);  in intel_c10_pll_program()
2136 	drm_dbg_kms(&i915->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx, hw_state->cmn);  in intel_c10pll_dump_hw_state()
2187 	pll_state->cmn[0]	= 0x0500;  in intel_c20_compute_hdmi_tmds_pll()
2188 	pll_state->cmn[1]	= 0x0005;  in intel_c20_compute_hdmi_tmds_pll()
2189 	pll_state->cmn[2]	= 0x0000;  in intel_c20_compute_hdmi_tmds_pll()
2190 	pll_state->cmn[3]	= 0x0000;  in intel_c20_compute_hdmi_tmds_pll()
2373 	for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {  in intel_c20pll_readout_hw_state()
2375 			pll_state->cmn[i] = intel_c20_sram_read(encoder,  in intel_c20pll_readout_hw_state()
2379 			pll_state->cmn[i] = intel_c20_sram_read(encoder,  in intel_c20pll_readout_hw_state()
2423 	drm_dbg_kms(&i915->drm, "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n",  in intel_c20pll_dump_hw_state()
2424 		    hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]);  in intel_c20pll_dump_hw_state()
2583 	for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {  in intel_c20_pll_program()
2587 					     pll_state->cmn[i]);  in intel_c20_pll_program()
2591 					     pll_state->cmn[i]);  in intel_c20_pll_program()
3271 	I915_STATE_WARN(i915, mpllb_hw_state->cmn != mpllb_sw_state->cmn,  in intel_c10pll_state_verify()
3274 			mpllb_sw_state->cmn, mpllb_hw_state->cmn);  in intel_c10pll_state_verify()
3300 	if (a->cmn != b->cmn)  in mtl_compare_hw_state_c10()
3315 	if (memcmp(&a->cmn, &b->cmn, sizeof(a->cmn)) != 0)  in mtl_compare_hw_state_c20()
3400 	for (i = 0; i < ARRAY_SIZE(mpll_sw_state->cmn); i++) {  in intel_c20pll_state_verify()
3401 		I915_STATE_WARN(i915, mpll_hw_state->cmn[i] != mpll_sw_state->cmn[i],  in intel_c20pll_state_verify()
3402 				"[CRTC:%d:%s] mismatch in C20: Register CMN[%i] (expected 0x%04x, found 0x%04x)",  in intel_c20pll_state_verify()
3404 				mpll_sw_state->cmn[i], mpll_hw_state->cmn[i]);  in intel_c20pll_state_verify()