Lines Matching +full:4 +full:- +full:lane
1 // SPDX-License-Identifier: MIT
34 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_encoder_is_c10phy()
60 * In DP-alt with pin assignment D, only PHY lane 0 is owned in intel_cx0_get_owned_lane_mask()
61 * by display and lane 1 is owned by USB. in intel_cx0_get_owned_lane_mask()
73 drm_WARN_ON(&i915->drm, !enabled); in assert_dc_off()
78 int lane; in intel_cx0_program_msgbus_timer() local
79 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_program_msgbus_timer()
81 for_each_cx0_lane_in_mask(INTEL_CX0_BOTH_LANES, lane) in intel_cx0_program_msgbus_timer()
83 XELPDP_PORT_MSGBUS_TIMER(i915, encoder->port, lane), in intel_cx0_program_msgbus_timer()
100 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_transaction_begin()
112 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_transaction_end()
120 int lane) in intel_clear_response_ready_flag() argument
122 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_clear_response_ready_flag()
124 intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, encoder->port, lane), in intel_clear_response_ready_flag()
128 static void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane) in intel_cx0_bus_reset() argument
130 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_bus_reset()
131 enum port port = encoder->port; in intel_cx0_bus_reset()
134 intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane), in intel_cx0_bus_reset()
137 if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane), in intel_cx0_bus_reset()
140 drm_err_once(&i915->drm, "Failed to bring PHY %c to idle.\n", phy_name(phy)); in intel_cx0_bus_reset()
144 intel_clear_response_ready_flag(encoder, lane); in intel_cx0_bus_reset()
148 int command, int lane, u32 *val) in intel_cx0_wait_for_ack() argument
150 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_wait_for_ack()
151 enum port port = encoder->port; in intel_cx0_wait_for_ack()
155 XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane), in intel_cx0_wait_for_ack()
160 drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for message ACK. Status: 0x%x\n", in intel_cx0_wait_for_ack()
163 if (!(intel_de_read(i915, XELPDP_PORT_MSGBUS_TIMER(i915, port, lane)) & in intel_cx0_wait_for_ack()
165 drm_dbg_kms(&i915->drm, in intel_cx0_wait_for_ack()
169 intel_cx0_bus_reset(encoder, lane); in intel_cx0_wait_for_ack()
170 return -ETIMEDOUT; in intel_cx0_wait_for_ack()
174 drm_dbg_kms(&i915->drm, "PHY %c Error occurred during %s command. Status: 0x%x\n", phy_name(phy), in intel_cx0_wait_for_ack()
176 intel_cx0_bus_reset(encoder, lane); in intel_cx0_wait_for_ack()
177 return -EINVAL; in intel_cx0_wait_for_ack()
181 drm_dbg_kms(&i915->drm, "PHY %c Not a %s response. MSGBUS Status: 0x%x.\n", phy_name(phy), in intel_cx0_wait_for_ack()
183 intel_cx0_bus_reset(encoder, lane); in intel_cx0_wait_for_ack()
184 return -EINVAL; in intel_cx0_wait_for_ack()
191 int lane, u16 addr) in __intel_cx0_read_once() argument
193 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in __intel_cx0_read_once()
194 enum port port = encoder->port; in __intel_cx0_read_once()
199 if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane), in __intel_cx0_read_once()
202 drm_dbg_kms(&i915->drm, in __intel_cx0_read_once()
204 intel_cx0_bus_reset(encoder, lane); in __intel_cx0_read_once()
205 return -ETIMEDOUT; in __intel_cx0_read_once()
208 intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane), in __intel_cx0_read_once()
213 ack = intel_cx0_wait_for_ack(encoder, XELPDP_PORT_P2M_COMMAND_READ_ACK, lane, &val); in __intel_cx0_read_once()
217 intel_clear_response_ready_flag(encoder, lane); in __intel_cx0_read_once()
224 intel_cx0_bus_reset(encoder, lane); in __intel_cx0_read_once()
230 int lane, u16 addr) in __intel_cx0_read() argument
232 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in __intel_cx0_read()
240 status = __intel_cx0_read_once(encoder, lane, addr); in __intel_cx0_read()
246 drm_err_once(&i915->drm, "PHY %c Read %04x failed after %d retries.\n", in __intel_cx0_read()
255 int lane = lane_mask_to_lane(lane_mask); in intel_cx0_read() local
257 return __intel_cx0_read(encoder, lane, addr); in intel_cx0_read()
261 int lane, u16 addr, u8 data, bool committed) in __intel_cx0_write_once() argument
263 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in __intel_cx0_write_once()
264 enum port port = encoder->port; in __intel_cx0_write_once()
269 if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane), in __intel_cx0_write_once()
272 drm_dbg_kms(&i915->drm, in __intel_cx0_write_once()
274 intel_cx0_bus_reset(encoder, lane); in __intel_cx0_write_once()
275 return -ETIMEDOUT; in __intel_cx0_write_once()
278 intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane), in __intel_cx0_write_once()
285 if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane), in __intel_cx0_write_once()
288 drm_dbg_kms(&i915->drm, in __intel_cx0_write_once()
290 intel_cx0_bus_reset(encoder, lane); in __intel_cx0_write_once()
291 return -ETIMEDOUT; in __intel_cx0_write_once()
295 ack = intel_cx0_wait_for_ack(encoder, XELPDP_PORT_P2M_COMMAND_WRITE_ACK, lane, &val); in __intel_cx0_write_once()
298 } else if ((intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane)) & in __intel_cx0_write_once()
300 drm_dbg_kms(&i915->drm, in __intel_cx0_write_once()
302 intel_cx0_bus_reset(encoder, lane); in __intel_cx0_write_once()
303 return -EINVAL; in __intel_cx0_write_once()
306 intel_clear_response_ready_flag(encoder, lane); in __intel_cx0_write_once()
313 intel_cx0_bus_reset(encoder, lane); in __intel_cx0_write_once()
319 int lane, u16 addr, u8 data, bool committed) in __intel_cx0_write() argument
321 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in __intel_cx0_write()
329 status = __intel_cx0_write_once(encoder, lane, addr, data, committed); in __intel_cx0_write()
335 drm_err_once(&i915->drm, in __intel_cx0_write()
342 int lane; in intel_cx0_write() local
344 for_each_cx0_lane_in_mask(lane_mask, lane) in intel_cx0_write()
345 __intel_cx0_write(encoder, lane, addr, data, committed); in intel_cx0_write()
349 int lane, u16 addr, u16 data) in intel_c20_sram_write() argument
351 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_c20_sram_write()
355 intel_cx0_write(encoder, lane, PHY_C20_WR_ADDRESS_H, addr >> 8, 0); in intel_c20_sram_write()
356 intel_cx0_write(encoder, lane, PHY_C20_WR_ADDRESS_L, addr & 0xff, 0); in intel_c20_sram_write()
358 intel_cx0_write(encoder, lane, PHY_C20_WR_DATA_H, data >> 8, 0); in intel_c20_sram_write()
359 intel_cx0_write(encoder, lane, PHY_C20_WR_DATA_L, data & 0xff, 1); in intel_c20_sram_write()
363 int lane, u16 addr) in intel_c20_sram_read() argument
365 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_c20_sram_read()
370 intel_cx0_write(encoder, lane, PHY_C20_RD_ADDRESS_H, addr >> 8, 0); in intel_c20_sram_read()
371 intel_cx0_write(encoder, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff, 1); in intel_c20_sram_read()
373 val = intel_cx0_read(encoder, lane, PHY_C20_RD_DATA_H); in intel_c20_sram_read()
375 val |= intel_cx0_read(encoder, lane, PHY_C20_RD_DATA_L); in intel_c20_sram_read()
381 int lane, u16 addr, u8 clear, u8 set, bool committed) in __intel_cx0_rmw() argument
385 old = __intel_cx0_read(encoder, lane, addr); in __intel_cx0_rmw()
389 __intel_cx0_write(encoder, lane, addr, val, committed); in __intel_cx0_rmw()
395 u8 lane; in intel_cx0_rmw() local
397 for_each_cx0_lane_in_mask(lane_mask, lane) in intel_cx0_rmw()
398 __intel_cx0_rmw(encoder, lane, addr, clear, set, committed); in intel_cx0_rmw()
405 (crtc_state->port_clock == 540000 || in intel_c10_get_tx_vboost_lvl()
406 crtc_state->port_clock == 810000)) in intel_c10_get_tx_vboost_lvl()
409 return 4; in intel_c10_get_tx_vboost_lvl()
419 (crtc_state->port_clock == 540000 || in intel_c10_get_tx_term_ctl()
420 crtc_state->port_clock == 810000)) in intel_c10_get_tx_term_ctl()
432 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_set_signal_levels()
446 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in intel_cx0_phy_set_signal_levels()
447 if (drm_WARN_ON_ONCE(&i915->drm, !trans)) { in intel_cx0_phy_set_signal_levels()
465 for (ln = 0; ln < crtc_state->lane_count; ln++) { in intel_cx0_phy_set_signal_levels()
467 int lane = ln / 2; in intel_cx0_phy_set_signal_levels() local
469 u8 lane_mask = lane == 0 ? INTEL_CX0_LANE0 : INTEL_CX0_LANE1; in intel_cx0_phy_set_signal_levels()
474 intel_cx0_rmw(encoder, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 0), in intel_cx0_phy_set_signal_levels()
476 C10_PHY_OVRD_LEVEL(trans->entries[level].snps.pre_cursor), in intel_cx0_phy_set_signal_levels()
478 intel_cx0_rmw(encoder, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 1), in intel_cx0_phy_set_signal_levels()
480 C10_PHY_OVRD_LEVEL(trans->entries[level].snps.vswing), in intel_cx0_phy_set_signal_levels()
482 intel_cx0_rmw(encoder, lane_mask, PHY_CX0_VDROVRD_CTL(lane, tx, 2), in intel_cx0_phy_set_signal_levels()
484 C10_PHY_OVRD_LEVEL(trans->entries[level].snps.post_cursor), in intel_cx0_phy_set_signal_levels()
502 * Note: The tables below are with SSC. In non-ssc
503 * registers 0xC04 to 0xC08(pll[4] to pll[8]) will be
515 .pll[4] = 0x26,
541 .pll[4] = 0x33,
567 .pll[4] = 0x39,
593 .pll[4] = 0x20,
619 .pll[4] = 0x26,
645 .pll[4] = 0x33,
671 .pll[4] = 0x20,
697 .pll[4] = 0xA8,
723 .pll[4] = 0x30,
1137 .pll[4] = 0,
1163 .pll[4] = 0,
1189 .pll[4] = 0,
1215 .pll[4] = 0,
1241 .pll[4] = 0,
1264 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
1274 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xCC, .pll[3] = 0x00, .pll[4] = 0x00,
1284 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xDC, .pll[3] = 0x00, .pll[4] = 0x00,
1294 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x62, .pll[3] = 0x00, .pll[4] = 0x00,
1304 .pll[0] = 0xC4, .pll[1] = 0x00, .pll[2] = 0x76, .pll[3] = 0x00, .pll[4] = 0x00,
1314 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
1324 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1334 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xB0, .pll[3] = 0x00, .pll[4] = 0x00,
1344 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xCE, .pll[3] = 0x00, .pll[4] = 0x00,
1354 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
1364 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x66, .pll[3] = 0x00, .pll[4] = 0x00,
1374 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x72, .pll[3] = 0x00, .pll[4] = 0x00,
1384 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1394 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7C, .pll[3] = 0x00, .pll[4] = 0x00,
1404 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x84, .pll[3] = 0x00, .pll[4] = 0x00,
1414 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x92, .pll[3] = 0x00, .pll[4] = 0x00,
1424 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0x98, .pll[3] = 0x00, .pll[4] = 0x00,
1434 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBC, .pll[3] = 0x00, .pll[4] = 0x00,
1444 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
1454 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
1464 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD6, .pll[3] = 0x00, .pll[4] = 0x00,
1474 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6C, .pll[3] = 0x00, .pll[4] = 0x00,
1484 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x70, .pll[3] = 0x00, .pll[4] = 0x00,
1494 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x78, .pll[3] = 0x00, .pll[4] = 0x00,
1504 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1514 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x80, .pll[3] = 0x00, .pll[4] = 0x00,
1524 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x88, .pll[3] = 0x00, .pll[4] = 0x00,
1534 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x8C, .pll[3] = 0x00, .pll[4] = 0x00,
1544 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1554 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1564 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBA, .pll[3] = 0x00, .pll[4] = 0x00,
1574 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xDA, .pll[3] = 0x00, .pll[4] = 0x00,
1584 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x68, .pll[3] = 0x00, .pll[4] = 0x00,
1594 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6A, .pll[3] = 0x00, .pll[4] = 0x00,
1604 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1614 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1624 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
1634 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xE2, .pll[3] = 0x00, .pll[4] = 0x00,
1644 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1654 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1979 if (clock == tables[i]->clock) in intel_c10_phy_check_hdmi_link_rate()
1999 MISSING_CASE(encoder->type); in intel_c10pll_tables_get()
2006 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_c10pll_update_pll()
2007 struct intel_cx0pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll; in intel_c10pll_update_pll()
2014 pll_state->ssc_enabled = in intel_c10pll_update_pll()
2015 (intel_dp->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5); in intel_c10pll_update_pll()
2019 if (pll_state->ssc_enabled) in intel_c10pll_update_pll()
2022 drm_WARN_ON(&i915->drm, ARRAY_SIZE(pll_state->c10.pll) < 9); in intel_c10pll_update_pll()
2023 for (i = 4; i < 9; i++) in intel_c10pll_update_pll()
2024 pll_state->c10.pll[i] = 0; in intel_c10pll_update_pll()
2035 return -EINVAL; in intel_c10pll_calc_state()
2038 if (crtc_state->port_clock == tables[i]->clock) { in intel_c10pll_calc_state()
2039 crtc_state->dpll_hw_state.cx0pll.c10 = *tables[i]; in intel_c10pll_calc_state()
2041 crtc_state->dpll_hw_state.cx0pll.use_c10 = true; in intel_c10pll_calc_state()
2047 return -EINVAL; in intel_c10pll_calc_state()
2053 u8 lane = INTEL_CX0_LANE0; in intel_c10pll_readout_hw_state() local
2063 intel_cx0_rmw(encoder, lane, PHY_C10_VDR_CONTROL(1), in intel_c10pll_readout_hw_state()
2067 for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) in intel_c10pll_readout_hw_state()
2068 pll_state->pll[i] = intel_cx0_read(encoder, lane, PHY_C10_VDR_PLL(i)); in intel_c10pll_readout_hw_state()
2070 pll_state->cmn = intel_cx0_read(encoder, lane, PHY_C10_VDR_CMN(0)); in intel_c10pll_readout_hw_state()
2071 pll_state->tx = intel_cx0_read(encoder, lane, PHY_C10_VDR_TX(0)); in intel_c10pll_readout_hw_state()
2080 const struct intel_c10pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c10; in intel_c10_pll_program()
2095 /* Program the pll values only for the master lane */ in intel_c10_pll_program()
2096 for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) in intel_c10_pll_program()
2098 pll_state->pll[i], in intel_c10_pll_program()
2099 (i % 4) ? MB_WRITE_UNCOMMITTED : MB_WRITE_COMMITTED); in intel_c10_pll_program()
2101 intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CMN(0), pll_state->cmn, MB_WRITE_COMMITTED); in intel_c10_pll_program()
2102 intel_cx0_write(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_TX(0), pll_state->tx, MB_WRITE_COMMITTED); in intel_c10_pll_program()
2117 fracen = hw_state->pll[0] & C10_PLL0_FRACEN; in intel_c10pll_dump_hw_state()
2118 drm_dbg_kms(&i915->drm, "c10pll_hw_state: fracen: %s, ", in intel_c10pll_dump_hw_state()
2122 frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11]; in intel_c10pll_dump_hw_state()
2123 frac_rem = hw_state->pll[14] << 8 | hw_state->pll[13]; in intel_c10pll_dump_hw_state()
2124 frac_den = hw_state->pll[10] << 8 | hw_state->pll[9]; in intel_c10pll_dump_hw_state()
2125 drm_dbg_kms(&i915->drm, "quot: %u, rem: %u, den: %u,\n", in intel_c10pll_dump_hw_state()
2129 multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, hw_state->pll[3]) << 8 | in intel_c10pll_dump_hw_state()
2130 hw_state->pll[2]) / 2 + 16; in intel_c10pll_dump_hw_state()
2131 tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, hw_state->pll[15]); in intel_c10pll_dump_hw_state()
2132 drm_dbg_kms(&i915->drm, in intel_c10pll_dump_hw_state()
2135 drm_dbg_kms(&i915->drm, "c10pll_rawhw_state:"); in intel_c10pll_dump_hw_state()
2136 drm_dbg_kms(&i915->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx, hw_state->cmn); in intel_c10pll_dump_hw_state()
2138 BUILD_BUG_ON(ARRAY_SIZE(hw_state->pll) % 4); in intel_c10pll_dump_hw_state()
2139 for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4) in intel_c10pll_dump_hw_state()
2140 drm_dbg_kms(&i915->drm, "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n", in intel_c10pll_dump_hw_state()
2141 i, hw_state->pll[i], i + 1, hw_state->pll[i + 1], in intel_c10pll_dump_hw_state()
2142 i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]); in intel_c10pll_dump_hw_state()
2159 return -EINVAL; in intel_c20_compute_hdmi_tmds_pll()
2165 multiplier = div64_u64((vco_freq << 28), (REFCLK_38_4_MHZ >> 4)); in intel_c20_compute_hdmi_tmds_pll()
2183 pll_state->clock = pixel_clock; in intel_c20_compute_hdmi_tmds_pll()
2184 pll_state->tx[0] = 0xbe88; in intel_c20_compute_hdmi_tmds_pll()
2185 pll_state->tx[1] = 0x9800; in intel_c20_compute_hdmi_tmds_pll()
2186 pll_state->tx[2] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2187 pll_state->cmn[0] = 0x0500; in intel_c20_compute_hdmi_tmds_pll()
2188 pll_state->cmn[1] = 0x0005; in intel_c20_compute_hdmi_tmds_pll()
2189 pll_state->cmn[2] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2190 pll_state->cmn[3] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2191 pll_state->mpllb[0] = (MPLL_TX_CLK_DIV(mpll_tx_clk_div) | in intel_c20_compute_hdmi_tmds_pll()
2193 pll_state->mpllb[1] = (CAL_DAC_CODE(CAL_DAC_CODE_31) | in intel_c20_compute_hdmi_tmds_pll()
2196 pll_state->mpllb[2] = (MPLLB_ANA_FREQ_VCO(mpllb_ana_freq_vco) | in intel_c20_compute_hdmi_tmds_pll()
2199 pll_state->mpllb[3] = (V2I(V2I_2) | in intel_c20_compute_hdmi_tmds_pll()
2202 pll_state->mpllb[4] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2203 pll_state->mpllb[5] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2204 pll_state->mpllb[6] = (C20_MPLLB_FRACEN | SSC_UP_SPREAD); in intel_c20_compute_hdmi_tmds_pll()
2205 pll_state->mpllb[7] = MPLL_FRACN_DEN; in intel_c20_compute_hdmi_tmds_pll()
2206 pll_state->mpllb[8] = mpll_fracn_quot; in intel_c20_compute_hdmi_tmds_pll()
2207 pll_state->mpllb[9] = mpll_fracn_rem; in intel_c20_compute_hdmi_tmds_pll()
2208 pll_state->mpllb[10] = HDMI_DIV(HDMI_DIV_1); in intel_c20_compute_hdmi_tmds_pll()
2219 if (clock == tables[i]->clock) in intel_c20_phy_check_hdmi_link_rate()
2233 if (intel_encoder_is_c10phy(&dig_port->base)) in intel_cx0_phy_check_hdmi_link_rate()
2242 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_c20_pll_tables_get()
2257 MISSING_CASE(encoder->type); in intel_c20_pll_tables_get()
2269 if (intel_c20_compute_hdmi_tmds_pll(crtc_state->port_clock, in intel_c20pll_calc_state()
2270 &crtc_state->dpll_hw_state.cx0pll.c20) == 0) in intel_c20pll_calc_state()
2276 return -EINVAL; in intel_c20pll_calc_state()
2279 if (crtc_state->port_clock == tables[i]->clock) { in intel_c20pll_calc_state()
2280 crtc_state->dpll_hw_state.cx0pll.c20 = *tables[i]; in intel_c20pll_calc_state()
2281 crtc_state->dpll_hw_state.cx0pll.use_c10 = false; in intel_c20pll_calc_state()
2286 return -EINVAL; in intel_c20pll_calc_state()
2299 return state->tx[0] & C20_PHY_USE_MPLLB; in intel_c20phy_use_mpllb()
2312 unsigned int tx_rate = REG_FIELD_GET(C20_PHY_TX_RATE, pll_state->tx[0]); in intel_c20pll_calc_port_clock()
2316 frac_en = REG_FIELD_GET(C20_MPLLB_FRACEN, pll_state->mpllb[6]); in intel_c20pll_calc_port_clock()
2317 frac_quot = pll_state->mpllb[8]; in intel_c20pll_calc_port_clock()
2318 frac_rem = pll_state->mpllb[9]; in intel_c20pll_calc_port_clock()
2319 frac_den = pll_state->mpllb[7]; in intel_c20pll_calc_port_clock()
2320 multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mpllb[0]); in intel_c20pll_calc_port_clock()
2321 tx_clk_div = REG_FIELD_GET(C20_MPLLB_TX_CLK_DIV_MASK, pll_state->mpllb[0]); in intel_c20pll_calc_port_clock()
2322 ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mpllb[6]); in intel_c20pll_calc_port_clock()
2326 frac_en = REG_FIELD_GET(C20_MPLLA_FRACEN, pll_state->mplla[6]); in intel_c20pll_calc_port_clock()
2327 frac_quot = pll_state->mplla[8]; in intel_c20pll_calc_port_clock()
2328 frac_rem = pll_state->mplla[9]; in intel_c20pll_calc_port_clock()
2329 frac_den = pll_state->mplla[7]; in intel_c20pll_calc_port_clock()
2330 multiplier = REG_FIELD_GET(C20_MULTIPLIER_MASK, pll_state->mplla[0]); in intel_c20pll_calc_port_clock()
2331 tx_clk_div = REG_FIELD_GET(C20_MPLLA_TX_CLK_DIV_MASK, pll_state->mplla[1]); in intel_c20pll_calc_port_clock()
2332 ref_clk_mpllb_div = REG_FIELD_GET(C20_REF_CLK_MPLLB_DIV_MASK, pll_state->mplla[6]); in intel_c20pll_calc_port_clock()
2333 fb_clk_div4_en = REG_FIELD_GET(C20_FB_CLK_DIV4_EN, pll_state->mplla[0]); in intel_c20pll_calc_port_clock()
2342 vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(ref, (multiplier << (17 - 2)) + frac) >> 17, 10); in intel_c20pll_calc_port_clock()
2353 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_c20pll_readout_hw_state()
2361 for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { in intel_c20pll_readout_hw_state()
2363 pll_state->tx[i] = intel_c20_sram_read(encoder, in intel_c20pll_readout_hw_state()
2367 pll_state->tx[i] = intel_c20_sram_read(encoder, in intel_c20pll_readout_hw_state()
2373 for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { in intel_c20pll_readout_hw_state()
2375 pll_state->cmn[i] = intel_c20_sram_read(encoder, in intel_c20pll_readout_hw_state()
2379 pll_state->cmn[i] = intel_c20_sram_read(encoder, in intel_c20pll_readout_hw_state()
2386 for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { in intel_c20pll_readout_hw_state()
2388 pll_state->mpllb[i] = intel_c20_sram_read(encoder, in intel_c20pll_readout_hw_state()
2392 pll_state->mpllb[i] = intel_c20_sram_read(encoder, in intel_c20pll_readout_hw_state()
2398 for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { in intel_c20pll_readout_hw_state()
2400 pll_state->mplla[i] = intel_c20_sram_read(encoder, in intel_c20pll_readout_hw_state()
2404 pll_state->mplla[i] = intel_c20_sram_read(encoder, in intel_c20pll_readout_hw_state()
2410 pll_state->clock = intel_c20pll_calc_port_clock(encoder, pll_state); in intel_c20pll_readout_hw_state()
2420 drm_dbg_kms(&i915->drm, "c20pll_hw_state:\n"); in intel_c20pll_dump_hw_state()
2421 drm_dbg_kms(&i915->drm, "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n", in intel_c20pll_dump_hw_state()
2422 hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]); in intel_c20pll_dump_hw_state()
2423 drm_dbg_kms(&i915->drm, "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n", in intel_c20pll_dump_hw_state()
2424 hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]); in intel_c20pll_dump_hw_state()
2427 for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++) in intel_c20pll_dump_hw_state()
2428 drm_dbg_kms(&i915->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]); in intel_c20pll_dump_hw_state()
2430 for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++) in intel_c20pll_dump_hw_state()
2431 drm_dbg_kms(&i915->drm, "mplla[%d] = 0x%.4x\n", i, hw_state->mplla[i]); in intel_c20pll_dump_hw_state()
2438 if (hw_state->use_c10) in intel_cx0pll_dump_hw_state()
2439 intel_c10pll_dump_hw_state(i915, &hw_state->c10); in intel_cx0pll_dump_hw_state()
2441 intel_c20pll_dump_hw_state(i915, &hw_state->c20); in intel_cx0pll_dump_hw_state()
2447 case 162000: /* 1.62 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2449 case 270000: /* 2.7 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2453 case 810000: /* 8.1 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2456 return 4; in intel_c20_get_dp_rate()
2527 /* TODO: optimize re-calibration in legacy mode */ in intel_c20_protocol_switch_valid()
2545 const struct intel_c20pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c20; in intel_c20_pll_program()
2548 u32 clock = crtc_state->port_clock; in intel_c20_pll_program()
2560 * the lane #0 MPLLB CAL_DONE_BANK DP2.0 10G and 20G rates enable MPLLA. in intel_c20_pll_program()
2564 for (i = 0; i < 4; i++) in intel_c20_pll_program()
2571 for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { in intel_c20_pll_program()
2575 pll_state->tx[i]); in intel_c20_pll_program()
2579 pll_state->tx[i]); in intel_c20_pll_program()
2583 for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { in intel_c20_pll_program()
2587 pll_state->cmn[i]); in intel_c20_pll_program()
2591 pll_state->cmn[i]); in intel_c20_pll_program()
2596 for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { in intel_c20_pll_program()
2600 pll_state->mpllb[i]); in intel_c20_pll_program()
2604 pll_state->mpllb[i]); in intel_c20_pll_program()
2607 for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { in intel_c20_pll_program()
2611 pll_state->mplla[i]); in intel_c20_pll_program()
2615 pll_state->mplla[i]); in intel_c20_pll_program()
2619 /* 4. Program custom width to match the link protocol */ in intel_c20_pll_program()
2657 if (pll_state->pll[0] & C10_PLL0_FRACEN) { in intel_c10pll_calc_port_clock()
2658 frac_quot = pll_state->pll[12] << 8 | pll_state->pll[11]; in intel_c10pll_calc_port_clock()
2659 frac_rem = pll_state->pll[14] << 8 | pll_state->pll[13]; in intel_c10pll_calc_port_clock()
2660 frac_den = pll_state->pll[10] << 8 | pll_state->pll[9]; in intel_c10pll_calc_port_clock()
2663 multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 | in intel_c10pll_calc_port_clock()
2664 pll_state->pll[2]) / 2 + 16; in intel_c10pll_calc_port_clock()
2666 tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, pll_state->pll[15]); in intel_c10pll_calc_port_clock()
2667 hdmi_div = REG_FIELD_GET8(C10_PLL15_HDMIDIV_MASK, pll_state->pll[15]); in intel_c10pll_calc_port_clock()
2681 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_program_port_clock_ctl()
2684 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port), in intel_program_port_clock_ctl()
2694 is_hdmi_frl(crtc_state->port_clock)) in intel_program_port_clock_ctl()
2701 if (crtc_state->port_clock == 1000000 || crtc_state->port_clock == 2000000) in intel_program_port_clock_ctl()
2702 val |= crtc_state->dpll_hw_state.cx0pll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLA : 0; in intel_program_port_clock_ctl()
2704 val |= crtc_state->dpll_hw_state.cx0pll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0; in intel_program_port_clock_ctl()
2706 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), in intel_program_port_clock_ctl()
2715 int lane = 0; in intel_cx0_get_powerdown_update() local
2717 for_each_cx0_lane_in_mask(lane_mask, lane) in intel_cx0_get_powerdown_update()
2718 val |= XELPDP_LANE_POWERDOWN_UPDATE(lane); in intel_cx0_get_powerdown_update()
2726 int lane = 0; in intel_cx0_get_powerdown_state() local
2728 for_each_cx0_lane_in_mask(lane_mask, lane) in intel_cx0_get_powerdown_state()
2729 val |= XELPDP_LANE_POWERDOWN_NEW_STATE(lane, state); in intel_cx0_get_powerdown_state()
2737 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_powerdown_change_sequence()
2738 enum port port = encoder->port; in intel_cx0_powerdown_change_sequence()
2741 int lane; in intel_cx0_powerdown_change_sequence() local
2748 for_each_cx0_lane_in_mask(lane_mask, lane) in intel_cx0_powerdown_change_sequence()
2749 if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane), in intel_cx0_powerdown_change_sequence()
2752 drm_dbg_kms(&i915->drm, in intel_cx0_powerdown_change_sequence()
2755 intel_cx0_bus_reset(encoder, lane); in intel_cx0_powerdown_change_sequence()
2766 drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n", in intel_cx0_powerdown_change_sequence()
2772 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_setup_powerdown()
2773 enum port port = encoder->port; in intel_cx0_setup_powerdown()
2788 int lane = 0; in intel_cx0_get_pclk_refclk_request() local
2790 for_each_cx0_lane_in_mask(lane_mask, lane) in intel_cx0_get_pclk_refclk_request()
2791 val |= XELPDP_LANE_PCLK_REFCLK_REQUEST(lane); in intel_cx0_get_pclk_refclk_request()
2799 int lane = 0; in intel_cx0_get_pclk_refclk_ack() local
2801 for_each_cx0_lane_in_mask(lane_mask, lane) in intel_cx0_get_pclk_refclk_ack()
2802 val |= XELPDP_LANE_PCLK_REFCLK_ACK(lane); in intel_cx0_get_pclk_refclk_ack()
2810 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_lane_reset()
2811 enum port port = encoder->port; in intel_cx0_phy_lane_reset()
2827 drm_warn(&i915->drm, "PHY %c failed to bring out of SOC reset after %dus.\n", in intel_cx0_phy_lane_reset()
2836 drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n", in intel_cx0_phy_lane_reset()
2847 drm_warn(&i915->drm, "PHY %c failed to request refclk after %dus.\n", in intel_cx0_phy_lane_reset()
2859 drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dms.\n", in intel_cx0_phy_lane_reset()
2888 for (i = 0; i < 4; i++) { in intel_cx0_program_phy_lane()
2911 int lane = 0; in intel_cx0_get_pclk_pll_request() local
2913 for_each_cx0_lane_in_mask(lane_mask, lane) in intel_cx0_get_pclk_pll_request()
2914 val |= XELPDP_LANE_PCLK_PLL_REQUEST(lane); in intel_cx0_get_pclk_pll_request()
2922 int lane = 0; in intel_cx0_get_pclk_pll_ack() local
2924 for_each_cx0_lane_in_mask(lane_mask, lane) in intel_cx0_get_pclk_pll_ack()
2925 val |= XELPDP_LANE_PCLK_PLL_ACK(lane); in intel_cx0_get_pclk_pll_ack()
2933 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0pll_enable()
2936 bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL; in intel_cx0pll_enable()
2952 * TODO: For DP alt mode use only one lane. in intel_cx0pll_enable()
2958 * 4. Program PORT_MSGBUS_TIMER register's Message Bus Timer field to 0xA000. in intel_cx0pll_enable()
2970 * 6. Program the enabled and disabled owned PHY lane in intel_cx0pll_enable()
2973 intel_cx0_program_phy_lane(i915, encoder, crtc_state->lane_count, lane_reversal); in intel_cx0pll_enable()
2976 * 7. Follow the Display Voltage Frequency Switching - Sequence in intel_cx0pll_enable()
2984 intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), in intel_cx0pll_enable()
2985 crtc_state->port_clock); in intel_cx0pll_enable()
2989 * LN<Lane for maxPCLK> to "1" to enable PLL. in intel_cx0pll_enable()
2991 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), in intel_cx0pll_enable()
2995 /* 10. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */ in intel_cx0pll_enable()
2996 if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), in intel_cx0pll_enable()
3000 drm_warn(&i915->drm, "Port %c PLL not locked after %dus.\n", in intel_cx0pll_enable()
3008 /* TODO: enable TBT-ALT mode */ in intel_cx0pll_enable()
3014 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_mtl_tbt_calc_port_clock()
3016 u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port)); in intel_mtl_tbt_calc_port_clock()
3020 drm_WARN_ON(&i915->drm, !(val & XELPDP_FORWARD_CLOCK_UNGATE)); in intel_mtl_tbt_calc_port_clock()
3021 drm_WARN_ON(&i915->drm, !(val & XELPDP_TBT_CLOCK_REQUEST)); in intel_mtl_tbt_calc_port_clock()
3022 drm_WARN_ON(&i915->drm, !(val & XELPDP_TBT_CLOCK_ACK)); in intel_mtl_tbt_calc_port_clock()
3059 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_mtl_tbt_pll_enable()
3067 val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(i915, crtc_state->port_clock)); in intel_mtl_tbt_pll_enable()
3069 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), in intel_mtl_tbt_pll_enable()
3073 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port)); in intel_mtl_tbt_pll_enable()
3076 * 3. Follow the Display Voltage Frequency Switching - Sequence in intel_mtl_tbt_pll_enable()
3081 * 4. Set PORT_CLOCK_CTL register TBT CLOCK Request to "1" to enable PLL. in intel_mtl_tbt_pll_enable()
3084 intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), val); in intel_mtl_tbt_pll_enable()
3087 if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), in intel_mtl_tbt_pll_enable()
3091 drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not locked after 100us.\n", in intel_mtl_tbt_pll_enable()
3092 encoder->base.base.id, encoder->base.name, phy_name(phy)); in intel_mtl_tbt_pll_enable()
3103 intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), in intel_mtl_tbt_pll_enable()
3104 crtc_state->port_clock); in intel_mtl_tbt_pll_enable()
3120 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in cx0_power_control_disable_val()
3125 if (IS_BATTLEMAGE(i915) && encoder->port == PORT_A) in cx0_power_control_disable_val()
3133 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0pll_disable()
3137 /* 1. Change owned PHY lane power to Disable state. */ in intel_cx0pll_disable()
3147 * 3. Set PORT_CLOCK_CTL register PCLK PLL Request LN<Lane for maxPCLK> in intel_cx0pll_disable()
3150 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), in intel_cx0pll_disable()
3154 /* 4. Program DDI_CLK_VALFREQ to 0. */ in intel_cx0pll_disable()
3155 intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0); in intel_cx0pll_disable()
3158 * 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0". in intel_cx0pll_disable()
3160 if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), in intel_cx0pll_disable()
3164 drm_warn(&i915->drm, "Port %c PLL not unlocked after %dus.\n", in intel_cx0pll_disable()
3173 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), in intel_cx0pll_disable()
3175 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), in intel_cx0pll_disable()
3183 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_mtl_tbt_pll_disable()
3194 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), in intel_mtl_tbt_pll_disable()
3198 if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), in intel_mtl_tbt_pll_disable()
3200 drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n", in intel_mtl_tbt_pll_disable()
3201 encoder->base.base.id, encoder->base.name, phy_name(phy)); in intel_mtl_tbt_pll_disable()
3204 * 4. Follow the Display Voltage Frequency Switching Sequence After in intel_mtl_tbt_pll_disable()
3211 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), in intel_mtl_tbt_pll_disable()
3216 intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0); in intel_mtl_tbt_pll_disable()
3233 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_mtl_port_pll_type()
3238 u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port)); in intel_mtl_port_pll_type()
3253 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_c10pll_state_verify()
3254 const struct intel_c10pll_state *mpllb_sw_state = &state->dpll_hw_state.cx0pll.c10; in intel_c10pll_state_verify()
3257 for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) { in intel_c10pll_state_verify()
3258 u8 expected = mpllb_sw_state->pll[i]; in intel_c10pll_state_verify()
3260 I915_STATE_WARN(i915, mpllb_hw_state->pll[i] != expected, in intel_c10pll_state_verify()
3262 crtc->base.base.id, crtc->base.name, i, in intel_c10pll_state_verify()
3263 expected, mpllb_hw_state->pll[i]); in intel_c10pll_state_verify()
3266 I915_STATE_WARN(i915, mpllb_hw_state->tx != mpllb_sw_state->tx, in intel_c10pll_state_verify()
3268 crtc->base.base.id, crtc->base.name, in intel_c10pll_state_verify()
3269 mpllb_sw_state->tx, mpllb_hw_state->tx); in intel_c10pll_state_verify()
3271 I915_STATE_WARN(i915, mpllb_hw_state->cmn != mpllb_sw_state->cmn, in intel_c10pll_state_verify()
3273 crtc->base.base.id, crtc->base.name, in intel_c10pll_state_verify()
3274 mpllb_sw_state->cmn, mpllb_hw_state->cmn); in intel_c10pll_state_verify()
3280 pll_state->use_c10 = false; in intel_cx0pll_readout_hw_state()
3282 pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)); in intel_cx0pll_readout_hw_state()
3283 if (pll_state->tbt_mode) in intel_cx0pll_readout_hw_state()
3287 intel_c10pll_readout_hw_state(encoder, &pll_state->c10); in intel_cx0pll_readout_hw_state()
3288 pll_state->use_c10 = true; in intel_cx0pll_readout_hw_state()
3290 intel_c20pll_readout_hw_state(encoder, &pll_state->c20); in intel_cx0pll_readout_hw_state()
3297 if (a->tx != b->tx) in mtl_compare_hw_state_c10()
3300 if (a->cmn != b->cmn) in mtl_compare_hw_state_c10()
3303 if (memcmp(&a->pll, &b->pll, sizeof(a->pll)) != 0) in mtl_compare_hw_state_c10()
3312 if (memcmp(&a->tx, &b->tx, sizeof(a->tx)) != 0) in mtl_compare_hw_state_c20()
3315 if (memcmp(&a->cmn, &b->cmn, sizeof(a->cmn)) != 0) in mtl_compare_hw_state_c20()
3318 if (a->tx[0] & C20_PHY_USE_MPLLB) { in mtl_compare_hw_state_c20()
3319 if (memcmp(&a->mpllb, &b->mpllb, sizeof(a->mpllb)) != 0) in mtl_compare_hw_state_c20()
3322 if (memcmp(&a->mplla, &b->mplla, sizeof(a->mplla)) != 0) in mtl_compare_hw_state_c20()
3332 if (a->tbt_mode || b->tbt_mode) in intel_cx0pll_compare_hw_state()
3335 if (a->use_c10 != b->use_c10) in intel_cx0pll_compare_hw_state()
3338 if (a->use_c10) in intel_cx0pll_compare_hw_state()
3339 return mtl_compare_hw_state_c10(&a->c10, in intel_cx0pll_compare_hw_state()
3340 &b->c10); in intel_cx0pll_compare_hw_state()
3342 return mtl_compare_hw_state_c20(&a->c20, in intel_cx0pll_compare_hw_state()
3343 &b->c20); in intel_cx0pll_compare_hw_state()
3350 return intel_c10pll_calc_port_clock(encoder, &pll_state->c10); in intel_cx0pll_calc_port_clock()
3352 return intel_c20pll_calc_port_clock(encoder, &pll_state->c20); in intel_cx0pll_calc_port_clock()
3360 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_c20pll_state_verify()
3361 const struct intel_c20pll_state *mpll_sw_state = &state->dpll_hw_state.cx0pll.c20; in intel_c20pll_state_verify()
3367 I915_STATE_WARN(i915, mpll_hw_state->clock != clock, in intel_c20pll_state_verify()
3369 crtc->base.base.id, crtc->base.name, in intel_c20pll_state_verify()
3370 mpll_sw_state->clock, mpll_hw_state->clock); in intel_c20pll_state_verify()
3374 crtc->base.base.id, crtc->base.name, in intel_c20pll_state_verify()
3378 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mpllb); i++) { in intel_c20pll_state_verify()
3379 I915_STATE_WARN(i915, mpll_hw_state->mpllb[i] != mpll_sw_state->mpllb[i], in intel_c20pll_state_verify()
3381 crtc->base.base.id, crtc->base.name, i, in intel_c20pll_state_verify()
3382 mpll_sw_state->mpllb[i], mpll_hw_state->mpllb[i]); in intel_c20pll_state_verify()
3385 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->mplla); i++) { in intel_c20pll_state_verify()
3386 I915_STATE_WARN(i915, mpll_hw_state->mplla[i] != mpll_sw_state->mplla[i], in intel_c20pll_state_verify()
3388 crtc->base.base.id, crtc->base.name, i, in intel_c20pll_state_verify()
3389 mpll_sw_state->mplla[i], mpll_hw_state->mplla[i]); in intel_c20pll_state_verify()
3393 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->tx); i++) { in intel_c20pll_state_verify()
3394 I915_STATE_WARN(i915, mpll_hw_state->tx[i] != mpll_sw_state->tx[i], in intel_c20pll_state_verify()
3396 crtc->base.base.id, crtc->base.name, i, in intel_c20pll_state_verify()
3397 mpll_sw_state->tx[i], mpll_hw_state->tx[i]); in intel_c20pll_state_verify()
3400 for (i = 0; i < ARRAY_SIZE(mpll_sw_state->cmn); i++) { in intel_c20pll_state_verify()
3401 I915_STATE_WARN(i915, mpll_hw_state->cmn[i] != mpll_sw_state->cmn[i], in intel_c20pll_state_verify()
3403 crtc->base.base.id, crtc->base.name, i, in intel_c20pll_state_verify()
3404 mpll_sw_state->cmn[i], mpll_hw_state->cmn[i]); in intel_c20pll_state_verify()
3411 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_cx0pll_state_verify()
3420 if (!new_crtc_state->hw.active) in intel_cx0pll_state_verify()