Lines Matching +full:3 +full:gbps
238 /* 3 tries is assumed to be enough to read successfully */ in __intel_cx0_read()
239 for (i = 0; i < 3; i++) { in __intel_cx0_read()
327 /* 3 tries is assumed to be enough to write successfully */ in __intel_cx0_write()
328 for (i = 0; i < 3; i++) { in __intel_cx0_write()
455 intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CMN(3), in intel_cx0_phy_set_signal_levels()
514 .pll[3] = 0x1,
540 .pll[3] = 0x1,
566 .pll[3] = 0x1,
592 .pll[3] = 0x0,
618 .pll[3] = 0x1,
644 .pll[3] = 0x1,
670 .pll[3] = 0,
696 .pll[3] = 0x1,
722 .pll[3] = 0x1,
865 .clock = 1000000, /* 10 Gbps */
889 .clock = 1350000, /* 13.5 Gbps */
914 .clock = 2000000, /* 20 Gbps */
1091 .clock = 1350000, /* 13.5 Gbps */
1136 .pll[3] = 0,
1162 .pll[3] = 0,
1188 .pll[3] = 0,
1214 .pll[3] = 0,
1240 .pll[3] = 0,
1264 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
1274 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xCC, .pll[3] = 0x00, .pll[4] = 0x00,
1284 .pll[0] = 0x04, .pll[1] = 0x00, .pll[2] = 0xDC, .pll[3] = 0x00, .pll[4] = 0x00,
1294 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x62, .pll[3] = 0x00, .pll[4] = 0x00,
1304 .pll[0] = 0xC4, .pll[1] = 0x00, .pll[2] = 0x76, .pll[3] = 0x00, .pll[4] = 0x00,
1314 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
1324 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1334 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xB0, .pll[3] = 0x00, .pll[4] = 0x00,
1344 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xCE, .pll[3] = 0x00, .pll[4] = 0x00,
1354 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
1364 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x66, .pll[3] = 0x00, .pll[4] = 0x00,
1374 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x72, .pll[3] = 0x00, .pll[4] = 0x00,
1384 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1394 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7C, .pll[3] = 0x00, .pll[4] = 0x00,
1404 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x84, .pll[3] = 0x00, .pll[4] = 0x00,
1414 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x92, .pll[3] = 0x00, .pll[4] = 0x00,
1424 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0x98, .pll[3] = 0x00, .pll[4] = 0x00,
1434 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBC, .pll[3] = 0x00, .pll[4] = 0x00,
1444 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xC0, .pll[3] = 0x00, .pll[4] = 0x00,
1454 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD0, .pll[3] = 0x00, .pll[4] = 0x00,
1464 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xD6, .pll[3] = 0x00, .pll[4] = 0x00,
1474 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6C, .pll[3] = 0x00, .pll[4] = 0x00,
1484 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x70, .pll[3] = 0x00, .pll[4] = 0x00,
1494 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x78, .pll[3] = 0x00, .pll[4] = 0x00,
1504 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1514 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x80, .pll[3] = 0x00, .pll[4] = 0x00,
1524 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x88, .pll[3] = 0x00, .pll[4] = 0x00,
1534 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x8C, .pll[3] = 0x00, .pll[4] = 0x00,
1544 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1554 .pll[0] = 0x74, .pll[1] = 0x00, .pll[2] = 0xAE, .pll[3] = 0x00, .pll[4] = 0x00,
1564 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xBA, .pll[3] = 0x00, .pll[4] = 0x00,
1574 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xDA, .pll[3] = 0x00, .pll[4] = 0x00,
1584 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x68, .pll[3] = 0x00, .pll[4] = 0x00,
1594 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x6A, .pll[3] = 0x00, .pll[4] = 0x00,
1604 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1614 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1624 .pll[0] = 0xB4, .pll[1] = 0x00, .pll[2] = 0x86, .pll[3] = 0x00, .pll[4] = 0x00,
1634 .pll[0] = 0x34, .pll[1] = 0x00, .pll[2] = 0xE2, .pll[3] = 0x00, .pll[4] = 0x00,
1644 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
1654 .pll[0] = 0xF4, .pll[1] = 0x00, .pll[2] = 0x7A, .pll[3] = 0x00, .pll[4] = 0x00,
2129 multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, hw_state->pll[3]) << 8 | in intel_c10pll_dump_hw_state()
2142 i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]); in intel_c10pll_dump_hw_state()
2190 pll_state->cmn[3] = 0x0000; in intel_c20_compute_hdmi_tmds_pll()
2199 pll_state->mpllb[3] = (V2I(V2I_2) | in intel_c20_compute_hdmi_tmds_pll()
2423 drm_dbg_kms(&i915->drm, "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n", in intel_c20pll_dump_hw_state()
2424 hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]); in intel_c20pll_dump_hw_state()
2447 case 162000: /* 1.62 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2449 case 270000: /* 2.7 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2451 case 540000: /* 5.4 Gbps DP 1.4 */ in intel_c20_get_dp_rate()
2453 case 810000: /* 8.1 Gbps DP1.4 */ in intel_c20_get_dp_rate()
2454 return 3; in intel_c20_get_dp_rate()
2455 case 216000: /* 2.16 Gbps eDP */ in intel_c20_get_dp_rate()
2457 case 243000: /* 2.43 Gbps eDP */ in intel_c20_get_dp_rate()
2459 case 324000: /* 3.24 Gbps eDP */ in intel_c20_get_dp_rate()
2461 case 432000: /* 4.32 Gbps eDP */ in intel_c20_get_dp_rate()
2463 case 1000000: /* 10 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2465 case 1350000: /* 13.5 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2467 case 2000000: /* 20 Gbps DP2.0 */ in intel_c20_get_dp_rate()
2469 case 648000: /* 6.48 Gbps eDP*/ in intel_c20_get_dp_rate()
2471 case 675000: /* 6.75 Gbps eDP*/ in intel_c20_get_dp_rate()
2485 case 300000: /* 3 Gbps */ in intel_c20_get_hdmi_rate()
2486 case 600000: /* 6 Gbps */ in intel_c20_get_hdmi_rate()
2487 case 1200000: /* 12 Gbps */ in intel_c20_get_hdmi_rate()
2489 case 800000: /* 8 Gbps */ in intel_c20_get_hdmi_rate()
2491 case 1000000: /* 10 Gbps */ in intel_c20_get_hdmi_rate()
2492 return 3; in intel_c20_get_hdmi_rate()
2511 case 300000: /* 3 Gbps */ in is_hdmi_frl()
2512 case 600000: /* 6 Gbps */ in is_hdmi_frl()
2513 case 800000: /* 8 Gbps */ in is_hdmi_frl()
2514 case 1000000: /* 10 Gbps */ in is_hdmi_frl()
2515 case 1200000: /* 12 Gbps */ in is_hdmi_frl()
2569 /* 3. Write SRAM configuration context. If A in use, write configuration to B context */ in intel_c20_pll_program()
2663 multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, pll_state->pll[3]) << 8 | in intel_c10pll_calc_port_clock()
2879 disables = REG_GENMASK8(3, 0) >> lane_count; in intel_cx0_program_phy_lane()
2881 disables = REG_GENMASK8(3, 0) << lane_count; in intel_cx0_program_phy_lane()
2951 * 3. Change Phy power state to Ready. in intel_cx0pll_enable()
3076 * 3. Follow the Display Voltage Frequency Switching - Sequence in intel_mtl_tbt_pll_enable()
3147 * 3. Set PORT_CLOCK_CTL register PCLK PLL Request LN<Lane for maxPCLK> in intel_cx0pll_disable()
3197 /* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */ in intel_mtl_tbt_pll_disable()