Lines Matching +full:ddc +full:- +full:rx
2 * Copyright © 2006-2007 Intel Corporation
103 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_crt_get_hw_state()
109 encoder->power_domain); in intel_crt_get_hw_state()
113 ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe); in intel_crt_get_hw_state()
115 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); in intel_crt_get_hw_state()
122 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_crt_get_flags()
126 tmp = intel_de_read(dev_priv, crt->adpa_reg); in intel_crt_get_flags()
144 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG); in intel_crt_get_config()
146 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); in intel_crt_get_config()
148 pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock; in intel_crt_get_config()
158 pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | in hsw_crt_get_config()
162 pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder); in hsw_crt_get_config()
171 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_crt_set_dpms()
173 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_crt_set_dpms()
174 const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; in intel_crt_set_dpms()
182 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) in intel_crt_set_dpms()
184 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) in intel_crt_set_dpms()
191 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe); in intel_crt_set_dpms()
193 adpa |= ADPA_PIPE_SEL(crtc->pipe); in intel_crt_set_dpms()
196 intel_de_write(dev_priv, BCLRPAT(dev_priv, crtc->pipe), 0); in intel_crt_set_dpms()
213 intel_de_write(dev_priv, crt->adpa_reg, adpa); in intel_crt_set_dpms()
244 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_disable_crt()
246 drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder); in hsw_disable_crt()
256 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); in hsw_post_disable_crt()
257 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_post_disable_crt()
275 drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder); in hsw_post_disable_crt()
285 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_pre_pll_enable_crt()
287 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder); in hsw_pre_pll_enable_crt()
297 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_pre_enable_crt()
298 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in hsw_pre_enable_crt()
299 enum pipe pipe = crtc->pipe; in hsw_pre_enable_crt()
301 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder); in hsw_pre_enable_crt()
315 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_enable_crt()
316 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in hsw_enable_crt()
317 enum pipe pipe = crtc->pipe; in hsw_enable_crt()
319 drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder); in hsw_enable_crt()
349 struct drm_device *dev = connector->dev; in intel_crt_mode_valid()
351 int max_dotclk = dev_priv->display.cdclk.max_dotclk_freq; in intel_crt_mode_valid()
359 if (mode->clock < 25000) in intel_crt_mode_valid()
374 if (mode->clock > max_clock) in intel_crt_mode_valid()
377 if (mode->clock > max_dotclk) in intel_crt_mode_valid()
382 ilk_get_lanes_required(mode->clock, 270000, 24) > 2) in intel_crt_mode_valid()
386 if (mode->hdisplay > 4096) in intel_crt_mode_valid()
397 &pipe_config->hw.adjusted_mode; in intel_crt_compute_config()
399 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) in intel_crt_compute_config()
400 return -EINVAL; in intel_crt_compute_config()
402 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; in intel_crt_compute_config()
403 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_crt_compute_config()
413 &pipe_config->hw.adjusted_mode; in pch_crt_compute_config()
415 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) in pch_crt_compute_config()
416 return -EINVAL; in pch_crt_compute_config()
418 pipe_config->has_pch_encoder = true; in pch_crt_compute_config()
420 return -EINVAL; in pch_crt_compute_config()
422 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in pch_crt_compute_config()
431 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_crt_compute_config()
433 &pipe_config->hw.adjusted_mode; in hsw_crt_compute_config()
435 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) in hsw_crt_compute_config()
436 return -EINVAL; in hsw_crt_compute_config()
439 if (adjusted_mode->crtc_hdisplay > 4096 || in hsw_crt_compute_config()
440 adjusted_mode->crtc_hblank_start > 4096) in hsw_crt_compute_config()
441 return -EINVAL; in hsw_crt_compute_config()
443 pipe_config->has_pch_encoder = true; in hsw_crt_compute_config()
445 return -EINVAL; in hsw_crt_compute_config()
447 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in hsw_crt_compute_config()
449 /* LPT FDI RX only supports 8bpc. */ in hsw_crt_compute_config()
451 /* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */ in hsw_crt_compute_config()
452 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { in hsw_crt_compute_config()
453 drm_dbg_kms(&dev_priv->drm, in hsw_crt_compute_config()
455 return -EINVAL; in hsw_crt_compute_config()
458 pipe_config->pipe_bpp = 24; in hsw_crt_compute_config()
462 pipe_config->port_clock = 135000 * 2; in hsw_crt_compute_config()
464 pipe_config->enhanced_framing = true; in hsw_crt_compute_config()
466 adjusted_mode->crtc_clock = lpt_iclkip(pipe_config); in hsw_crt_compute_config()
473 struct drm_device *dev = connector->dev; in ilk_crt_detect_hotplug()
480 if (crt->force_hotplug_required) { in ilk_crt_detect_hotplug()
484 crt->force_hotplug_required = false; in ilk_crt_detect_hotplug()
486 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); in ilk_crt_detect_hotplug()
487 drm_dbg_kms(&dev_priv->drm, in ilk_crt_detect_hotplug()
494 intel_de_write(dev_priv, crt->adpa_reg, adpa); in ilk_crt_detect_hotplug()
497 crt->adpa_reg, in ilk_crt_detect_hotplug()
500 drm_dbg_kms(&dev_priv->drm, in ilk_crt_detect_hotplug()
504 intel_de_write(dev_priv, crt->adpa_reg, save_adpa); in ilk_crt_detect_hotplug()
505 intel_de_posting_read(dev_priv, crt->adpa_reg); in ilk_crt_detect_hotplug()
510 adpa = intel_de_read(dev_priv, crt->adpa_reg); in ilk_crt_detect_hotplug()
515 drm_dbg_kms(&dev_priv->drm, "ironlake hotplug adpa=0x%x, result %d\n", in ilk_crt_detect_hotplug()
523 struct drm_device *dev = connector->dev; in valleyview_crt_detect_hotplug()
534 * - We enable power wells and reset the ADPA in valleyview_crt_detect_hotplug()
535 * - output_poll_exec does force probe on VGA, triggering a hpd in valleyview_crt_detect_hotplug()
536 * - HPD handler waits for poll to unlock dev->mode_config.mutex in valleyview_crt_detect_hotplug()
537 * - output_poll_exec shuts off the ADPA, unlocks in valleyview_crt_detect_hotplug()
538 * dev->mode_config.mutex in valleyview_crt_detect_hotplug()
539 * - HPD handler runs, resets ADPA and brings us back to the start in valleyview_crt_detect_hotplug()
543 reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin); in valleyview_crt_detect_hotplug()
545 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); in valleyview_crt_detect_hotplug()
546 drm_dbg_kms(&dev_priv->drm, in valleyview_crt_detect_hotplug()
551 intel_de_write(dev_priv, crt->adpa_reg, adpa); in valleyview_crt_detect_hotplug()
553 if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg, in valleyview_crt_detect_hotplug()
555 drm_dbg_kms(&dev_priv->drm, in valleyview_crt_detect_hotplug()
557 intel_de_write(dev_priv, crt->adpa_reg, save_adpa); in valleyview_crt_detect_hotplug()
561 adpa = intel_de_read(dev_priv, crt->adpa_reg); in valleyview_crt_detect_hotplug()
567 drm_dbg_kms(&dev_priv->drm, in valleyview_crt_detect_hotplug()
571 intel_hpd_enable(dev_priv, crt->base.hpd_pin); in valleyview_crt_detect_hotplug()
578 struct drm_device *dev = connector->dev; in intel_crt_detect_hotplug()
608 drm_dbg_kms(&dev_priv->drm, in intel_crt_detect_hotplug()
626 struct i2c_adapter *ddc) in intel_crt_get_edid() argument
630 drm_edid = drm_edid_read_ddc(connector, ddc); in intel_crt_get_edid()
632 if (!drm_edid && !intel_gmbus_is_forced_bit(ddc)) { in intel_crt_get_edid()
633 drm_dbg_kms(connector->dev, in intel_crt_get_edid()
634 "CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); in intel_crt_get_edid()
635 intel_gmbus_force_bit(ddc, true); in intel_crt_get_edid()
636 drm_edid = drm_edid_read_ddc(connector, ddc); in intel_crt_get_edid()
637 intel_gmbus_force_bit(ddc, false); in intel_crt_get_edid()
645 struct i2c_adapter *ddc) in intel_crt_ddc_get_modes() argument
650 drm_edid = intel_crt_get_edid(connector, ddc); in intel_crt_ddc_get_modes()
664 struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev); in intel_crt_detect_ddc()
668 drm_edid = intel_crt_get_edid(connector, connector->ddc); in intel_crt_detect_ddc()
672 * This may be a DVI-I connector with a shared DDC in intel_crt_detect_ddc()
677 drm_dbg_kms(&dev_priv->drm, in intel_crt_detect_ddc()
678 "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); in intel_crt_detect_ddc()
680 drm_dbg_kms(&dev_priv->drm, in intel_crt_detect_ddc()
681 "CRT detected via DDC:0x50 [EDID]\n"); in intel_crt_detect_ddc()
685 drm_dbg_kms(&dev_priv->drm, in intel_crt_detect_ddc()
686 "CRT not detected via DDC:0x50 [no valid EDID found]\n"); in intel_crt_detect_ddc()
697 struct drm_device *dev = crt->base.base.dev; in intel_crt_load_detect()
709 drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n"); in intel_crt_load_detect()
761 VBLANK_START(vblank_start - 1) | in intel_crt_load_detect()
762 VBLANK_END(vblank_end - 1)); in intel_crt_load_detect()
766 if (vblank_start - vactive >= vtotal - vblank_end) in intel_crt_load_detect()
816 DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident); in intel_spurious_crt_detect_dmi_callback()
831 .ident = "Intel DZ77BH-55K",
834 DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"),
845 struct drm_i915_private *dev_priv = to_i915(connector->dev); in intel_crt_detect()
847 struct intel_encoder *intel_encoder = &crt->base; in intel_crt_detect()
852 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s] force=%d\n", in intel_crt_detect()
853 connector->base.id, connector->name, in intel_crt_detect()
860 return connector->status; in intel_crt_detect()
862 if (dev_priv->display.params.load_detect_test) { in intel_crt_detect()
864 intel_encoder->power_domain); in intel_crt_detect()
873 intel_encoder->power_domain); in intel_crt_detect()
881 drm_dbg_kms(&dev_priv->drm, in intel_crt_detect()
886 drm_dbg_kms(&dev_priv->drm, in intel_crt_detect()
906 status = connector->status; in intel_crt_detect()
910 /* for pre-945g platforms use load detect */ in intel_crt_detect()
921 to_intel_crtc(connector->state->crtc)->pipe); in intel_crt_detect()
922 else if (dev_priv->display.params.load_detect_test) in intel_crt_detect()
930 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); in intel_crt_detect()
937 struct drm_device *dev = connector->dev; in intel_crt_get_modes()
940 struct intel_encoder *intel_encoder = &crt->base; in intel_crt_get_modes()
942 struct i2c_adapter *ddc; in intel_crt_get_modes() local
949 intel_encoder->power_domain); in intel_crt_get_modes()
951 ret = intel_crt_ddc_get_modes(connector, connector->ddc); in intel_crt_get_modes()
955 /* Try to probe digital port for output in DVI-I -> VGA mode. */ in intel_crt_get_modes()
956 ddc = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); in intel_crt_get_modes()
957 ret = intel_crt_ddc_get_modes(connector, ddc); in intel_crt_get_modes()
960 intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); in intel_crt_get_modes()
967 struct drm_i915_private *dev_priv = to_i915(encoder->dev); in intel_crt_reset()
973 adpa = intel_de_read(dev_priv, crt->adpa_reg); in intel_crt_reset()
976 intel_de_write(dev_priv, crt->adpa_reg, adpa); in intel_crt_reset()
977 intel_de_posting_read(dev_priv, crt->adpa_reg); in intel_crt_reset()
979 drm_dbg_kms(&dev_priv->drm, "crt adpa set to 0x%x\n", adpa); in intel_crt_reset()
980 crt->force_hotplug_required = true; in intel_crt_reset()
1052 ddc_pin = dev_priv->display.vbt.crt_ddc_pin; in intel_crt_init()
1054 connector = &intel_connector->base; in intel_crt_init()
1055 crt->connector = intel_connector; in intel_crt_init()
1056 drm_connector_init_with_ddc(&dev_priv->drm, connector, in intel_crt_init()
1061 drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs, in intel_crt_init()
1064 intel_connector_attach_encoder(intel_connector, &crt->base); in intel_crt_init()
1066 crt->base.type = INTEL_OUTPUT_ANALOG; in intel_crt_init()
1067 crt->base.cloneable = BIT(INTEL_OUTPUT_DVO) | BIT(INTEL_OUTPUT_HDMI); in intel_crt_init()
1069 crt->base.pipe_mask = BIT(PIPE_A); in intel_crt_init()
1071 crt->base.pipe_mask = ~0; in intel_crt_init()
1074 connector->interlace_allowed = true; in intel_crt_init()
1076 crt->adpa_reg = adpa_reg; in intel_crt_init()
1078 crt->base.power_domain = POWER_DOMAIN_PORT_CRT; in intel_crt_init()
1082 crt->base.hpd_pin = HPD_CRT; in intel_crt_init()
1083 crt->base.hotplug = intel_encoder_hotplug; in intel_crt_init()
1084 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; in intel_crt_init()
1086 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; in intel_crt_init()
1088 intel_connector->base.polled = intel_connector->polled; in intel_crt_init()
1093 crt->base.port = PORT_E; in intel_crt_init()
1094 crt->base.get_config = hsw_crt_get_config; in intel_crt_init()
1095 crt->base.get_hw_state = intel_ddi_get_hw_state; in intel_crt_init()
1096 crt->base.compute_config = hsw_crt_compute_config; in intel_crt_init()
1097 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt; in intel_crt_init()
1098 crt->base.pre_enable = hsw_pre_enable_crt; in intel_crt_init()
1099 crt->base.enable = hsw_enable_crt; in intel_crt_init()
1100 crt->base.disable = hsw_disable_crt; in intel_crt_init()
1101 crt->base.post_disable = hsw_post_disable_crt; in intel_crt_init()
1102 crt->base.enable_clock = hsw_ddi_enable_clock; in intel_crt_init()
1103 crt->base.disable_clock = hsw_ddi_disable_clock; in intel_crt_init()
1104 crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled; in intel_crt_init()
1106 intel_ddi_buf_trans_init(&crt->base); in intel_crt_init()
1109 crt->base.compute_config = pch_crt_compute_config; in intel_crt_init()
1110 crt->base.disable = pch_disable_crt; in intel_crt_init()
1111 crt->base.post_disable = pch_post_disable_crt; in intel_crt_init()
1113 crt->base.compute_config = intel_crt_compute_config; in intel_crt_init()
1114 crt->base.disable = intel_disable_crt; in intel_crt_init()
1116 crt->base.port = PORT_NONE; in intel_crt_init()
1117 crt->base.get_config = intel_crt_get_config; in intel_crt_init()
1118 crt->base.get_hw_state = intel_crt_get_hw_state; in intel_crt_init()
1119 crt->base.enable = intel_enable_crt; in intel_crt_init()
1121 intel_connector->get_hw_state = intel_connector_get_hw_state; in intel_crt_init()
1134 dev_priv->display.fdi.rx_config = intel_de_read(dev_priv, in intel_crt_init()
1138 intel_crt_reset(&crt->base.base); in intel_crt_init()