Lines Matching +full:- +full:phy
1 // SPDX-License-Identifier: MIT
17 for ((__phy) = I915_MAX_PHYS; (__phy)-- > PHY_A;) \
33 .name = "0.85V dot0 (low-voltage)",
55 icl_get_procmon_ref_values(struct drm_i915_private *dev_priv, enum phy phy) in icl_get_procmon_ref_values() argument
59 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); in icl_get_procmon_ref_values()
78 enum phy phy) in icl_set_procmon_ref_values() argument
82 procmon = icl_get_procmon_ref_values(dev_priv, phy); in icl_set_procmon_ref_values()
84 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW1(phy), in icl_set_procmon_ref_values()
85 (0xff << 16) | 0xff, procmon->dw1); in icl_set_procmon_ref_values()
87 intel_de_write(dev_priv, ICL_PORT_COMP_DW9(phy), procmon->dw9); in icl_set_procmon_ref_values()
88 intel_de_write(dev_priv, ICL_PORT_COMP_DW10(phy), procmon->dw10); in icl_set_procmon_ref_values()
92 enum phy phy, i915_reg_t reg, u32 mask, in check_phy_reg() argument
98 drm_dbg(&dev_priv->drm, in check_phy_reg()
99 "Combo PHY %c reg %08x state mismatch: " in check_phy_reg()
101 phy_name(phy), in check_phy_reg()
110 enum phy phy) in icl_verify_procmon_ref_values() argument
115 procmon = icl_get_procmon_ref_values(dev_priv, phy); in icl_verify_procmon_ref_values()
117 ret = check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW1(phy), in icl_verify_procmon_ref_values()
118 (0xff << 16) | 0xff, procmon->dw1); in icl_verify_procmon_ref_values()
119 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW9(phy), in icl_verify_procmon_ref_values()
120 -1U, procmon->dw9); in icl_verify_procmon_ref_values()
121 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW10(phy), in icl_verify_procmon_ref_values()
122 -1U, procmon->dw10); in icl_verify_procmon_ref_values()
127 static bool has_phy_misc(struct drm_i915_private *i915, enum phy phy) in has_phy_misc() argument
130 * Some platforms only expect PHY_MISC to be programmed for PHY-A and in has_phy_misc()
131 * PHY-B and may not even have instances of the register for the in has_phy_misc()
132 * other combo PHY's. in has_phy_misc()
134 * ADL-S technically has three instances of PHY_MISC, but only requires in has_phy_misc()
135 * that we program it for PHY A. in has_phy_misc()
139 return phy == PHY_A; in has_phy_misc()
143 return phy < PHY_C; in has_phy_misc()
149 enum phy phy) in icl_combo_phy_enabled() argument
151 /* The PHY C added by EHL has no PHY_MISC register */ in icl_combo_phy_enabled()
152 if (!has_phy_misc(dev_priv, phy)) in icl_combo_phy_enabled()
153 return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT; in icl_combo_phy_enabled()
155 return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) & in icl_combo_phy_enabled()
157 (intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT); in icl_combo_phy_enabled()
162 struct intel_display *display = &i915->display; in ehl_vbt_ddi_d_present()
170 * the PHY. So if combo PHY A is wired up to drive an external in ehl_vbt_ddi_d_present()
179 * DDI-D _and_ an internal display on DDI-A/DSI leave an error message in ehl_vbt_ddi_d_present()
183 drm_err(&i915->drm, in ehl_vbt_ddi_d_present()
184 "VBT claims to have both internal and external displays on PHY A. Configuring for internal.\n"); in ehl_vbt_ddi_d_present()
189 static bool phy_is_master(struct drm_i915_private *dev_priv, enum phy phy) in phy_is_master() argument
196 * A(master) -> B(slave), C(slave) in phy_is_master()
198 * A(master) -> B(slave) in phy_is_master()
199 * C(master) -> D(slave) in phy_is_master()
200 * ADL-S: in phy_is_master()
201 * A(master) -> B(slave), C(slave) in phy_is_master()
202 * D(master) -> E(slave) in phy_is_master()
204 * We must set the IREFGEN bit for any PHY acting as a master in phy_is_master()
205 * to another PHY. in phy_is_master()
207 if (phy == PHY_A) in phy_is_master()
210 return phy == PHY_D; in phy_is_master()
212 return phy == PHY_C; in phy_is_master()
218 enum phy phy) in icl_combo_phy_verify_state() argument
223 if (!icl_combo_phy_enabled(dev_priv, phy)) in icl_combo_phy_verify_state()
227 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_TX_DW8_LN(0, phy), in icl_combo_phy_verify_state()
233 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_PCS_DW1_LN(0, phy), in icl_combo_phy_verify_state()
237 ret &= icl_verify_procmon_ref_values(dev_priv, phy); in icl_combo_phy_verify_state()
239 if (phy_is_master(dev_priv, phy)) { in icl_combo_phy_verify_state()
240 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_COMP_DW8(phy), in icl_combo_phy_verify_state()
247 ret &= check_phy_reg(dev_priv, phy, ICL_PHY_MISC(phy), in icl_combo_phy_verify_state()
253 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy), in icl_combo_phy_verify_state()
260 enum phy phy, bool is_dsi, in intel_combo_phy_power_up_lanes() argument
266 drm_WARN_ON(&dev_priv->drm, lane_reversal); in intel_combo_phy_power_up_lanes()
304 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), in intel_combo_phy_power_up_lanes()
310 enum phy phy; in icl_combo_phys_init() local
312 for_each_combo_phy(dev_priv, phy) { in icl_combo_phys_init()
316 if (icl_combo_phy_verify_state(dev_priv, phy)) in icl_combo_phys_init()
319 procmon = icl_get_procmon_ref_values(dev_priv, phy); in icl_combo_phys_init()
321 drm_dbg(&dev_priv->drm, in icl_combo_phys_init()
322 "Initializing combo PHY %c (Voltage/Process Info : %s)\n", in icl_combo_phys_init()
323 phy_name(phy), procmon->name); in icl_combo_phys_init()
325 if (!has_phy_misc(dev_priv, phy)) in icl_combo_phys_init()
329 * EHL's combo PHY A can be hooked up to either an external in icl_combo_phys_init()
330 * display (via DDI-D) or an internal display (via DDI-A or in icl_combo_phys_init()
332 * can't be changed on the fly, so initialize the PHY's mux in icl_combo_phys_init()
336 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); in icl_combo_phys_init()
338 phy == PHY_A) { in icl_combo_phys_init()
346 intel_de_write(dev_priv, ICL_PHY_MISC(phy), val); in icl_combo_phys_init()
350 val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN(0, phy)); in icl_combo_phys_init()
354 intel_de_write(dev_priv, ICL_PORT_TX_DW8_GRP(phy), val); in icl_combo_phys_init()
356 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); in icl_combo_phys_init()
359 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val); in icl_combo_phys_init()
362 icl_set_procmon_ref_values(dev_priv, phy); in icl_combo_phys_init()
364 if (phy_is_master(dev_priv, phy)) in icl_combo_phys_init()
365 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW8(phy), in icl_combo_phys_init()
368 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW0(phy), 0, COMP_INIT); in icl_combo_phys_init()
369 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), in icl_combo_phys_init()
376 enum phy phy; in icl_combo_phys_uninit() local
378 for_each_combo_phy_reverse(dev_priv, phy) { in icl_combo_phys_uninit()
379 if (phy == PHY_A && in icl_combo_phys_uninit()
380 !icl_combo_phy_verify_state(dev_priv, phy)) { in icl_combo_phys_uninit()
384 * https://gitlab.freedesktop.org/drm/intel/-/issues/2411 in icl_combo_phys_uninit()
387 drm_dbg_kms(&dev_priv->drm, in icl_combo_phys_uninit()
388 "Combo PHY %c HW state changed unexpectedly\n", in icl_combo_phys_uninit()
389 phy_name(phy)); in icl_combo_phys_uninit()
391 drm_warn(&dev_priv->drm, in icl_combo_phys_uninit()
392 "Combo PHY %c HW state changed unexpectedly\n", in icl_combo_phys_uninit()
393 phy_name(phy)); in icl_combo_phys_uninit()
397 if (!has_phy_misc(dev_priv, phy)) in icl_combo_phys_uninit()
400 intel_de_rmw(dev_priv, ICL_PHY_MISC(phy), 0, in icl_combo_phys_uninit()
404 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW0(phy), COMP_INIT, 0); in icl_combo_phys_uninit()