183 	cdclk_config->cdclk = 450000;  in fixed_450mhz_get_cdclk()
514 		cdclk_config->cdclk = 450000;  in hsw_get_cdclk()
516 		cdclk_config->cdclk = 450000;  in hsw_get_cdclk()
766 	else if (min_cdclk > 450000)  in bdw_calc_cdclk()
769 		return 450000;  in bdw_calc_cdclk()
780 	case 450000:  in bdw_calc_voltage_level()
798 		cdclk_config->cdclk = 450000;  in bdw_get_cdclk()
800 		cdclk_config->cdclk = 450000;  in bdw_get_cdclk()
824 	case 450000:  in bdw_cdclk_freq_sel()
900 		else if (min_cdclk > 450000)  in skl_calc_cdclk()
903 			return 450000;  in skl_calc_cdclk()
913 	else if (cdclk > 450000)  in skl_calc_voltage_level()
997 			cdclk_config->cdclk = 450000;  in skl_get_cdclk()
1103 	case 450000:  in skl_cdclk_freq_sel()
1440 	{ .refclk = 38400, .cdclk = 450000, .ratio = 25, .waveform = 0xfffe },
3447 			dev_priv->display.cdclk.max_cdclk_freq = 450000;  in intel_update_max_cdclk()
3449 			dev_priv->display.cdclk.max_cdclk_freq = 450000;  in intel_update_max_cdclk()