966 			       struct intel_bw_state *new_bw_state)  in mtl_find_qgv_points()  argument
974 	ret = intel_atomic_lock_global_state(&new_bw_state->base);  in mtl_find_qgv_points()
983 	if (!intel_can_enable_sagv(i915, new_bw_state)) {  in mtl_find_qgv_points()
984 		new_bw_state->qgv_point_peakbw = U16_MAX;  in mtl_find_qgv_points()
1029 	new_bw_state->qgv_point_peakbw = DIV_ROUND_CLOSEST(qgv_peak_bw, 100);  in mtl_find_qgv_points()
1038 			       struct intel_bw_state *new_bw_state)  in icl_find_qgv_points()  argument
1047 	ret = intel_atomic_lock_global_state(&new_bw_state->base);  in icl_find_qgv_points()
1096 	if (!intel_can_enable_sagv(i915, new_bw_state)) {  in icl_find_qgv_points()
1106 	new_bw_state->qgv_points_mask = icl_prepare_qgv_points_mask(i915,  in icl_find_qgv_points()
1113 	if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) {  in icl_find_qgv_points()
1114 		ret = intel_atomic_serialize_global_state(&new_bw_state->base);  in icl_find_qgv_points()
1124 				     struct intel_bw_state *new_bw_state)  in intel_bw_check_qgv_points()  argument
1126 	unsigned int data_rate = intel_bw_data_rate(i915, new_bw_state);  in intel_bw_check_qgv_points()
1128 			intel_bw_num_active_planes(i915, new_bw_state);  in intel_bw_check_qgv_points()
1134 					   new_bw_state);  in intel_bw_check_qgv_points()
1137 					   old_bw_state, new_bw_state);  in intel_bw_check_qgv_points()
1142 				   const struct intel_bw_state *new_bw_state)  in intel_bw_state_changed()  argument
1150 			&new_bw_state->dbuf_bw[pipe];  in intel_bw_state_changed()
1159 		if (old_bw_state->min_cdclk[pipe] != new_bw_state->min_cdclk[pipe])  in intel_bw_state_changed()
1268 	struct intel_bw_state *new_bw_state = NULL;  in intel_bw_calc_min_cdclk()  local
1280 		new_bw_state = intel_atomic_get_bw_state(state);  in intel_bw_calc_min_cdclk()
1281 		if (IS_ERR(new_bw_state))  in intel_bw_calc_min_cdclk()
1282 			return PTR_ERR(new_bw_state);  in intel_bw_calc_min_cdclk()
1286 		skl_crtc_calc_dbuf_bw(new_bw_state, crtc_state);  in intel_bw_calc_min_cdclk()
1288 		new_bw_state->min_cdclk[crtc->pipe] =  in intel_bw_calc_min_cdclk()
1295 	if (intel_bw_state_changed(dev_priv, old_bw_state, new_bw_state)) {  in intel_bw_calc_min_cdclk()
1296 		int ret = intel_atomic_lock_global_state(&new_bw_state->base);  in intel_bw_calc_min_cdclk()
1302 	new_min_cdclk = intel_bw_min_cdclk(dev_priv, new_bw_state);  in intel_bw_calc_min_cdclk()
1355 		struct intel_bw_state *new_bw_state;  in intel_bw_check_data_rate()  local
1365 		new_bw_state = intel_atomic_get_bw_state(state);  in intel_bw_check_data_rate()
1366 		if (IS_ERR(new_bw_state))  in intel_bw_check_data_rate()
1367 			return PTR_ERR(new_bw_state);  in intel_bw_check_data_rate()
1369 		new_bw_state->data_rate[crtc->pipe] = new_data_rate;  in intel_bw_check_data_rate()
1370 		new_bw_state->num_active_planes[crtc->pipe] = new_active_planes;  in intel_bw_check_data_rate()
1377 			    new_bw_state->data_rate[crtc->pipe],  in intel_bw_check_data_rate()
1378 			    new_bw_state->num_active_planes[crtc->pipe]);  in intel_bw_check_data_rate()
1388 	struct intel_bw_state *new_bw_state;  in intel_bw_atomic_check()  local
1401 	new_bw_state = intel_atomic_get_new_bw_state(state);  in intel_bw_atomic_check()
1403 	if (new_bw_state &&  in intel_bw_atomic_check()
1405 	     intel_can_enable_sagv(i915, new_bw_state) ||  in intel_bw_atomic_check()
1406 	     new_bw_state->force_check_qgv))  in intel_bw_atomic_check()
1416 	ret = intel_bw_check_qgv_points(i915, old_bw_state, new_bw_state);  in intel_bw_atomic_check()
1420 	new_bw_state->force_check_qgv = false;  in intel_bw_atomic_check()