Lines Matching +full:tras +full:- +full:min
1 // SPDX-License-Identifier: MIT
49 val = intel_uncore_read(&dev_priv->uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC); in dg1_mchbar_read_qgv_point_info()
55 sp->dclk = DIV_ROUND_UP((16667 * dclk_ratio * dclk_reference) + 500, 1000); in dg1_mchbar_read_qgv_point_info()
57 val = intel_uncore_read(&dev_priv->uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU); in dg1_mchbar_read_qgv_point_info()
59 sp->dclk *= 2; in dg1_mchbar_read_qgv_point_info()
61 if (sp->dclk == 0) in dg1_mchbar_read_qgv_point_info()
62 return -EINVAL; in dg1_mchbar_read_qgv_point_info()
64 val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR); in dg1_mchbar_read_qgv_point_info()
65 sp->t_rp = REG_FIELD_GET(DG1_DRAM_T_RP_MASK, val); in dg1_mchbar_read_qgv_point_info()
66 sp->t_rdpre = REG_FIELD_GET(DG1_DRAM_T_RDPRE_MASK, val); in dg1_mchbar_read_qgv_point_info()
68 val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH); in dg1_mchbar_read_qgv_point_info()
69 sp->t_rcd = REG_FIELD_GET(DG1_DRAM_T_RCD_MASK, val); in dg1_mchbar_read_qgv_point_info()
70 sp->t_ras = REG_FIELD_GET(DG1_DRAM_T_RAS_MASK, val); in dg1_mchbar_read_qgv_point_info()
72 sp->t_rc = sp->t_rp + sp->t_ras; in dg1_mchbar_read_qgv_point_info()
85 ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO | in icl_pcode_read_qgv_point_info()
92 sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) >= 12 ? 500 : 0), in icl_pcode_read_qgv_point_info()
94 sp->t_rp = (val & 0xff0000) >> 16; in icl_pcode_read_qgv_point_info()
95 sp->t_rcd = (val & 0xff000000) >> 24; in icl_pcode_read_qgv_point_info()
97 sp->t_rdpre = val2 & 0xff; in icl_pcode_read_qgv_point_info()
98 sp->t_ras = (val2 & 0xff00) >> 8; in icl_pcode_read_qgv_point_info()
100 sp->t_rc = sp->t_rp + sp->t_ras; in icl_pcode_read_qgv_point_info()
112 ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO | in adls_pcode_read_psf_gv_point_info()
127 unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points; in icl_qgv_points_mask()
128 unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points; in icl_qgv_points_mask()
137 qgv_points = GENMASK(num_qgv_points - 1, 0); in icl_qgv_points_mask()
140 psf_points = GENMASK(num_psf_gv_points - 1, 0); in icl_qgv_points_mask()
160 ret = skl_pcode_request(&dev_priv->uncore, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG, in icl_pcode_restrict_qgv_points()
167 drm_err(&dev_priv->drm, in icl_pcode_restrict_qgv_points()
173 dev_priv->display.sagv.status = is_sagv_enabled(dev_priv, points_mask) ? in icl_pcode_restrict_qgv_points()
185 val = intel_uncore_read(&dev_priv->uncore, in mtl_read_qgv_point_info()
187 val2 = intel_uncore_read(&dev_priv->uncore, in mtl_read_qgv_point_info()
190 sp->dclk = DIV_ROUND_CLOSEST(16667 * dclk, 1000); in mtl_read_qgv_point_info()
191 sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val); in mtl_read_qgv_point_info()
192 sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val); in mtl_read_qgv_point_info()
194 sp->t_rdpre = REG_FIELD_GET(MTL_TRDPRE_MASK, val2); in mtl_read_qgv_point_info()
195 sp->t_ras = REG_FIELD_GET(MTL_TRAS_MASK, val2); in mtl_read_qgv_point_info()
197 sp->t_rc = sp->t_rp + sp->t_ras; in mtl_read_qgv_point_info()
219 const struct dram_info *dram_info = &dev_priv->dram_info; in icl_get_qgv_points()
222 qi->num_points = dram_info->num_qgv_points; in icl_get_qgv_points()
223 qi->num_psf_points = dram_info->num_psf_gv_points; in icl_get_qgv_points()
226 switch (dram_info->type) { in icl_get_qgv_points()
228 qi->t_bl = 4; in icl_get_qgv_points()
229 qi->max_numchannels = 2; in icl_get_qgv_points()
230 qi->channel_width = 64; in icl_get_qgv_points()
231 qi->deinterleave = 2; in icl_get_qgv_points()
234 qi->t_bl = 8; in icl_get_qgv_points()
235 qi->max_numchannels = 4; in icl_get_qgv_points()
236 qi->channel_width = 32; in icl_get_qgv_points()
237 qi->deinterleave = 2; in icl_get_qgv_points()
241 qi->t_bl = 16; in icl_get_qgv_points()
242 qi->max_numchannels = 8; in icl_get_qgv_points()
243 qi->channel_width = 16; in icl_get_qgv_points()
244 qi->deinterleave = 4; in icl_get_qgv_points()
247 qi->channel_width = 32; in icl_get_qgv_points()
250 MISSING_CASE(dram_info->type); in icl_get_qgv_points()
251 return -EINVAL; in icl_get_qgv_points()
254 switch (dram_info->type) { in icl_get_qgv_points()
256 qi->t_bl = is_y_tile ? 8 : 4; in icl_get_qgv_points()
257 qi->max_numchannels = 2; in icl_get_qgv_points()
258 qi->channel_width = 64; in icl_get_qgv_points()
259 qi->deinterleave = is_y_tile ? 1 : 2; in icl_get_qgv_points()
262 qi->t_bl = is_y_tile ? 16 : 8; in icl_get_qgv_points()
263 qi->max_numchannels = 4; in icl_get_qgv_points()
264 qi->channel_width = 32; in icl_get_qgv_points()
265 qi->deinterleave = is_y_tile ? 1 : 2; in icl_get_qgv_points()
269 qi->t_bl = 8; in icl_get_qgv_points()
270 qi->max_numchannels = 4; in icl_get_qgv_points()
271 qi->channel_width = 32; in icl_get_qgv_points()
272 qi->deinterleave = 2; in icl_get_qgv_points()
277 qi->t_bl = 16; in icl_get_qgv_points()
278 qi->max_numchannels = 8; in icl_get_qgv_points()
279 qi->channel_width = 16; in icl_get_qgv_points()
280 qi->deinterleave = is_y_tile ? 2 : 4; in icl_get_qgv_points()
283 qi->t_bl = 16; in icl_get_qgv_points()
284 qi->max_numchannels = 1; in icl_get_qgv_points()
288 qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8; in icl_get_qgv_points()
289 qi->max_numchannels = 1; in icl_get_qgv_points()
292 if (drm_WARN_ON(&dev_priv->drm, in icl_get_qgv_points()
293 qi->num_points > ARRAY_SIZE(qi->points))) in icl_get_qgv_points()
294 qi->num_points = ARRAY_SIZE(qi->points); in icl_get_qgv_points()
296 for (i = 0; i < qi->num_points; i++) { in icl_get_qgv_points()
297 struct intel_qgv_point *sp = &qi->points[i]; in icl_get_qgv_points()
301 drm_dbg_kms(&dev_priv->drm, "Could not read QGV %d info\n", i); in icl_get_qgv_points()
305 drm_dbg_kms(&dev_priv->drm, in icl_get_qgv_points()
306 "QGV %d: DCLK=%d tRP=%d tRDPRE=%d tRAS=%d tRCD=%d tRC=%d\n", in icl_get_qgv_points()
307 i, sp->dclk, sp->t_rp, sp->t_rdpre, sp->t_ras, in icl_get_qgv_points()
308 sp->t_rcd, sp->t_rc); in icl_get_qgv_points()
311 if (qi->num_psf_points > 0) { in icl_get_qgv_points()
312 ret = adls_pcode_read_psf_gv_point_info(dev_priv, qi->psf_points); in icl_get_qgv_points()
314 …drm_err(&dev_priv->drm, "Failed to read PSF point data; PSF points will not be considered in bandw… in icl_get_qgv_points()
315 qi->num_psf_points = 0; in icl_get_qgv_points()
318 for (i = 0; i < qi->num_psf_points; i++) in icl_get_qgv_points()
319 drm_dbg_kms(&dev_priv->drm, in icl_get_qgv_points()
321 i, qi->psf_points[i].clk); in icl_get_qgv_points()
342 for (i = 0; i < qi->num_points; i++) in icl_sagv_max_dclk()
343 dclk = max(dclk, qi->points[i].dclk); in icl_sagv_max_dclk()
405 int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels); in icl_get_bw_info()
409 int num_groups = ARRAY_SIZE(dev_priv->display.bw.max); in icl_get_bw_info()
414 drm_dbg_kms(&dev_priv->drm, in icl_get_bw_info()
420 maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10); in icl_get_bw_info()
421 ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels); in icl_get_bw_info()
425 struct intel_bw_info *bi = &dev_priv->display.bw.max[i]; in icl_get_bw_info()
429 clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i; in icl_get_bw_info()
430 bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1; in icl_get_bw_info()
432 bi->num_qgv_points = qi.num_points; in icl_get_bw_info()
433 bi->num_psf_gv_points = qi.num_psf_points; in icl_get_bw_info()
445 ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd + in icl_get_bw_info()
446 (clpchgroup - 1) * qi.t_bl + sp->t_rdpre); in icl_get_bw_info()
447 bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct); in icl_get_bw_info()
449 bi->deratedbw[j] = min(maxdebw, in icl_get_bw_info()
450 bw * (100 - sa->derating) / 100); in icl_get_bw_info()
452 drm_dbg_kms(&dev_priv->drm, in icl_get_bw_info()
454 i, j, bi->num_planes, bi->deratedbw[j]); in icl_get_bw_info()
463 dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED; in icl_get_bw_info()
465 dev_priv->display.sagv.status = I915_SAGV_ENABLED; in icl_get_bw_info()
473 const struct dram_info *dram_info = &dev_priv->dram_info; in tgl_get_bw_info()
475 int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels); in tgl_get_bw_info()
480 int num_groups = ARRAY_SIZE(dev_priv->display.bw.max); in tgl_get_bw_info()
485 drm_dbg_kms(&dev_priv->drm, in tgl_get_bw_info()
491 (dram_info->type == INTEL_DRAM_LPDDR4 || dram_info->type == INTEL_DRAM_LPDDR5)) in tgl_get_bw_info()
500 drm_warn(&dev_priv->drm, "Number of channels exceeds max number of channels."); in tgl_get_bw_info()
507 maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100); in tgl_get_bw_info()
509 ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels); in tgl_get_bw_info()
517 struct intel_bw_info *bi = &dev_priv->display.bw.max[i]; in tgl_get_bw_info()
522 clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i; in tgl_get_bw_info()
524 if (i < num_groups - 1) { in tgl_get_bw_info()
525 bi_next = &dev_priv->display.bw.max[i + 1]; in tgl_get_bw_info()
528 bi_next->num_planes = (ipqdepth - clpchgroup) / in tgl_get_bw_info()
531 bi_next->num_planes = 0; in tgl_get_bw_info()
534 bi->num_qgv_points = qi.num_points; in tgl_get_bw_info()
535 bi->num_psf_gv_points = qi.num_psf_points; in tgl_get_bw_info()
547 ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd + in tgl_get_bw_info()
548 (clpchgroup - 1) * qi.t_bl + sp->t_rdpre); in tgl_get_bw_info()
549 bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct); in tgl_get_bw_info()
551 bi->deratedbw[j] = min(maxdebw, in tgl_get_bw_info()
552 bw * (100 - sa->derating) / 100); in tgl_get_bw_info()
553 bi->peakbw[j] = DIV_ROUND_CLOSEST(sp->dclk * in tgl_get_bw_info()
557 drm_dbg_kms(&dev_priv->drm, in tgl_get_bw_info()
559 i, j, bi->num_planes, bi->deratedbw[j], in tgl_get_bw_info()
560 bi->peakbw[j]); in tgl_get_bw_info()
566 bi->psf_bw[j] = adl_calc_psf_bw(sp->clk); in tgl_get_bw_info()
568 drm_dbg_kms(&dev_priv->drm, in tgl_get_bw_info()
570 i, j, bi->num_planes, bi->psf_bw[j]); in tgl_get_bw_info()
580 dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED; in tgl_get_bw_info()
582 dev_priv->display.sagv.status = I915_SAGV_ENABLED; in tgl_get_bw_info()
590 int num_groups = ARRAY_SIZE(i915->display.bw.max); in dg2_get_bw_info()
597 * platforms. DG2-G10 platforms have a constant 50 GB/s bandwidth, in dg2_get_bw_info()
598 * whereas DG2-G11 platforms have 38 GB/s. in dg2_get_bw_info()
601 struct intel_bw_info *bi = &i915->display.bw.max[i]; in dg2_get_bw_info()
603 bi->num_planes = 1; in dg2_get_bw_info()
605 bi->num_qgv_points = 1; in dg2_get_bw_info()
606 bi->deratedbw[0] = deratedbw; in dg2_get_bw_info()
609 i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED; in dg2_get_bw_info()
616 int num_channels = i915->dram_info.num_channels; in xe2_hpd_get_bw_info()
622 drm_dbg_kms(&i915->drm, in xe2_hpd_get_bw_info()
628 maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10); in xe2_hpd_get_bw_info()
632 int bw = num_channels * (qi.channel_width / 8) * point->dclk; in xe2_hpd_get_bw_info()
634 i915->display.bw.max[0].deratedbw[i] = in xe2_hpd_get_bw_info()
635 min(maxdebw, (100 - sa->derating) * bw / 100); in xe2_hpd_get_bw_info()
636 i915->display.bw.max[0].peakbw[i] = bw; in xe2_hpd_get_bw_info()
638 drm_dbg_kms(&i915->drm, "QGV %d: deratedbw=%u peakbw: %u\n", in xe2_hpd_get_bw_info()
639 i, i915->display.bw.max[0].deratedbw[i], in xe2_hpd_get_bw_info()
640 i915->display.bw.max[0].peakbw[i]); in xe2_hpd_get_bw_info()
644 i915->display.bw.max[0].num_planes = 1; in xe2_hpd_get_bw_info()
645 i915->display.bw.max[0].num_qgv_points = qi.num_points; in xe2_hpd_get_bw_info()
646 for (i = 1; i < ARRAY_SIZE(i915->display.bw.max); i++) in xe2_hpd_get_bw_info()
647 memcpy(&i915->display.bw.max[i], &i915->display.bw.max[0], in xe2_hpd_get_bw_info()
648 sizeof(i915->display.bw.max[0])); in xe2_hpd_get_bw_info()
652 * battery and plugged-in operation. in xe2_hpd_get_bw_info()
654 drm_WARN_ON(&i915->drm, qi.num_points != 2); in xe2_hpd_get_bw_info()
655 i915->display.sagv.status = I915_SAGV_ENABLED; in xe2_hpd_get_bw_info()
670 for (i = 0; i < ARRAY_SIZE(dev_priv->display.bw.max); i++) { in icl_max_bw_index()
672 &dev_priv->display.bw.max[i]; in icl_max_bw_index()
676 * SAGV is forced to off/min/med/max. in icl_max_bw_index()
678 if (qgv_point >= bi->num_qgv_points) in icl_max_bw_index()
681 if (num_planes >= bi->num_planes) in icl_max_bw_index()
698 for (i = ARRAY_SIZE(dev_priv->display.bw.max) - 1; i >= 0; i--) { in tgl_max_bw_index()
700 &dev_priv->display.bw.max[i]; in tgl_max_bw_index()
704 * SAGV is forced to off/min/med/max. in tgl_max_bw_index()
706 if (qgv_point >= bi->num_qgv_points) in tgl_max_bw_index()
709 if (num_planes <= bi->num_planes) in tgl_max_bw_index()
720 &dev_priv->display.bw.max[0]; in adl_psf_bw()
722 return bi->psf_bw[psf_gv_point]; in adl_psf_bw()
735 if (idx >= ARRAY_SIZE(i915->display.bw.max)) in icl_qgv_bw()
738 return i915->display.bw.max[idx].deratedbw[qgv_point]; in icl_qgv_bw()
770 return hweight8(crtc_state->active_planes & ~BIT(PLANE_CURSOR)); in intel_bw_crtc_num_active_planes()
775 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_bw_crtc_data_rate()
776 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_bw_crtc_data_rate()
788 data_rate += crtc_state->data_rate[plane_id]; in intel_bw_crtc_data_rate()
791 data_rate += crtc_state->data_rate_y[plane_id]; in intel_bw_crtc_data_rate()
800 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_bw_crtc_min_cdclk()
801 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_bw_crtc_min_cdclk()
812 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_bw_crtc_update()
813 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in intel_bw_crtc_update()
815 bw_state->data_rate[crtc->pipe] = in intel_bw_crtc_update()
817 bw_state->num_active_planes[crtc->pipe] = in intel_bw_crtc_update()
819 bw_state->force_check_qgv = true; in intel_bw_crtc_update()
821 drm_dbg_kms(&i915->drm, "pipe %c data rate %u num active planes %u\n", in intel_bw_crtc_update()
822 pipe_name(crtc->pipe), in intel_bw_crtc_update()
823 bw_state->data_rate[crtc->pipe], in intel_bw_crtc_update()
824 bw_state->num_active_planes[crtc->pipe]); in intel_bw_crtc_update()
834 num_active_planes += bw_state->num_active_planes[pipe]; in intel_bw_num_active_planes()
846 data_rate += bw_state->data_rate[pipe]; in intel_bw_data_rate()
857 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_atomic_get_old_bw_state()
860 bw_state = intel_atomic_get_old_global_obj_state(state, &dev_priv->display.bw.obj); in intel_atomic_get_old_bw_state()
868 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_atomic_get_new_bw_state()
871 bw_state = intel_atomic_get_new_global_obj_state(state, &dev_priv->display.bw.obj); in intel_atomic_get_new_bw_state()
879 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_atomic_get_bw_state()
882 bw_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.bw.obj); in intel_atomic_get_bw_state()
892 unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points; in icl_max_bw_qgv_point_mask()
928 unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points; in icl_max_bw_psf_gv_point_mask()
953 bw_state->qgv_points_mask = icl_prepare_qgv_points_mask(i915, in icl_force_disable_sagv()
957 drm_dbg_kms(&i915->drm, "Forcing SAGV disable: mask 0x%x\n", in icl_force_disable_sagv()
958 bw_state->qgv_points_mask); in icl_force_disable_sagv()
960 icl_pcode_restrict_qgv_points(i915, bw_state->qgv_points_mask); in icl_force_disable_sagv()
969 unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points; in mtl_find_qgv_points()
974 ret = intel_atomic_lock_global_state(&new_bw_state->base); in mtl_find_qgv_points()
984 new_bw_state->qgv_point_peakbw = U16_MAX; in mtl_find_qgv_points()
985 drm_dbg_kms(&i915->drm, "No SAGV, use UINT_MAX as peak bw."); in mtl_find_qgv_points()
998 if (bw_index >= ARRAY_SIZE(i915->display.bw.max)) in mtl_find_qgv_points()
1001 max_data_rate = i915->display.bw.max[bw_index].deratedbw[i]; in mtl_find_qgv_points()
1006 if (max_data_rate - data_rate < best_rate) { in mtl_find_qgv_points()
1007 best_rate = max_data_rate - data_rate; in mtl_find_qgv_points()
1008 qgv_peak_bw = i915->display.bw.max[bw_index].peakbw[i]; in mtl_find_qgv_points()
1011 drm_dbg_kms(&i915->drm, "QGV point %d: max bw %d required %d qgv_peak_bw: %d\n", in mtl_find_qgv_points()
1015 drm_dbg_kms(&i915->drm, "Matching peaks QGV bw: %d for required data rate: %d\n", in mtl_find_qgv_points()
1023 drm_dbg_kms(&i915->drm, "No QGV points for bw %d for display configuration(%d active planes).\n", in mtl_find_qgv_points()
1025 return -EINVAL; in mtl_find_qgv_points()
1029 new_bw_state->qgv_point_peakbw = DIV_ROUND_CLOSEST(qgv_peak_bw, 100); in mtl_find_qgv_points()
1040 unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points; in icl_find_qgv_points()
1041 unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points; in icl_find_qgv_points()
1047 ret = intel_atomic_lock_global_state(&new_bw_state->base); in icl_find_qgv_points()
1057 drm_dbg_kms(&i915->drm, "QGV point %d: max bw %d required %d\n", in icl_find_qgv_points()
1067 drm_dbg_kms(&i915->drm, "PSF GV point %d: max bw %d" in icl_find_qgv_points()
1074 * left, so if we couldn't - simply reject the configuration for obvious in icl_find_qgv_points()
1078 drm_dbg_kms(&i915->drm, "No QGV points provide sufficient memory" in icl_find_qgv_points()
1081 return -EINVAL; in icl_find_qgv_points()
1085 drm_dbg_kms(&i915->drm, "No PSF GV points provide sufficient memory" in icl_find_qgv_points()
1088 return -EINVAL; in icl_find_qgv_points()
1098 drm_dbg_kms(&i915->drm, "No SAGV, using single QGV point mask 0x%x\n", in icl_find_qgv_points()
1106 new_bw_state->qgv_points_mask = icl_prepare_qgv_points_mask(i915, in icl_find_qgv_points()
1113 if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) { in icl_find_qgv_points()
1114 ret = intel_atomic_serialize_global_state(&new_bw_state->base); in icl_find_qgv_points()
1148 &old_bw_state->dbuf_bw[pipe]; in intel_bw_state_changed()
1150 &new_bw_state->dbuf_bw[pipe]; in intel_bw_state_changed()
1154 if (old_crtc_bw->max_bw[slice] != new_crtc_bw->max_bw[slice] || in intel_bw_state_changed()
1155 old_crtc_bw->active_planes[slice] != new_crtc_bw->active_planes[slice]) in intel_bw_state_changed()
1159 if (old_bw_state->min_cdclk[pipe] != new_bw_state->min_cdclk[pipe]) in intel_bw_state_changed()
1172 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in skl_plane_calc_dbuf_bw()
1173 struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe]; in skl_plane_calc_dbuf_bw()
1182 crtc_bw->max_bw[slice] = max(crtc_bw->max_bw[slice], data_rate); in skl_plane_calc_dbuf_bw()
1183 crtc_bw->active_planes[slice] |= BIT(plane_id); in skl_plane_calc_dbuf_bw()
1190 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in skl_crtc_calc_dbuf_bw()
1191 struct drm_i915_private *i915 = to_i915(crtc->base.dev); in skl_crtc_calc_dbuf_bw()
1192 struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe]; in skl_crtc_calc_dbuf_bw()
1197 if (!crtc_state->hw.active) in skl_crtc_calc_dbuf_bw()
1209 &crtc_state->wm.skl.plane_ddb[plane_id], in skl_crtc_calc_dbuf_bw()
1210 crtc_state->data_rate[plane_id]); in skl_crtc_calc_dbuf_bw()
1214 &crtc_state->wm.skl.plane_ddb_y[plane_id], in skl_crtc_calc_dbuf_bw()
1215 crtc_state->data_rate[plane_id]); in skl_crtc_calc_dbuf_bw()
1237 const struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[pipe]; in intel_bw_dbuf_min_cdclk()
1239 max_bw = max(crtc_bw->max_bw[slice], max_bw); in intel_bw_dbuf_min_cdclk()
1240 num_active_planes += hweight8(crtc_bw->active_planes[slice]); in intel_bw_dbuf_min_cdclk()
1259 min_cdclk = max(bw_state->min_cdclk[pipe], min_cdclk); in intel_bw_min_cdclk()
1267 struct drm_i915_private *dev_priv = to_i915(state->base.dev); in intel_bw_calc_min_cdclk()
1288 new_bw_state->min_cdclk[crtc->pipe] = in intel_bw_calc_min_cdclk()
1296 int ret = intel_atomic_lock_global_state(&new_bw_state->base); in intel_bw_calc_min_cdclk()
1306 * the min cdclk doesn't increase. in intel_bw_calc_min_cdclk()
1321 * the min cdclk doesn't increase. in intel_bw_calc_min_cdclk()
1327 if (new_min_cdclk <= cdclk_state->bw_min_cdclk) in intel_bw_calc_min_cdclk()
1330 drm_dbg_kms(&dev_priv->drm, in intel_bw_calc_min_cdclk()
1331 "new bandwidth min cdclk (%d kHz) > old min cdclk (%d kHz)\n", in intel_bw_calc_min_cdclk()
1332 new_min_cdclk, cdclk_state->bw_min_cdclk); in intel_bw_calc_min_cdclk()
1340 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_bw_check_data_rate()
1369 new_bw_state->data_rate[crtc->pipe] = new_data_rate; in intel_bw_check_data_rate()
1370 new_bw_state->num_active_planes[crtc->pipe] = new_active_planes; in intel_bw_check_data_rate()
1374 drm_dbg_kms(&i915->drm, in intel_bw_check_data_rate()
1376 crtc->base.base.id, crtc->base.name, in intel_bw_check_data_rate()
1377 new_bw_state->data_rate[crtc->pipe], in intel_bw_check_data_rate()
1378 new_bw_state->num_active_planes[crtc->pipe]); in intel_bw_check_data_rate()
1387 struct drm_i915_private *i915 = to_i915(state->base.dev); in intel_bw_atomic_check()
1406 new_bw_state->force_check_qgv)) in intel_bw_atomic_check()
1420 new_bw_state->force_check_qgv = false; in intel_bw_atomic_check()
1430 state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); in intel_bw_duplicate_state()
1434 return &state->base; in intel_bw_duplicate_state()
1454 return -ENOMEM; in intel_bw_init()
1456 intel_atomic_global_obj_init(i915, &i915->display.bw.obj, in intel_bw_init()
1457 &state->base, &intel_bw_funcs); in intel_bw_init()