i915/display/intel_alpm.c

56 		*silence_period = 20;  in _lnl_get_silence_period_and_lfps_half_cycle()
107  * : 12 us
110  * The tPHY Establishment (a.k.a. t1) term is 50us
113  * Number ML_PHY_LOCK = ( 7 + CEILING( 6.5us / tML_PHY_LOCK ) + 1)
114  * Rounding up the 6.5us padding to the next ML_PHY_LOCK boundary and
177 	if (DISPLAY_VER(display) < 20)  in _lnl_compute_alpm_params()
180 	/* ALPM Entry Check = 2 + CEILING( 5us /tline ) */  in _lnl_compute_alpm_params()
200  * are 50 us io wake time and 32 us fast wake time. Clearly preharge pulses are
201  * not (improperly) included in 32 us fast wake time. 50 us - 32 us = 18 us.
228 	int tfw_exit_latency = 20; /* eDP spec */  in intel_alpm_compute_params()
239 	if (DISPLAY_VER(display) >= 20)  in intel_alpm_compute_params()
280 	if (DISPLAY_VER(display) < 20)  in intel_alpm_lobf_compute_config()
317 	if (DISPLAY_VER(display) < 20 ||  in lnl_alpm_configure()
409 	if (DISPLAY_VER(display) < 20 ||  in intel_alpm_lobf_debugfs_add()