Lines Matching +full:10 +full:us
42 * FLOOR( (Link Rate * tLFPS_Cycle) / (2 * 10) )
45 * PORT_ALPM_LFPS_CTL[ LFPS Cycle Count ] = 10
107 * : 12 us
110 * The tPHY Establishment (a.k.a. t1) term is 50us
113 * Number ML_PHY_LOCK = ( 7 + CEILING( 6.5us / tML_PHY_LOCK ) + 1)
114 * Rounding up the 6.5us padding to the next ML_PHY_LOCK boundary and
118 * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) )
128 /* port_clock is link rate in 10kbit/s units */ in _lnl_compute_aux_less_wake_time()
180 /* ALPM Entry Check = 2 + CEILING( 5us /tline ) */ in _lnl_compute_alpm_params()
200 * are 50 us io wake time and 32 us fast wake time. Clearly preharge pulses are
201 * not (improperly) included in 32 us fast wake time. 50 us - 32 us = 18 us.
210 return 10; in tgl_io_buffer_wake_time()
342 PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) | in lnl_alpm_configure()