122 	intel_dp->DP = intel_de_read(display, intel_dp->output_reg) & DP_DETECTED;  in intel_dp_prepare()
173 	bool cur_state = intel_de_read(display, intel_dp->output_reg) & DP_PORT_EN;  in assert_dp_port()
317 	ret = g4x_dp_port_enabled(dev_priv, intel_dp->output_reg,  in intel_dp_get_hw_state()
355 	tmp = intel_de_read(display, intel_dp->output_reg);  in intel_dp_get_config()
428 			(intel_de_read(display, intel_dp->output_reg) &  in intel_dp_link_down()
442 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);  in intel_dp_link_down()
443 	intel_de_posting_read(display, intel_dp->output_reg);  in intel_dp_link_down()
446 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);  in intel_dp_link_down()
447 	intel_de_posting_read(display, intel_dp->output_reg);  in intel_dp_link_down()
466 		intel_de_write(display, intel_dp->output_reg, intel_dp->DP);  in intel_dp_link_down()
467 		intel_de_posting_read(display, intel_dp->output_reg);  in intel_dp_link_down()
470 		intel_de_write(display, intel_dp->output_reg, intel_dp->DP);  in intel_dp_link_down()
471 		intel_de_posting_read(display, intel_dp->output_reg);  in intel_dp_link_down()
500 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);  in g4x_dp_audio_enable()
519 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);  in g4x_dp_audio_disable()
627 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);  in cpt_set_link_train()
628 	intel_de_posting_read(display, intel_dp->output_reg);  in cpt_set_link_train()
655 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);  in g4x_set_link_train()
656 	intel_de_posting_read(display, intel_dp->output_reg);  in g4x_set_link_train()
677 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);  in intel_dp_enable_port()
678 	intel_de_posting_read(display, intel_dp->output_reg);  in intel_dp_enable_port()
689 	u32 dp_reg = intel_de_read(display, intel_dp->output_reg);  in intel_enable_dp()
1052 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);  in g4x_set_signal_levels()
1053 	intel_de_posting_read(display, intel_dp->output_reg);  in g4x_set_signal_levels()
1100 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);  in snb_cpu_edp_set_signal_levels()
1101 	intel_de_posting_read(display, intel_dp->output_reg);  in snb_cpu_edp_set_signal_levels()
1152 	intel_de_write(display, intel_dp->output_reg, intel_dp->DP);  in ivb_cpu_edp_set_signal_levels()
1153 	intel_de_posting_read(display, intel_dp->output_reg);  in ivb_cpu_edp_set_signal_levels()
1259 	if (g4x_dp_port_enabled(dev_priv, intel_dp->output_reg,  in vlv_active_pipe()
1272 	intel_dp->DP = intel_de_read(display, intel_dp->output_reg);  in intel_dp_encoder_reset()
1292 		 i915_reg_t output_reg, enum port port)  in g4x_dp_init()  argument
1393 	dig_port->dp.output_reg = output_reg;  in g4x_dp_init()