Lines Matching +full:mode +full:- +full:reg
1 // SPDX-License-Identifier: GPL-2.0-or-later
60 struct drm_framebuffer *fb = new_plane_state->fb; in hibmc_plane_atomic_check()
61 struct drm_crtc *crtc = new_plane_state->crtc; in hibmc_plane_atomic_check()
63 u32 src_w = new_plane_state->src_w >> 16; in hibmc_plane_atomic_check()
64 u32 src_h = new_plane_state->src_h >> 16; in hibmc_plane_atomic_check()
73 if (src_w != new_plane_state->crtc_w || src_h != new_plane_state->crtc_h) { in hibmc_plane_atomic_check()
74 drm_dbg_atomic(plane->dev, "scale not support\n"); in hibmc_plane_atomic_check()
75 return -EINVAL; in hibmc_plane_atomic_check()
78 if (new_plane_state->crtc_x < 0 || new_plane_state->crtc_y < 0) { in hibmc_plane_atomic_check()
79 drm_dbg_atomic(plane->dev, "crtc_x/y of drm_plane state is invalid\n"); in hibmc_plane_atomic_check()
80 return -EINVAL; in hibmc_plane_atomic_check()
83 if (!crtc_state->enable) in hibmc_plane_atomic_check()
86 if (new_plane_state->crtc_x + new_plane_state->crtc_w > in hibmc_plane_atomic_check()
87 crtc_state->adjusted_mode.hdisplay || in hibmc_plane_atomic_check()
88 new_plane_state->crtc_y + new_plane_state->crtc_h > in hibmc_plane_atomic_check()
89 crtc_state->adjusted_mode.vdisplay) { in hibmc_plane_atomic_check()
90 drm_dbg_atomic(plane->dev, "visible portion of plane is invalid\n"); in hibmc_plane_atomic_check()
91 return -EINVAL; in hibmc_plane_atomic_check()
94 if (new_plane_state->fb->pitches[0] % 128 != 0) { in hibmc_plane_atomic_check()
95 drm_dbg_atomic(plane->dev, "wrong stride with 128-byte aligned\n"); in hibmc_plane_atomic_check()
96 return -EINVAL; in hibmc_plane_atomic_check()
106 u32 reg; in hibmc_plane_atomic_update() local
109 struct hibmc_drm_private *priv = to_hibmc_drm_private(plane->dev); in hibmc_plane_atomic_update()
112 if (!new_state->fb) in hibmc_plane_atomic_update()
115 gbo = drm_gem_vram_of_gem(new_state->fb->obj[0]); in hibmc_plane_atomic_update()
121 writel(gpu_addr, priv->mmio + HIBMC_CRT_FB_ADDRESS); in hibmc_plane_atomic_update()
123 reg = new_state->fb->width * (new_state->fb->format->cpp[0]); in hibmc_plane_atomic_update()
125 line_l = new_state->fb->pitches[0]; in hibmc_plane_atomic_update()
126 writel(HIBMC_FIELD(HIBMC_CRT_FB_WIDTH_WIDTH, reg) | in hibmc_plane_atomic_update()
128 priv->mmio + HIBMC_CRT_FB_WIDTH); in hibmc_plane_atomic_update()
131 reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL); in hibmc_plane_atomic_update()
132 reg &= ~HIBMC_CRT_DISP_CTL_FORMAT_MASK; in hibmc_plane_atomic_update()
133 reg |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_FORMAT, in hibmc_plane_atomic_update()
134 new_state->fb->format->cpp[0] * 8 / 16); in hibmc_plane_atomic_update()
135 writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL); in hibmc_plane_atomic_update()
162 struct hibmc_drm_private *priv = to_hibmc_drm_private(crtc->dev); in hibmc_crtc_dpms()
163 u32 reg; in hibmc_crtc_dpms() local
165 reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL); in hibmc_crtc_dpms()
166 reg &= ~HIBMC_CRT_DISP_CTL_DPMS_MASK; in hibmc_crtc_dpms()
167 reg |= HIBMC_FIELD(HIBMC_CRT_DISP_CTL_DPMS, dpms); in hibmc_crtc_dpms()
168 reg &= ~HIBMC_CRT_DISP_CTL_TIMING_MASK; in hibmc_crtc_dpms()
170 reg |= HIBMC_CRT_DISP_CTL_TIMING(1); in hibmc_crtc_dpms()
171 writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL); in hibmc_crtc_dpms()
177 u32 reg; in hibmc_crtc_atomic_enable() local
178 struct hibmc_drm_private *priv = to_hibmc_drm_private(crtc->dev); in hibmc_crtc_atomic_enable()
183 reg = readl(priv->mmio + HIBMC_CURRENT_GATE); in hibmc_crtc_atomic_enable()
184 reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK; in hibmc_crtc_atomic_enable()
185 reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK; in hibmc_crtc_atomic_enable()
186 reg |= HIBMC_CURR_GATE_LOCALMEM(1); in hibmc_crtc_atomic_enable()
187 reg |= HIBMC_CURR_GATE_DISPLAY(1); in hibmc_crtc_atomic_enable()
188 hibmc_set_current_gate(priv, reg); in hibmc_crtc_atomic_enable()
196 u32 reg; in hibmc_crtc_atomic_disable() local
197 struct hibmc_drm_private *priv = to_hibmc_drm_private(crtc->dev); in hibmc_crtc_atomic_disable()
205 reg = readl(priv->mmio + HIBMC_CURRENT_GATE); in hibmc_crtc_atomic_disable()
206 reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK; in hibmc_crtc_atomic_disable()
207 reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK; in hibmc_crtc_atomic_disable()
208 reg |= HIBMC_CURR_GATE_LOCALMEM(0); in hibmc_crtc_atomic_disable()
209 reg |= HIBMC_CURR_GATE_DISPLAY(0); in hibmc_crtc_atomic_disable()
210 hibmc_set_current_gate(priv, reg); in hibmc_crtc_atomic_disable()
215 const struct drm_display_mode *mode) in hibmc_crtc_mode_valid() argument
218 int vrefresh = drm_mode_vrefresh(mode); in hibmc_crtc_mode_valid()
224 if (hibmc_pll_table[i].hdisplay == mode->hdisplay && in hibmc_crtc_mode_valid()
225 hibmc_pll_table[i].vdisplay == mode->vdisplay) in hibmc_crtc_mode_valid()
259 val = readl(priv->mmio + CRT_PLL1_HS); in set_vclock_hisilicon()
261 writel(val, priv->mmio + CRT_PLL1_HS); in set_vclock_hisilicon()
264 writel(val, priv->mmio + CRT_PLL1_HS); in set_vclock_hisilicon()
266 writel(pll, priv->mmio + CRT_PLL1_HS); in set_vclock_hisilicon()
271 writel(val, priv->mmio + CRT_PLL1_HS); in set_vclock_hisilicon()
276 writel(val, priv->mmio + CRT_PLL1_HS); in set_vclock_hisilicon()
281 writel(val, priv->mmio + CRT_PLL1_HS); in set_vclock_hisilicon()
305 * setup a mode in board.
311 struct drm_display_mode *mode, in display_ctrl_adjust() argument
319 x = mode->hdisplay; in display_ctrl_adjust()
320 y = mode->vdisplay; in display_ctrl_adjust()
323 writel(pll2, priv->mmio + CRT_PLL2_HS); in display_ctrl_adjust()
327 * Hisilicon has to set up the top-left and bottom-right in display_ctrl_adjust()
330 * auto-centering mode. in display_ctrl_adjust()
334 priv->mmio + HIBMC_CRT_AUTO_CENTERING_TL); in display_ctrl_adjust()
336 writel(HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_BOTTOM, y - 1) | in display_ctrl_adjust()
337 HIBMC_FIELD(HIBMC_CRT_AUTO_CENTERING_BR_RIGHT, x - 1), in display_ctrl_adjust()
338 priv->mmio + HIBMC_CRT_AUTO_CENTERING_BR); in display_ctrl_adjust()
355 writel(ctrl, priv->mmio + HIBMC_CRT_DISP_CTL); in display_ctrl_adjust()
363 struct drm_display_mode *mode = &crtc->state->mode; in hibmc_crtc_mode_set_nofb() local
364 struct drm_device *dev = crtc->dev; in hibmc_crtc_mode_set_nofb()
366 u32 width = mode->hsync_end - mode->hsync_start; in hibmc_crtc_mode_set_nofb()
367 u32 height = mode->vsync_end - mode->vsync_start; in hibmc_crtc_mode_set_nofb()
369 writel(format_pll_reg(), priv->mmio + HIBMC_CRT_PLL_CTRL); in hibmc_crtc_mode_set_nofb()
370 writel(HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_TOTAL, mode->htotal - 1) | in hibmc_crtc_mode_set_nofb()
371 HIBMC_FIELD(HIBMC_CRT_HORZ_TOTAL_DISP_END, mode->hdisplay - 1), in hibmc_crtc_mode_set_nofb()
372 priv->mmio + HIBMC_CRT_HORZ_TOTAL); in hibmc_crtc_mode_set_nofb()
375 HIBMC_FIELD(HIBMC_CRT_HORZ_SYNC_START, mode->hsync_start - 1), in hibmc_crtc_mode_set_nofb()
376 priv->mmio + HIBMC_CRT_HORZ_SYNC); in hibmc_crtc_mode_set_nofb()
378 writel(HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_TOTAL, mode->vtotal - 1) | in hibmc_crtc_mode_set_nofb()
379 HIBMC_FIELD(HIBMC_CRT_VERT_TOTAL_DISP_END, mode->vdisplay - 1), in hibmc_crtc_mode_set_nofb()
380 priv->mmio + HIBMC_CRT_VERT_TOTAL); in hibmc_crtc_mode_set_nofb()
383 HIBMC_FIELD(HIBMC_CRT_VERT_SYNC_START, mode->vsync_start - 1), in hibmc_crtc_mode_set_nofb()
384 priv->mmio + HIBMC_CRT_VERT_SYNC); in hibmc_crtc_mode_set_nofb()
391 display_ctrl_adjust(dev, mode, val); in hibmc_crtc_mode_set_nofb()
397 u32 reg; in hibmc_crtc_atomic_begin() local
398 struct drm_device *dev = crtc->dev; in hibmc_crtc_atomic_begin()
404 reg = readl(priv->mmio + HIBMC_CURRENT_GATE); in hibmc_crtc_atomic_begin()
405 reg &= ~HIBMC_CURR_GATE_DISPLAY_MASK; in hibmc_crtc_atomic_begin()
406 reg &= ~HIBMC_CURR_GATE_LOCALMEM_MASK; in hibmc_crtc_atomic_begin()
407 reg |= HIBMC_CURR_GATE_DISPLAY(1); in hibmc_crtc_atomic_begin()
408 reg |= HIBMC_CURR_GATE_LOCALMEM(1); in hibmc_crtc_atomic_begin()
409 hibmc_set_current_gate(priv, reg); in hibmc_crtc_atomic_begin()
420 spin_lock_irqsave(&crtc->dev->event_lock, flags); in hibmc_crtc_atomic_flush()
421 if (crtc->state->event) in hibmc_crtc_atomic_flush()
422 drm_crtc_send_vblank_event(crtc, crtc->state->event); in hibmc_crtc_atomic_flush()
423 crtc->state->event = NULL; in hibmc_crtc_atomic_flush()
424 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); in hibmc_crtc_atomic_flush()
429 struct hibmc_drm_private *priv = to_hibmc_drm_private(crtc->dev); in hibmc_crtc_enable_vblank()
432 priv->mmio + HIBMC_RAW_INTERRUPT_EN); in hibmc_crtc_enable_vblank()
439 struct hibmc_drm_private *priv = to_hibmc_drm_private(crtc->dev); in hibmc_crtc_disable_vblank()
442 priv->mmio + HIBMC_RAW_INTERRUPT_EN); in hibmc_crtc_disable_vblank()
447 struct hibmc_drm_private *priv = to_hibmc_drm_private(crtc->dev); in hibmc_crtc_load_lut()
448 void __iomem *mmio = priv->mmio; in hibmc_crtc_load_lut()
450 u32 reg; in hibmc_crtc_load_lut() local
453 r = crtc->gamma_store; in hibmc_crtc_load_lut()
454 g = r + crtc->gamma_size; in hibmc_crtc_load_lut()
455 b = g + crtc->gamma_size; in hibmc_crtc_load_lut()
457 for (i = 0; i < crtc->gamma_size; i++) { in hibmc_crtc_load_lut()
467 reg = readl(priv->mmio + HIBMC_CRT_DISP_CTL); in hibmc_crtc_load_lut()
468 reg |= HIBMC_FIELD(HIBMC_CTL_DISP_CTL_GAMMA, 1); in hibmc_crtc_load_lut()
469 writel(reg, priv->mmio + HIBMC_CRT_DISP_CTL); in hibmc_crtc_load_lut()
504 struct drm_device *dev = &priv->dev; in hibmc_de_init()
505 struct drm_crtc *crtc = &priv->crtc; in hibmc_de_init()
506 struct drm_plane *plane = &priv->primary_plane; in hibmc_de_init()