drm/gma500/psb_intel_reg.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
70 #define GMBUS3			0x510c /* data buffer bytes 3-0 */
155  * - PLL enabled
156  * - pipe enabled
157  * - LVDS/DVOB/DVOC on
250  * The i830 generation, in LVDS mode, defines P1 as the bit number set within
256 							 * in DVO non-gang */
266  * Parallel to Serial Load Pulse phase selection.
268  * digital display port. The range is 4 to 13; 10 or more
293  * Value is pixels minus 1.  Must be set to 1 pixel for SDVO.
309  * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
310  * rate to 130Mhz to get a bus rate of 1.30Ghz.  The DPLL clock rate would be
311  * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
321  * This best be set to the default value (3) or the CRT won't work. No,
413  * Programmed value is multiplier - 1, up to 5x.
426 /* Bits to be preserved when writing */
431  * This register controls the LVDS output enable, pipe selection, and data
436 #define LVDS			0x61180  macro
438  * Enables the LVDS port.  This bit must be set before DPLLs are enabled, as
439  * the DPLL semantics change when the LVDS is assigned to that pipe.
442 /* Selects pipe B for LVDS data.  Must be set on pre-965. */
445 /* Turns on border drawing to allow centered display. */
449  * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
471  * Controls the B0-B3 data pairs.  This must be set to match the DPLL p2
472  * setting for whether we are in dual-channel mode.  The B3 pair will
688  * of video memory available to the BIOS in SWF1.
776 /* #define LVDS			0x61180 */
784 /* Turns on border drawing to allow centered display. */
865 /* DPI PIXEL FORMATS */
995  *	The display module returns the self-diagnostic results following
1000  *	This command causes the display module to enter the Sleep mode.
1007  *	This command causes the display module to exit Sleep mode.
1012  *	This command causes the display module to enter the Partial Display
1018  *	This command causes the display module to enter the Normal mode.
1023  *	This command causes the display module to stop inverting the image
1029  *	This command causes the display module to invert the image data only on
1040 This command causes the display module to stop displaying the image data
1046 This command causes the display module to start displaying the image data
1066  *	This command transfers image data from the host processor to the
1075  *	refer to the Frame Memory Line Pointer.
1094  *	to display modules frame memory,bits B[7:5] and B3, and from the
1095  *	display modules frame memory to the display device, bits B[2:0] and B4.
1103  *	line in the frame memory that is written to the display device as the
1108  *	This command causes the display module to exit Idle mode.
1112  *	This command causes the display module to enter Idle Mode.
1121  *	Bits D[6:4]  DPI Pixel Format Definition
1135  *	This command transfers image data from the host processor to the
1147  *	The display module returns the current scanline, N, used to update the
1184  *	This command is used to control ambient light, panel backlight
1237 #define PSB_MASK(high, low) (((1<<((high)-(low)+1))-1)<<(low))
1241 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
1268 /* 32-bit value read/written from the DPIO reg. */
1270 /* 32-bit address of the DPIO reg to be read/written. */
1296 /* the bit 14:13 is used to select between the different reference clock for Pipe A/B */
1316 #define SB_P2_14				2 /* LVDS single */
1317 #define SB_P2_7				3 /* LVDS double */
1337 /* Link training mode - select a suitable mode for each stage */
1353 /* Signal pre-emphasis levels, like voltages, the other end tells us what
1363 /* How many wires to use. I guess 3 was too hard */
1381 /** limit RGB values to avoid confusing TVs */
1394 /** The aux channel provides a way to talk to the
1452 /* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
1470  * Attributes and VB-ID.