107 	u32 dpll = 0, fp = 0, dspcntr, pipeconf;  in psb_intel_crtc_mode_set()  local
158 	dpll = DPLL_VGA_MODE_DIS;  in psb_intel_crtc_mode_set()
160 		dpll |= DPLLB_MODE_LVDS;  in psb_intel_crtc_mode_set()
161 		dpll |= DPLL_DVO_HIGH_SPEED;  in psb_intel_crtc_mode_set()
163 		dpll |= DPLLB_MODE_DAC_SERIAL;  in psb_intel_crtc_mode_set()
167 		dpll |= DPLL_DVO_HIGH_SPEED;  in psb_intel_crtc_mode_set()
168 		dpll |=  in psb_intel_crtc_mode_set()
173 	dpll |= (1 << (clock.p1 - 1)) << 16;  in psb_intel_crtc_mode_set()
176 		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;  in psb_intel_crtc_mode_set()
179 		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;  in psb_intel_crtc_mode_set()
182 		dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;  in psb_intel_crtc_mode_set()
185 		dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;  in psb_intel_crtc_mode_set()
191 /*	dpll |= PLL_REF_INPUT_TVCLKINBC; */  in psb_intel_crtc_mode_set()
192 		dpll |= 3;  in psb_intel_crtc_mode_set()
194 	dpll |= PLL_REF_INPUT_DREFCLK;  in psb_intel_crtc_mode_set()
209 	dpll |= DPLL_VCO_ENABLE;  in psb_intel_crtc_mode_set()
218 	if (dpll & DPLL_VCO_ENABLE) {  in psb_intel_crtc_mode_set()
220 		REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE);  in psb_intel_crtc_mode_set()
221 		REG_READ(map->dpll);  in psb_intel_crtc_mode_set()
255 	REG_WRITE(map->dpll, dpll);  in psb_intel_crtc_mode_set()
256 	REG_READ(map->dpll);  in psb_intel_crtc_mode_set()
261 	REG_WRITE(map->dpll, dpll);  in psb_intel_crtc_mode_set()
263 	REG_READ(map->dpll);  in psb_intel_crtc_mode_set()
310 	u32 dpll;  in psb_intel_crtc_clock_get()  local
317 		dpll = REG_READ(map->dpll);  in psb_intel_crtc_clock_get()
318 		if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)  in psb_intel_crtc_clock_get()
325 		dpll = p->dpll;  in psb_intel_crtc_clock_get()
327 		if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)  in psb_intel_crtc_clock_get()
342 		    ffs((dpll &  in psb_intel_crtc_clock_get()
347 		if ((dpll & PLL_REF_INPUT_MASK) ==  in psb_intel_crtc_clock_get()
354 		if (dpll & PLL_P1_DIVIDE_BY_TWO)  in psb_intel_crtc_clock_get()
358 			    ((dpll &  in psb_intel_crtc_clock_get()
362 		if (dpll & PLL_P2_DIVIDE_BY_4)  in psb_intel_crtc_clock_get()