32 	return 0;  in oaktrail_output_init()
39 #define MRST_BLC_MAX_PWM_REG_FREQ	    0xFFFF
51 	if (gma_power_begin(dev, 0)) {  in oaktrail_set_brightness()
69 		REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));  in oaktrail_set_brightness()
100 		REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));  in oaktrail_backlight_init()
106 	return 0;  in oaktrail_backlight_init()
125 	struct psb_pipe *p = &regs->pipe[0];  in oaktrail_save_display_registers()
165 	for (i = 0; i < 256; i++)  in oaktrail_save_display_registers()
204 		PSB_WVDC32(0, PP_CONTROL);  in oaktrail_save_display_registers()
208 		} while (pp_stat & 0x80000000);  in oaktrail_save_display_registers()
211 		PSB_WVDC32(0x58000000, DSPACNTR);  in oaktrail_save_display_registers()
213 		PSB_WVDC32(0, DSPASURF);  in oaktrail_save_display_registers()
219 		PSB_WVDC32(0x0, PIPEACONF);  in oaktrail_save_display_registers()
224 		PSB_WVDC32(0, MRST_DPLL_A);  in oaktrail_save_display_registers()
226 	return 0;  in oaktrail_save_display_registers()
239 	struct psb_pipe *p = &regs->pipe[0];  in oaktrail_restore_display_registers()
254 	PSB_WVDC32(0x80000000, VGACNTRL);  in oaktrail_restore_display_registers()
296 	for (i = 0; i < 256; i++)  in oaktrail_restore_display_registers()
318 	} while (pp_stat & 0x08000000);  in oaktrail_restore_display_registers()
323 	} while (pp_stat & 0x10000000);  in oaktrail_restore_display_registers()
341 	return 0;  in oaktrail_restore_display_registers()
366 	return 0;  in oaktrail_power_down()
386 		if ((pwr_sts & pwr_mask) == 0)  in oaktrail_power_up()
391 	return 0;  in oaktrail_power_up()
455 	if (ret < 0)  in oaktrail_chip_setup()
464 	return 0;  in oaktrail_chip_setup()
482 	.lvds_mask = (1 << 0),
484 	.cursor_needs_phys = 0,