drm/gma500/oaktrail.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * Copyright (c) 2007-2011, Intel Corporation.
16 	u8 hblank_hi:4;
17 	u8 hactive_hi:4;
20 	u8 vblank_hi:4;
21 	u8 vactive_hi:4;
24 	u8 vsync_pulse_width_lo:4;
25 	u8 vsync_offset_lo:4;
32 	u8 height_mm_hi:4;
33 	u8 width_mm_hi:4;
48 	u32 hactive_hi:4;
50 	u32 hblank_hi:4;
58 	u16 vactive_hi:4;
60 	u16 vblank_hi:4;
61 	u16 vsync_offset_lo:4;
63 	u16 vsync_pulse_width_lo:4;
77 	u16 Panel_Backlight_Inverter_Descriptor;/* 16 bits, as follows */
78 				/* Bit 0, Frequency, 15 bits,0 - 32767Hz */
81 			/*16 bits, Defined as follows: */
83 			/* Bit 0, Type, 2 bits, */
84 			/* 0: Type-1, */
85 			/* 1: Type-2, */
86 			/* 2: Type-3, */
87 			/* 3: Type-4 */
88 			/* Bit 2, Pixel Format, 4 bits */
93 			/* Bit 6, Reserved, 2 bits, 00b */
94 			/* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */
95 			/* Bit 14, Reserved, 2 bits, 00b */
106 	u16 Panel_Backlight_Inverter_Descriptor;/*16 bits, as follows*/
107 				/*Bit 0, Frequency, 16 bits, 0 - 32767Hz*/
108 	u8 Panel_Initial_Brightness;/* [7:0] 0 - 100% */
111 			/*16 bits, Defined as follows: */
113 			/* Bit 0, Type, 2 bits, */
114 			/* 0: Type-1, */
115 			/* 1: Type-2, */
116 			/* 2: Type-3, */
117 			/* 3: Type-4 */
118 			/* Bit 2, Pixel Format, 4 bits */
123 			/* Bit 6, Reserved, 2 bits, 00b */
124 			/* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */
125 			/* Bit 14, Reserved, 2 bits, 00b */
130 		u16 NumberOfLanes:2; /*Num of Lanes, 2 bits,0 = 1 lane,*/
131 			/* 1 = 2 lanes, 2 = 3 lanes, 3 = 4 lanes. */
133 		/*3: 400MHz, 4: 500MHz, 5: 600MHz, 6: 700MHz, 7: 800MHz.*/
134 		u16 SupportedVideoTransferMode:2; /*0: Non-burst only */
135 					/* 1: Burst and non-burst */
137 		u16 HSClkBehavior:1; /*0: Continuous, 1: Non-continuous*/
141 		u16 Rsvd:5;/*5 bits,00000b */
147 	union { /*8 bits,Defined as follows: */
149 			u8 PanelType:4; /*4 bits, Bit field for panels*/
150 					/* 0 - 3: 0 = LVDS, 1 = MIPI*/
151 					/*2 bits,Specifies which of the*/
153 					/* 4 panels to use by default*/
155 					/* the 4 MIPI DSI receivers to use*/
159 	struct oaktrail_panel_descriptor_v1 panel[4];/*panel descrs,38 bytes each*/
160 	union oaktrail_panel_rx panelrx[4]; /* panel receivers*/
164 	union { /*8 bits,Defined as follows: */
166 			u8 PanelType:4; /*4 bits, Bit field for panels*/
167 					/* 0 - 3: 0 = LVDS, 1 = MIPI*/
168 					/*2 bits,Specifies which of the*/
170 					/* 4 panels to use by default*/
172 					/* the 4 MIPI DSI receivers to use*/
176 	struct oaktrail_panel_descriptor_v2 panel[4];/*panel descrs,38 bytes each*/
177 	union oaktrail_panel_rx panelrx[4]; /* panel receivers*/
192 	u8 pt; /* panel type, 4 bit field, 0=lvds, 1=mipi */