Lines Matching +full:x +full:- +full:min
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2006-2011 Intel Corporation
37 .dot = {.min = 20000, .max = 115500},
38 .vco = {.min = 1800000, .max = 3600000},
39 .n = {.min = 2, .max = 6},
40 .m = {.min = 60, .max = 160},
41 .m1 = {.min = 0, .max = 0},
42 .m2 = {.min = 58, .max = 158},
43 .p = {.min = 28, .max = 140},
44 .p1 = {.min = 2, .max = 10},
49 .dot = {.min = 20000, .max = 115500},
50 .vco = {.min = 1800000, .max = 3600000},
51 .n = {.min = 2, .max = 6},
52 .m = {.min = 60, .max = 160},
53 .m1 = {.min = 0, .max = 0},
54 .m2 = {.min = 58, .max = 158},
55 .p = {.min = 28, .max = 140},
56 .p1 = {.min = 2, .max = 10},
57 /* The single-channel range is 25-112Mhz, and dual-channel
58 * is 80-224Mhz. Prefer single channel as much as possible.
64 .dot = {.min = 20000, .max = 400000},
65 .vco = {.min = 1809000, .max = 3564000},
66 .n = {.min = 1, .max = 1},
67 .m = {.min = 67, .max = 132},
68 .m1 = {.min = 0, .max = 0},
69 .m2 = {.min = 65, .max = 130},
70 .p = {.min = 5, .max = 90},
71 .p1 = {.min = 1, .max = 9},
76 .dot = {.min = 20000, .max = 400000},
77 .vco = {.min = 1800000, .max = 3600000},
78 .n = {.min = 2, .max = 6},
79 .m = {.min = 60, .max = 160},
80 .m1 = {.min = 0, .max = 0},
81 .m2 = {.min = 58, .max = 158},
82 .p = {.min = 5, .max = 100},
83 .p1 = {.min = 1, .max = 10},
88 .dot = {.min = 160000, .max = 272000},
89 .vco = {.min = 1809000, .max = 3564000},
90 .n = {.min = 1, .max = 1},
91 .m = {.min = 67, .max = 132},
92 .m1 = {.min = 0, .max = 0},
93 .m2 = {.min = 65, .max = 130},
94 .p = {.min = 5, .max = 90},
95 .p1 = {.min = 1, .max = 9},
100 .dot = {.min = 160000, .max = 272000},
101 .vco = {.min = 1800000, .max = 3600000},
102 .n = {.min = 2, .max = 6},
103 .m = {.min = 60, .max = 164},
104 .m1 = {.min = 0, .max = 0},
105 .m2 = {.min = 58, .max = 162},
106 .p = {.min = 5, .max = 100},
107 .p1 = {.min = 1, .max = 10},
118 ret__ = -ETIMEDOUT; \
165 DRM_DEBUG_KMS("0x%08x: 0x%08x (before)\n", reg, temp); in cdv_sb_write()
166 DRM_DEBUG_KMS("0x%08x: 0x%08x\n", reg, val); in cdv_sb_write()
190 DRM_DEBUG_KMS("0x%08x: 0x%08x (after)\n", reg, temp); in cdv_sb_write()
217 int pipe = gma_crtc->pipe; in cdv_dpll_set_clock_cdv()
272 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
288 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT); in cdv_dpll_set_clock_cdv()
290 if (clock->vco < 2250000) { in cdv_dpll_set_clock_cdv()
293 } else if (clock->vco < 2750000) { in cdv_dpll_set_clock_cdv()
296 } else if (clock->vco < 3300000) { in cdv_dpll_set_clock_cdv()
312 p |= SET_FIELD(clock->p1, SB_P1_DIVIDER); in cdv_dpll_set_clock_cdv()
313 switch (clock->p2) { in cdv_dpll_set_clock_cdv()
327 DRM_ERROR("Bad P2 clock: %d\n", clock->p2); in cdv_dpll_set_clock_cdv()
328 return -EINVAL; in cdv_dpll_set_clock_cdv()
370 * Now only single-channel LVDS is supported on CDV. If it is in cdv_intel_limit()
371 * incorrect, please add the dual-channel LVDS. in cdv_intel_limit()
395 clock->m = clock->m2 + 2; in cdv_intel_clock()
396 clock->p = clock->p1 * clock->p2; in cdv_intel_clock()
397 clock->vco = (refclk * clock->m) / clock->n; in cdv_intel_clock()
398 clock->dot = clock->vco / clock->p; in cdv_intel_clock()
448 gma_crtc->clock_funcs->clock(refclk, &clock); in cdv_intel_find_dp_pll()
462 crtc = dev_priv->pipe_to_crtc_mapping[pipe]; in cdv_intel_pipe_enabled()
465 if (crtc->primary->fb == NULL || !gma_crtc->active) in cdv_intel_pipe_enabled()
474 /* Disable self-refresh before adjust WM */ in cdv_disable_sr()
483 REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/); in cdv_disable_sr()
519 if (gma_crtc->pipe == 1 && in cdv_update_wm()
534 /* enable self-refresh for single pipe active */ in cdv_update_wm()
551 dev_priv->ops->disable_sr(dev); in cdv_update_wm()
557 * or -1 if the panel fitter is not present or not in use
567 return -1; in cdv_intel_panel_fitter_pipe()
574 int x, int y, in cdv_intel_crtc_mode_set() argument
577 struct drm_device *dev = crtc->dev; in cdv_intel_crtc_mode_set()
580 int pipe = gma_crtc->pipe; in cdv_intel_crtc_mode_set()
581 const struct psb_offset *map = &dev_priv->regmap[pipe]; in cdv_intel_crtc_mode_set()
599 if (!connector->encoder in cdv_intel_crtc_mode_set()
600 || connector->encoder->crtc != crtc) in cdv_intel_crtc_mode_set()
603 ddi_select = gma_encoder->ddi_select; in cdv_intel_crtc_mode_set()
604 switch (gma_encoder->type) { in cdv_intel_crtc_mode_set()
627 if (dev_priv->dplla_96mhz) in cdv_intel_crtc_mode_set()
628 /* low-end sku, 96/100 mhz */ in cdv_intel_crtc_mode_set()
631 /* high-end sku, 27/100 mhz */ in cdv_intel_crtc_mode_set()
635 * Based on the spec the low-end SKU has only CRT/LVDS. So it is in cdv_intel_crtc_mode_set()
637 * On the high-end SKU, it will use the 27/100M reference clk in cdv_intel_crtc_mode_set()
648 if (is_lvds && dev_priv->lvds_use_ssc) { in cdv_intel_crtc_mode_set()
649 refclk = dev_priv->lvds_ssc_freq * 1000; in cdv_intel_crtc_mode_set()
650 DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq); in cdv_intel_crtc_mode_set()
655 limit = gma_crtc->clock_funcs->limit(crtc, refclk); in cdv_intel_crtc_mode_set()
657 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, in cdv_intel_crtc_mode_set()
661 adjusted_mode->clock, clock.dot); in cdv_intel_crtc_mode_set()
684 pipeconf = REG_READ(map->conf); in cdv_intel_crtc_mode_set()
688 switch (dev_priv->edp.bpp) { in cdv_intel_crtc_mode_set()
703 /* the BPC will be 6 if it is 18-bit LVDS panel */ in cdv_intel_crtc_mode_set()
722 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
723 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
740 /* Set the B0-B3 data pairs corresponding to in cdv_intel_crtc_mode_set()
742 * set the DPLLs for dual-channel mode or not. in cdv_intel_crtc_mode_set()
749 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) in cdv_intel_crtc_mode_set()
767 REG_WRITE(map->dpll, in cdv_intel_crtc_mode_set()
768 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); in cdv_intel_crtc_mode_set()
769 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
773 if (!(REG_READ(map->dpll) & DPLL_LOCK)) { in cdv_intel_crtc_mode_set()
774 dev_err(dev->dev, "Failed to get DPLL lock\n"); in cdv_intel_crtc_mode_set()
775 return -EBUSY; in cdv_intel_crtc_mode_set()
779 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock; in cdv_intel_crtc_mode_set()
780 …REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_U… in cdv_intel_crtc_mode_set()
783 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | in cdv_intel_crtc_mode_set()
784 ((adjusted_mode->crtc_htotal - 1) << 16)); in cdv_intel_crtc_mode_set()
785 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | in cdv_intel_crtc_mode_set()
786 ((adjusted_mode->crtc_hblank_end - 1) << 16)); in cdv_intel_crtc_mode_set()
787 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | in cdv_intel_crtc_mode_set()
788 ((adjusted_mode->crtc_hsync_end - 1) << 16)); in cdv_intel_crtc_mode_set()
789 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | in cdv_intel_crtc_mode_set()
790 ((adjusted_mode->crtc_vtotal - 1) << 16)); in cdv_intel_crtc_mode_set()
791 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | in cdv_intel_crtc_mode_set()
792 ((adjusted_mode->crtc_vblank_end - 1) << 16)); in cdv_intel_crtc_mode_set()
793 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | in cdv_intel_crtc_mode_set()
794 ((adjusted_mode->crtc_vsync_end - 1) << 16)); in cdv_intel_crtc_mode_set()
798 REG_WRITE(map->size, in cdv_intel_crtc_mode_set()
799 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); in cdv_intel_crtc_mode_set()
800 REG_WRITE(map->pos, 0); in cdv_intel_crtc_mode_set()
801 REG_WRITE(map->src, in cdv_intel_crtc_mode_set()
802 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); in cdv_intel_crtc_mode_set()
803 REG_WRITE(map->conf, pipeconf); in cdv_intel_crtc_mode_set()
804 REG_READ(map->conf); in cdv_intel_crtc_mode_set()
808 REG_WRITE(map->cntr, dspcntr); in cdv_intel_crtc_mode_set()
813 crtc->helper_private; in cdv_intel_crtc_mode_set()
814 crtc_funcs->mode_set_base(crtc, x, y, old_fb); in cdv_intel_crtc_mode_set()
828 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); in i8xx_clock()
829 clock->p = clock->p1 * clock->p2; in i8xx_clock()
830 clock->vco = refclk * clock->m / (clock->n + 2); in i8xx_clock()
831 clock->dot = clock->vco / clock->p; in i8xx_clock()
840 int pipe = gma_crtc->pipe; in cdv_intel_crtc_clock_get()
841 const struct psb_offset *map = &dev_priv->regmap[pipe]; in cdv_intel_crtc_clock_get()
846 struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; in cdv_intel_crtc_clock_get()
849 dpll = REG_READ(map->dpll); in cdv_intel_crtc_clock_get()
851 fp = REG_READ(map->fp0); in cdv_intel_crtc_clock_get()
853 fp = REG_READ(map->fp1); in cdv_intel_crtc_clock_get()
857 dpll = p->dpll; in cdv_intel_crtc_clock_get()
859 fp = p->fp0; in cdv_intel_crtc_clock_get()
861 fp = p->fp1; in cdv_intel_crtc_clock_get()
864 (dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN); in cdv_intel_crtc_clock_get()
878 dev_err(dev->dev, "PLL %d\n", dpll); in cdv_intel_crtc_clock_get()
918 int pipe = gma_crtc->pipe; in cdv_intel_crtc_mode_get()
920 struct psb_pipe *p = &dev_priv->regs.pipe[pipe]; in cdv_intel_crtc_mode_get()
921 const struct psb_offset *map = &dev_priv->regmap[pipe]; in cdv_intel_crtc_mode_get()
929 htot = REG_READ(map->htotal); in cdv_intel_crtc_mode_get()
930 hsync = REG_READ(map->hsync); in cdv_intel_crtc_mode_get()
931 vtot = REG_READ(map->vtotal); in cdv_intel_crtc_mode_get()
932 vsync = REG_READ(map->vsync); in cdv_intel_crtc_mode_get()
935 htot = p->htotal; in cdv_intel_crtc_mode_get()
936 hsync = p->hsync; in cdv_intel_crtc_mode_get()
937 vtot = p->vtotal; in cdv_intel_crtc_mode_get()
938 vsync = p->vsync; in cdv_intel_crtc_mode_get()
945 mode->clock = cdv_intel_crtc_clock_get(dev, crtc); in cdv_intel_crtc_mode_get()
946 mode->hdisplay = (htot & 0xffff) + 1; in cdv_intel_crtc_mode_get()
947 mode->htotal = ((htot & 0xffff0000) >> 16) + 1; in cdv_intel_crtc_mode_get()
948 mode->hsync_start = (hsync & 0xffff) + 1; in cdv_intel_crtc_mode_get()
949 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; in cdv_intel_crtc_mode_get()
950 mode->vdisplay = (vtot & 0xffff) + 1; in cdv_intel_crtc_mode_get()
951 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; in cdv_intel_crtc_mode_get()
952 mode->vsync_start = (vsync & 0xffff) + 1; in cdv_intel_crtc_mode_get()
953 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; in cdv_intel_crtc_mode_get()