Lines Matching refs:timing_base
97 unsigned int timing_base; member
117 .timing_base = 0x0,
123 .timing_base = 0x0,
129 .timing_base = 0x20000,
137 .timing_base = 0x0,
147 .timing_base = 0x20000,
159 .timing_base = 0x20000,
460 void __iomem *timing_base = ctx->regs + ctx->driver_data->timing_base; in fimd_setup_trigger() local
462 u32 val = readl(timing_base + TRIGCON); in fimd_setup_trigger()
475 writel(val, timing_base + TRIGCON); in fimd_setup_trigger()
483 void __iomem *timing_base = ctx->regs + driver_data->timing_base; in fimd_commit() local
495 writel(val, timing_base + I80IFCONFAx(0)); in fimd_commit()
498 writel(0, timing_base + I80IFCONFBx(0)); in fimd_commit()
520 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); in fimd_commit()
530 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); in fimd_commit()
540 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); in fimd_commit()
544 writel(ctx->vidout_con, timing_base + VIDOUT_CON); in fimd_commit()
574 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); in fimd_commit()
990 void *timing_base = ctx->regs + driver_data->timing_base; in fimd_trigger() local
1003 reg = readl(timing_base + TRIGCON); in fimd_trigger()
1005 writel(reg, timing_base + TRIGCON); in fimd_trigger()