Lines Matching +full:0 +full:x0000000f
7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
48 #define MMU_EXCEPTION_SLAVE_NOT_PRESENT 0x00000001
49 #define MMU_EXCEPTION_PAGE_NOT_PRESENT 0x00000002
50 #define MMU_EXCEPTION_WRITE_VIOLATION 0x00000003
51 #define MMU_EXCEPTION_OUT_OF_BOUND 0x00000004
52 #define MMU_EXCEPTION_READ_SECURITY_VIOLATION 0x00000005
53 #define MMU_EXCEPTION_WRITE_SECURITY_VIOLATION 0x00000006
54 #define VIVS_HI 0x00000000
56 #define VIVS_HI_CLOCK_CONTROL 0x00000000
57 #define VIVS_HI_CLOCK_CONTROL_CLK3D_DIS 0x00000001
58 #define VIVS_HI_CLOCK_CONTROL_CLK2D_DIS 0x00000002
59 #define VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK 0x000001fc
62 #define VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD 0x00000200
63 #define VIVS_HI_CLOCK_CONTROL_DISABLE_RAM_CLK_GATING 0x00000400
64 #define VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS 0x00000800
65 #define VIVS_HI_CLOCK_CONTROL_SOFT_RESET 0x00001000
66 #define VIVS_HI_CLOCK_CONTROL_IDLE_3D 0x00010000
67 #define VIVS_HI_CLOCK_CONTROL_IDLE_2D 0x00020000
68 #define VIVS_HI_CLOCK_CONTROL_IDLE_VG 0x00040000
69 #define VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU 0x00080000
70 #define VIVS_HI_CLOCK_CONTROL_DEBUG_PIXEL_PIPE__MASK 0x00f00000
74 #define VIVS_HI_IDLE_STATE 0x00000004
75 #define VIVS_HI_IDLE_STATE_FE 0x00000001
76 #define VIVS_HI_IDLE_STATE_DE 0x00000002
77 #define VIVS_HI_IDLE_STATE_PE 0x00000004
78 #define VIVS_HI_IDLE_STATE_SH 0x00000008
79 #define VIVS_HI_IDLE_STATE_PA 0x00000010
80 #define VIVS_HI_IDLE_STATE_SE 0x00000020
81 #define VIVS_HI_IDLE_STATE_RA 0x00000040
82 #define VIVS_HI_IDLE_STATE_TX 0x00000080
83 #define VIVS_HI_IDLE_STATE_VG 0x00000100
84 #define VIVS_HI_IDLE_STATE_IM 0x00000200
85 #define VIVS_HI_IDLE_STATE_FP 0x00000400
86 #define VIVS_HI_IDLE_STATE_TS 0x00000800
87 #define VIVS_HI_IDLE_STATE_BL 0x00001000
88 #define VIVS_HI_IDLE_STATE_ASYNCFE 0x00002000
89 #define VIVS_HI_IDLE_STATE_MC 0x00004000
90 #define VIVS_HI_IDLE_STATE_PPA 0x00008000
91 #define VIVS_HI_IDLE_STATE_WD 0x00010000
92 #define VIVS_HI_IDLE_STATE_NN 0x00020000
93 #define VIVS_HI_IDLE_STATE_TP 0x00040000
94 #define VIVS_HI_IDLE_STATE_AXI_LP 0x80000000
96 #define VIVS_HI_AXI_CONFIG 0x00000008
97 #define VIVS_HI_AXI_CONFIG_AWID__MASK 0x0000000f
98 #define VIVS_HI_AXI_CONFIG_AWID__SHIFT 0
100 #define VIVS_HI_AXI_CONFIG_ARID__MASK 0x000000f0
103 #define VIVS_HI_AXI_CONFIG_AWCACHE__MASK 0x00000f00
106 #define VIVS_HI_AXI_CONFIG_ARCACHE__MASK 0x0000f000
110 #define VIVS_HI_AXI_STATUS 0x0000000c
111 #define VIVS_HI_AXI_STATUS_WR_ERR_ID__MASK 0x0000000f
112 #define VIVS_HI_AXI_STATUS_WR_ERR_ID__SHIFT 0
114 #define VIVS_HI_AXI_STATUS_RD_ERR_ID__MASK 0x000000f0
117 #define VIVS_HI_AXI_STATUS_DET_WR_ERR 0x00000100
118 #define VIVS_HI_AXI_STATUS_DET_RD_ERR 0x00000200
120 #define VIVS_HI_INTR_ACKNOWLEDGE 0x00000010
121 #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__MASK 0x3fffffff
122 #define VIVS_HI_INTR_ACKNOWLEDGE_INTR_VEC__SHIFT 0
124 #define VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION 0x40000000
125 #define VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR 0x80000000
127 #define VIVS_HI_INTR_ENBL 0x00000014
128 #define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__MASK 0xffffffff
129 #define VIVS_HI_INTR_ENBL_INTR_ENBL_VEC__SHIFT 0
132 #define VIVS_HI_CHIP_IDENTITY 0x00000018
133 #define VIVS_HI_CHIP_IDENTITY_FAMILY__MASK 0xff000000
136 #define VIVS_HI_CHIP_IDENTITY_PRODUCT__MASK 0x00ff0000
139 #define VIVS_HI_CHIP_IDENTITY_REVISION__MASK 0x0000f000
143 #define VIVS_HI_CHIP_FEATURE 0x0000001c
145 #define VIVS_HI_CHIP_MODEL 0x00000020
147 #define VIVS_HI_CHIP_REV 0x00000024
149 #define VIVS_HI_CHIP_DATE 0x00000028
151 #define VIVS_HI_CHIP_TIME 0x0000002c
153 #define VIVS_HI_CHIP_CUSTOMER_ID 0x00000030
155 #define VIVS_HI_CHIP_MINOR_FEATURE_0 0x00000034
157 #define VIVS_HI_CACHE_CONTROL 0x00000038
159 #define VIVS_HI_MEMORY_COUNTER_RESET 0x0000003c
161 #define VIVS_HI_PROFILE_READ_BYTES8 0x00000040
163 #define VIVS_HI_PROFILE_WRITE_BYTES8 0x00000044
165 #define VIVS_HI_CHIP_SPECS 0x00000048
166 #define VIVS_HI_CHIP_SPECS_STREAM_COUNT__MASK 0x0000000f
167 #define VIVS_HI_CHIP_SPECS_STREAM_COUNT__SHIFT 0
169 #define VIVS_HI_CHIP_SPECS_REGISTER_MAX__MASK 0x000000f0
172 #define VIVS_HI_CHIP_SPECS_THREAD_COUNT__MASK 0x00000f00
175 #define VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE__MASK 0x0001f000
178 #define VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT__MASK 0x01f00000
181 #define VIVS_HI_CHIP_SPECS_PIXEL_PIPES__MASK 0x0e000000
184 #define VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE__MASK 0xf0000000
188 #define VIVS_HI_PROFILE_WRITE_BURSTS 0x0000004c
190 #define VIVS_HI_PROFILE_WRITE_REQUESTS 0x00000050
192 #define VIVS_HI_PROFILE_READ_BURSTS 0x00000058
194 #define VIVS_HI_PROFILE_READ_REQUESTS 0x0000005c
196 #define VIVS_HI_PROFILE_READ_LASTS 0x00000060
198 #define VIVS_HI_GP_OUT0 0x00000064
200 #define VIVS_HI_GP_OUT1 0x00000068
202 #define VIVS_HI_GP_OUT2 0x0000006c
204 #define VIVS_HI_AXI_CONTROL 0x00000070
205 #define VIVS_HI_AXI_CONTROL_WR_FULL_BURST_MODE 0x00000001
207 #define VIVS_HI_CHIP_MINOR_FEATURE_1 0x00000074
209 #define VIVS_HI_PROFILE_TOTAL_CYCLES 0x00000078
211 #define VIVS_HI_PROFILE_IDLE_CYCLES 0x0000007c
213 #define VIVS_HI_CHIP_SPECS_2 0x00000080
214 #define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__MASK 0x000000ff
215 #define VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE__SHIFT 0
217 #define VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT__MASK 0x0000ff00
220 #define VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS__MASK 0xffff0000
224 #define VIVS_HI_CHIP_MINOR_FEATURE_2 0x00000084
226 #define VIVS_HI_CHIP_MINOR_FEATURE_3 0x00000088
228 #define VIVS_HI_CHIP_SPECS_3 0x0000008c
229 #define VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT__MASK 0x000001f0
232 #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__MASK 0x00000007
233 #define VIVS_HI_CHIP_SPECS_3_GPU_CORE_COUNT__SHIFT 0
236 #define VIVS_HI_COMPRESSION_FLAGS 0x00000090
237 #define VIVS_HI_COMPRESSION_FLAGS_DEC300 0x00000040
239 #define VIVS_HI_CHIP_MINOR_FEATURE_4 0x00000094
241 #define VIVS_HI_CHIP_SPECS_4 0x0000009c
242 #define VIVS_HI_CHIP_SPECS_4_STREAM_COUNT__MASK 0x0001f000
246 #define VIVS_HI_CHIP_MINOR_FEATURE_5 0x000000a0
248 #define VIVS_HI_CHIP_PRODUCT_ID 0x000000a8
250 #define VIVS_HI_BLT_INTR 0x000000d4
252 #define VIVS_HI_CHIP_ECO_ID 0x000000e8
254 #define VIVS_HI_AUXBIT 0x000000ec
256 #define VIVS_PM 0x00000000
258 #define VIVS_PM_POWER_CONTROLS 0x00000100
259 #define VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING 0x00000001
260 #define VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING 0x00000002
261 #define VIVS_PM_POWER_CONTROLS_DISABLE_STARVE_MODULE_CLOCK_GATING 0x00000004
262 #define VIVS_PM_POWER_CONTROLS_TURN_ON_COUNTER__MASK 0x000000f0
265 #define VIVS_PM_POWER_CONTROLS_TURN_OFF_COUNTER__MASK 0xffff0000
269 #define VIVS_PM_MODULE_CONTROLS 0x00000104
270 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_FE 0x00000001
271 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_DE 0x00000002
272 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE 0x00000004
273 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH 0x00000008
274 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA 0x00000010
275 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE 0x00000020
276 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA 0x00000040
277 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX 0x00000080
278 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH_EU 0x00000400
279 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ 0x00010000
280 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ 0x00020000
281 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_NN 0x00400000
283 #define VIVS_PM_MODULE_STATUS 0x00000108
284 #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_FE 0x00000001
285 #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_DE 0x00000002
286 #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_PE 0x00000004
287 #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_SH 0x00000008
288 #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_PA 0x00000010
289 #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_SE 0x00000020
290 #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_RA 0x00000040
291 #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_TX 0x00000080
293 #define VIVS_PM_PULSE_EATER 0x0000010c
294 #define VIVS_PM_PULSE_EATER_DISABLE 0x00000001
295 #define VIVS_PM_PULSE_EATER_DVFS_PERIOD__MASK 0x0000ff00
298 #define VIVS_PM_PULSE_EATER_UNK16 0x00010000
299 #define VIVS_PM_PULSE_EATER_UNK17 0x00020000
300 #define VIVS_PM_PULSE_EATER_INTERNAL_DFS 0x00040000
301 #define VIVS_PM_PULSE_EATER_UNK19 0x00080000
302 #define VIVS_PM_PULSE_EATER_UNK20 0x00100000
303 #define VIVS_PM_PULSE_EATER_UNK22 0x00400000
304 #define VIVS_PM_PULSE_EATER_UNK23 0x00800000
306 #define VIVS_MMUv2 0x00000000
308 #define VIVS_MMUv2_SAFE_ADDRESS 0x00000180
310 #define VIVS_MMUv2_CONFIGURATION 0x00000184
311 #define VIVS_MMUv2_CONFIGURATION_MODE__MASK 0x00000001
312 #define VIVS_MMUv2_CONFIGURATION_MODE__SHIFT 0
313 #define VIVS_MMUv2_CONFIGURATION_MODE_MODE4_K 0x00000000
314 #define VIVS_MMUv2_CONFIGURATION_MODE_MODE1_K 0x00000001
315 #define VIVS_MMUv2_CONFIGURATION_MODE_MASK 0x00000008
316 #define VIVS_MMUv2_CONFIGURATION_FLUSH__MASK 0x00000010
318 #define VIVS_MMUv2_CONFIGURATION_FLUSH_FLUSH 0x00000010
319 #define VIVS_MMUv2_CONFIGURATION_FLUSH_MASK 0x00000080
320 #define VIVS_MMUv2_CONFIGURATION_ADDRESS_MASK 0x00000100
321 #define VIVS_MMUv2_CONFIGURATION_ADDRESS__MASK 0xfffffc00
325 #define VIVS_MMUv2_STATUS 0x00000188
326 #define VIVS_MMUv2_STATUS_EXCEPTION0__MASK 0x0000000f
327 #define VIVS_MMUv2_STATUS_EXCEPTION0__SHIFT 0
329 #define VIVS_MMUv2_STATUS_EXCEPTION1__MASK 0x000000f0
332 #define VIVS_MMUv2_STATUS_EXCEPTION2__MASK 0x00000f00
335 #define VIVS_MMUv2_STATUS_EXCEPTION3__MASK 0x0000f000
339 #define VIVS_MMUv2_CONTROL 0x0000018c
340 #define VIVS_MMUv2_CONTROL_ENABLE 0x00000001
342 #define VIVS_MMUv2_EXCEPTION_ADDR(i0) (0x00000190 + 0x4*(i0))
343 #define VIVS_MMUv2_EXCEPTION_ADDR__ESIZE 0x00000004
344 #define VIVS_MMUv2_EXCEPTION_ADDR__LEN 0x00000004
346 #define VIVS_MMUv2_PROFILE_BLT_READ 0x000001a4
348 #define VIVS_MMUv2_PTA_CONFIG 0x000001ac
349 #define VIVS_MMUv2_PTA_CONFIG_INDEX__MASK 0x0000ffff
350 #define VIVS_MMUv2_PTA_CONFIG_INDEX__SHIFT 0
352 #define VIVS_MMUv2_PTA_CONFIG_UNK16 0x00010000
354 #define VIVS_MMUv2_AXI_POLICY(i0) (0x000001c0 + 0x4*(i0))
355 #define VIVS_MMUv2_AXI_POLICY__ESIZE 0x00000004
356 #define VIVS_MMUv2_AXI_POLICY__LEN 0x00000008
358 #define VIVS_MMUv2_SEC_EXCEPTION_ADDR 0x00000380
360 #define VIVS_MMUv2_SEC_STATUS 0x00000384
361 #define VIVS_MMUv2_SEC_STATUS_EXCEPTION0__MASK 0x00000003
362 #define VIVS_MMUv2_SEC_STATUS_EXCEPTION0__SHIFT 0
364 #define VIVS_MMUv2_SEC_STATUS_EXCEPTION1__MASK 0x00000030
367 #define VIVS_MMUv2_SEC_STATUS_EXCEPTION2__MASK 0x00000300
370 #define VIVS_MMUv2_SEC_STATUS_EXCEPTION3__MASK 0x00003000
374 #define VIVS_MMUv2_SEC_CONTROL 0x00000388
375 #define VIVS_MMUv2_SEC_CONTROL_ENABLE 0x00000001
377 #define VIVS_MMUv2_PTA_ADDRESS_LOW 0x0000038c
379 #define VIVS_MMUv2_PTA_ADDRESS_HIGH 0x00000390
381 #define VIVS_MMUv2_PTA_CONTROL 0x00000394
382 #define VIVS_MMUv2_PTA_CONTROL_ENABLE 0x00000001
384 #define VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW 0x00000398
386 #define VIVS_MMUv2_SEC_SAFE_ADDR_LOW 0x0000039c
388 #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG 0x000003a0
389 #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__MASK 0x000000ff
390 #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_NON_SEC_SAFE_ADDR_HIGH__SHIFT 0
392 #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_UNK15 0x00008000
393 #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_SEC_SAFE_ADDR_HIGH__MASK 0x00ff0000
396 #define VIVS_MMUv2_SAFE_ADDRESS_CONFIG_UNK31 0x80000000
398 #define VIVS_MMUv2_SEC_COMMAND_CONTROL 0x000003a4
399 #define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__MASK 0x0000ffff
400 #define VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH__SHIFT 0
402 #define VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE 0x00010000
404 #define VIVS_MMUv2_AHB_CONTROL 0x000003a8
405 #define VIVS_MMUv2_AHB_CONTROL_RESET 0x00000001
406 #define VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS 0x00000002
408 #define VIVS_MC 0x00000000
410 #define VIVS_MC_MMU_FE_PAGE_TABLE 0x00000400
412 #define VIVS_MC_MMU_TX_PAGE_TABLE 0x00000404
414 #define VIVS_MC_MMU_PE_PAGE_TABLE 0x00000408
416 #define VIVS_MC_MMU_PEZ_PAGE_TABLE 0x0000040c
418 #define VIVS_MC_MMU_RA_PAGE_TABLE 0x00000410
420 #define VIVS_MC_DEBUG_MEMORY 0x00000414
421 #define VIVS_MC_DEBUG_MEMORY_SPECIAL_PATCH_GC320 0x00000008
422 #define VIVS_MC_DEBUG_MEMORY_FAST_CLEAR_BYPASS 0x00100000
423 #define VIVS_MC_DEBUG_MEMORY_COMPRESSION_BYPASS 0x00200000
425 #define VIVS_MC_MEMORY_BASE_ADDR_RA 0x00000418
427 #define VIVS_MC_MEMORY_BASE_ADDR_FE 0x0000041c
429 #define VIVS_MC_MEMORY_BASE_ADDR_TX 0x00000420
431 #define VIVS_MC_MEMORY_BASE_ADDR_PEZ 0x00000424
433 #define VIVS_MC_MEMORY_BASE_ADDR_PE 0x00000428
435 #define VIVS_MC_MEMORY_TIMING_CONTROL 0x0000042c
437 #define VIVS_MC_MEMORY_FLUSH 0x00000430
439 #define VIVS_MC_PROFILE_CYCLE_COUNTER 0x00000438
441 #define VIVS_MC_DEBUG_READ0 0x0000043c
443 #define VIVS_MC_DEBUG_READ1 0x00000440
445 #define VIVS_MC_DEBUG_WRITE 0x00000444
447 #define VIVS_MC_PROFILE_RA_READ 0x00000448
449 #define VIVS_MC_PROFILE_TX_READ 0x0000044c
451 #define VIVS_MC_PROFILE_FE_READ 0x00000450
453 #define VIVS_MC_PROFILE_PE_READ 0x00000454
455 #define VIVS_MC_PROFILE_DE_READ 0x00000458
457 #define VIVS_MC_PROFILE_SH_READ 0x0000045c
459 #define VIVS_MC_PROFILE_PA_READ 0x00000460
461 #define VIVS_MC_PROFILE_SE_READ 0x00000464
463 #define VIVS_MC_PROFILE_MC_READ 0x00000468
465 #define VIVS_MC_PROFILE_HI_READ 0x0000046c
467 #define VIVS_MC_PROFILE_CONFIG0 0x00000470
468 #define VIVS_MC_PROFILE_CONFIG0_FE__MASK 0x000000ff
469 #define VIVS_MC_PROFILE_CONFIG0_FE__SHIFT 0
470 #define VIVS_MC_PROFILE_CONFIG0_FE_DRAW_COUNT 0x0000000a
471 #define VIVS_MC_PROFILE_CONFIG0_FE_OUT_VERTEX_COUNT 0x0000000b
472 #define VIVS_MC_PROFILE_CONFIG0_FE_CACHE_MISS_COUNT 0x0000000c
473 #define VIVS_MC_PROFILE_CONFIG0_FE_RESET 0x0000000f
474 #define VIVS_MC_PROFILE_CONFIG0_FE_CACHE_LK_COUNT 0x00000010
475 #define VIVS_MC_PROFILE_CONFIG0_FE_STALL_COUNT 0x00000011
476 #define VIVS_MC_PROFILE_CONFIG0_FE_PROCESS_COUNT 0x00000012
477 #define VIVS_MC_PROFILE_CONFIG0_DE__MASK 0x0000ff00
479 #define VIVS_MC_PROFILE_CONFIG0_DE_RESET 0x00000f00
480 #define VIVS_MC_PROFILE_CONFIG0_PE__MASK 0x00ff0000
482 #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_COLOR_PIPE 0x00000000
483 #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_KILLED_BY_DEPTH_PIPE 0x00010000
484 #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_COLOR_PIPE 0x00020000
485 #define VIVS_MC_PROFILE_CONFIG0_PE_PIXEL_COUNT_DRAWN_BY_DEPTH_PIPE 0x00030000
486 #define VIVS_MC_PROFILE_CONFIG0_PE_PIXELS_RENDERED_2D 0x000b0000
487 #define VIVS_MC_PROFILE_CONFIG0_PE_RESET 0x000f0000
488 #define VIVS_MC_PROFILE_CONFIG0_SH__MASK 0xff000000
490 #define VIVS_MC_PROFILE_CONFIG0_SH_SHADER_CYCLES 0x04000000
491 #define VIVS_MC_PROFILE_CONFIG0_SH_PS_INST_COUNTER 0x07000000
492 #define VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_PIXEL_COUNTER 0x08000000
493 #define VIVS_MC_PROFILE_CONFIG0_SH_VS_INST_COUNTER 0x09000000
494 #define VIVS_MC_PROFILE_CONFIG0_SH_RENDERED_VERTICE_COUNTER 0x0a000000
495 #define VIVS_MC_PROFILE_CONFIG0_SH_VTX_BRANCH_INST_COUNTER 0x0b000000
496 #define VIVS_MC_PROFILE_CONFIG0_SH_VTX_TEXLD_INST_COUNTER 0x0c000000
497 #define VIVS_MC_PROFILE_CONFIG0_SH_PXL_BRANCH_INST_COUNTER 0x0d000000
498 #define VIVS_MC_PROFILE_CONFIG0_SH_PXL_TEXLD_INST_COUNTER 0x0e000000
499 #define VIVS_MC_PROFILE_CONFIG0_SH_RESET 0x0f000000
501 #define VIVS_MC_PROFILE_CONFIG1 0x00000474
502 #define VIVS_MC_PROFILE_CONFIG1_PA__MASK 0x000000ff
503 #define VIVS_MC_PROFILE_CONFIG1_PA__SHIFT 0
504 #define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_VTX_COUNTER 0x00000003
505 #define VIVS_MC_PROFILE_CONFIG1_PA_INPUT_PRIM_COUNTER 0x00000004
506 #define VIVS_MC_PROFILE_CONFIG1_PA_OUTPUT_PRIM_COUNTER 0x00000005
507 #define VIVS_MC_PROFILE_CONFIG1_PA_DEPTH_CLIPPED_COUNTER 0x00000006
508 #define VIVS_MC_PROFILE_CONFIG1_PA_TRIVIAL_REJECTED_COUNTER 0x00000007
509 #define VIVS_MC_PROFILE_CONFIG1_PA_CULLED_COUNTER 0x00000008
510 #define VIVS_MC_PROFILE_CONFIG1_PA_DROPED_PRIM_COUNTER 0x00000009
511 #define VIVS_MC_PROFILE_CONFIG1_PA_FRUSTUM_CLIPPED_PRIM_COUNTER 0x0000000a
512 #define VIVS_MC_PROFILE_CONFIG1_PA_RESET 0x0000000f
513 #define VIVS_MC_PROFILE_CONFIG1_SE__MASK 0x0000ff00
515 #define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_TRIANGLE_COUNT 0x00000000
516 #define VIVS_MC_PROFILE_CONFIG1_SE_CULLED_LINES_COUNT 0x00000100
517 #define VIVS_MC_PROFILE_CONFIG1_SE_TRIVIAL_REJECTED_LINE_COUNT 0x00000400
518 #define VIVS_MC_PROFILE_CONFIG1_SE_RESET 0x00000f00
519 #define VIVS_MC_PROFILE_CONFIG1_RA__MASK 0x00ff0000
521 #define VIVS_MC_PROFILE_CONFIG1_RA_VALID_PIXEL_COUNT 0x00000000
522 #define VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_QUAD_COUNT 0x00010000
523 #define VIVS_MC_PROFILE_CONFIG1_RA_VALID_QUAD_COUNT_AFTER_EARLY_Z 0x00020000
524 #define VIVS_MC_PROFILE_CONFIG1_RA_TOTAL_PRIMITIVE_COUNT 0x00030000
525 #define VIVS_MC_PROFILE_CONFIG1_RA_PIPE_CACHE_MISS_COUNTER 0x00090000
526 #define VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_CACHE_MISS_COUNTER 0x000a0000
527 #define VIVS_MC_PROFILE_CONFIG1_RA_CULLED_QUAD_COUNT 0x000b0000
528 #define VIVS_MC_PROFILE_CONFIG1_RA_RESET 0x000f0000
529 #define VIVS_MC_PROFILE_CONFIG1_RA_PIPE_HZ_CACHE_MISS_COUNTER 0x00110000
530 #define VIVS_MC_PROFILE_CONFIG1_RA_PREFETCH_HZ_CACHE_MISS_COUNTER 0x00120000
531 #define VIVS_MC_PROFILE_CONFIG1_TX__MASK 0xff000000
533 #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_BILINEAR_REQUESTS 0x00000000
534 #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TRILINEAR_REQUESTS 0x01000000
535 #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_DISCARDED_TEXTURE_REQUESTS 0x02000000
536 #define VIVS_MC_PROFILE_CONFIG1_TX_TOTAL_TEXTURE_REQUESTS 0x03000000
537 #define VIVS_MC_PROFILE_CONFIG1_TX_UNKNOWN 0x04000000
538 #define VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_COUNT 0x05000000
539 #define VIVS_MC_PROFILE_CONFIG1_TX_MEM_READ_IN_8B_COUNT 0x06000000
540 #define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_COUNT 0x07000000
541 #define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_HIT_TEXEL_COUNT 0x08000000
542 #define VIVS_MC_PROFILE_CONFIG1_TX_CACHE_MISS_TEXEL_COUNT 0x09000000
543 #define VIVS_MC_PROFILE_CONFIG1_TX_RESET 0x0f000000
545 #define VIVS_MC_PROFILE_CONFIG2 0x00000478
546 #define VIVS_MC_PROFILE_CONFIG2_MC__MASK 0x000000ff
547 #define VIVS_MC_PROFILE_CONFIG2_MC__SHIFT 0
548 #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_PIPELINE 0x00000001
549 #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_IP 0x00000002
550 #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_PIPELINE 0x00000003
551 #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_SENTOUT_FROM_COLORPIPE 0x00000004
552 #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_FROM_COLORPIPE 0x00000005
553 #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_DEPTHPIPE 0x00000007
554 #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_SENTOUT_FROM_DEPTHPIPE 0x00000008
555 #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_DEPTHPIPE 0x00000009
556 #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_SENTOUT_FROM_DEPTHPIPE 0x0000000a
557 #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_FROM_DEPTHPIPE 0x0000000b
558 #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_8B_FROM_OTHERS 0x0000000c
559 #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_8B_FROM_OTHERS 0x0000000d
560 #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_READ_REQ_FROM_OTHERS 0x0000000e
561 #define VIVS_MC_PROFILE_CONFIG2_MC_TOTAL_WRITE_REQ_FROM_OTHERS 0x0000000f
562 #define VIVS_MC_PROFILE_CONFIG2_MC_FE_READ_BANDWIDTH 0x00000015
563 #define VIVS_MC_PROFILE_CONFIG2_MC_MMU_READ_BANDWIDTH 0x00000016
564 #define VIVS_MC_PROFILE_CONFIG2_MC_BLT_READ_BANDWIDTH 0x00000017
565 #define VIVS_MC_PROFILE_CONFIG2_MC_SH0_READ_BANDWIDTH 0x00000018
566 #define VIVS_MC_PROFILE_CONFIG2_MC_SH1_READ_BANDWIDTH 0x00000019
567 #define VIVS_MC_PROFILE_CONFIG2_MC_PE_WRITE_BANDWIDTH 0x0000001a
568 #define VIVS_MC_PROFILE_CONFIG2_MC_BLT_WRITE_BANDWIDTH 0x0000001b
569 #define VIVS_MC_PROFILE_CONFIG2_MC_SH0_WRITE_BANDWIDTH 0x0000001c
570 #define VIVS_MC_PROFILE_CONFIG2_MC_SH1_WRITE_BANDWIDTH 0x0000001d
571 #define VIVS_MC_PROFILE_CONFIG2_HI__MASK 0x0000ff00
573 #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_READ_REQUEST_STALLED 0x00000000
574 #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_REQUEST_STALLED 0x00000100
575 #define VIVS_MC_PROFILE_CONFIG2_HI_AXI_CYCLES_WRITE_DATA_STALLED 0x00000200
576 #define VIVS_MC_PROFILE_CONFIG2_HI_RESET 0x00000f00
577 #define VIVS_MC_PROFILE_CONFIG2_L2__MASK 0x00ff0000
579 #define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_AXI0_READ_REQUEST_COUNT 0x00000000
580 #define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_AXI0_WRITE_REQUEST_COUNT 0x00040000
581 #define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_AXI1_WRITE_REQUEST_COUNT 0x00050000
582 #define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_READ_TRANSACTIONS_REQUEST_BY_AXI0 0x00080000
583 #define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_READ_TRANSACTIONS_REQUEST_BY_AXI1 0x00090000
584 #define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_WRITE_TRANSACTIONS_REQUEST_BY_AXI0 0x000c0000
585 #define VIVS_MC_PROFILE_CONFIG2_L2_TOTAL_WRITE_TRANSACTIONS_REQUEST_BY_AXI1 0x000d0000
586 #define VIVS_MC_PROFILE_CONFIG2_L2_RESET 0x000f0000
587 #define VIVS_MC_PROFILE_CONFIG2_L2_AXI0_MINMAX_LATENCY 0x00100000
588 #define VIVS_MC_PROFILE_CONFIG2_L2_AXI0_TOTAL_LATENCY 0x00110000
589 #define VIVS_MC_PROFILE_CONFIG2_L2_AXI0_TOTAL_REQUEST_COUNT 0x00120000
590 #define VIVS_MC_PROFILE_CONFIG2_L2_AXI1_MINMAX_LATENCY 0x00130000
591 #define VIVS_MC_PROFILE_CONFIG2_L2_AXI1_TOTAL_LATENCY 0x00140000
592 #define VIVS_MC_PROFILE_CONFIG2_L2_AXI1_TOTAL_REQUEST_COUNT 0x00150000
593 #define VIVS_MC_PROFILE_CONFIG2_BLT__MASK 0xff000000
595 #define VIVS_MC_PROFILE_CONFIG2_BLT_UNK0 0x00000000
597 #define VIVS_MC_PROFILE_CONFIG3 0x0000047c
599 #define VIVS_MC_BUS_CONFIG 0x00000480
600 #define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK 0x0000000f
601 #define VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__SHIFT 0
603 #define VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK 0x000000f0
607 #define VIVS_MC_START_COMPOSITION 0x00000554
609 #define VIVS_MC_FLAGS 0x00000558
610 #define VIVS_MC_FLAGS_128B_MERGE 0x00000001
611 #define VIVS_MC_FLAGS_TPCV11_COMPRESSION 0x08000000
613 #define VIVS_MC_L2_CACHE_CONFIG 0x0000055c
615 #define VIVS_MC_PROFILE_L2_READ 0x00000564
617 #define VIVS_MC_MC_LATENCY_RESET 0x00000568
619 #define VIVS_MC_MC_AXI_MAX_MIN_LATENCY 0x0000056c
621 #define VIVS_MC_MC_AXI_TOTAL_LATENCY 0x00000570
623 #define VIVS_MC_MC_AXI_SAMPLE_COUNT 0x00000574
625 #define VIVS_DEC400EX 0x00000000
627 #define VIVS_DEC400EX_UNK00800 0x00000800
629 #define VIVS_DEC400EX_UNK00808 0x00000808